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JPS5336147A - Circuit for designating mos memory address - Google Patents

Circuit for designating mos memory address

Info

Publication number
JPS5336147A
JPS5336147A JP10977477A JP10977477A JPS5336147A JP S5336147 A JPS5336147 A JP S5336147A JP 10977477 A JP10977477 A JP 10977477A JP 10977477 A JP10977477 A JP 10977477A JP S5336147 A JPS5336147 A JP S5336147A
Authority
JP
Japan
Prior art keywords
designating
circuit
memory address
mos memory
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10977477A
Other languages
Japanese (ja)
Other versions
JPS6032279B2 (en
Inventor
Hofuman Riyuudeigaa
Fuon Batsuse Pauruuerunaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPS5336147A publication Critical patent/JPS5336147A/en
Publication of JPS6032279B2 publication Critical patent/JPS6032279B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4082Address Buffers; level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4087Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/02Shaping pulses by amplifying
    • H03K5/023Shaping pulses by amplifying using field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
JP52109774A 1976-09-15 1977-09-12 MOS memory address designation circuit Expired JPS6032279B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2641524A DE2641524B1 (en) 1976-09-15 1976-09-15 Arrangement for addressing a MOS memory
DE2641524.7 1976-09-15

Publications (2)

Publication Number Publication Date
JPS5336147A true JPS5336147A (en) 1978-04-04
JPS6032279B2 JPS6032279B2 (en) 1985-07-26

Family

ID=5987981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52109774A Expired JPS6032279B2 (en) 1976-09-15 1977-09-12 MOS memory address designation circuit

Country Status (4)

Country Link
JP (1) JPS6032279B2 (en)
DE (1) DE2641524B1 (en)
FR (1) FR2365179A1 (en)
GB (1) GB1588183A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413289A (en) * 1988-05-06 1989-01-18 Nec Corp Decoder circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100206598B1 (en) * 1995-12-29 1999-07-01 김영환 Word line drive
KR101412460B1 (en) * 2012-05-21 2014-07-01 주식회사 뉴핫맥스 Industrial oven heater

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902082A (en) * 1974-02-11 1975-08-26 Mostek Corp Dynamic data input latch and decoder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413289A (en) * 1988-05-06 1989-01-18 Nec Corp Decoder circuit
JPH0434235B2 (en) * 1988-05-06 1992-06-05 Nippon Electric Co

Also Published As

Publication number Publication date
DE2641524B1 (en) 1977-11-17
JPS6032279B2 (en) 1985-07-26
FR2365179B1 (en) 1983-05-13
FR2365179A1 (en) 1978-04-14
DE2641524C2 (en) 1978-07-13
GB1588183A (en) 1981-04-15

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