Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/50—Physical imperfections
  • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
  • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

• the field of the invention is that of devices based on semiconductor material III-V, such as for example GaN. This type of material is of particular interest for applications of electronic components that can be high-power transistors or diodes.
• semiconductor materials III-V are materials composed of one or more elements of column III (boron, gallium, aluminum, indium, etc.) and column V (arsenic, antimony, phosphorus, etc.). ) of the periodic table of Mendeleev, such as gallium arsenide, indium arsenide, gallium nitride.
• the present invention relates more specifically to devices comprising materials III-N for example GaN, AlGaN, or all alloys AlxGayln ( -x - y ) N with x and y between 0 and 1 inclusive.
• the Applicant has demonstrated the effect of surface defects related to the nature of type III-N material and in particular GaN, such as so-called "inverted pyramid” type defects on the breakdown voltage of a device using this type of material.
• FIG. 1 illustrates the type of "inverted pyramid” type defect thanks to an electron microscopy image still commonly referred to as "SEM” for “Scanning Electron Microscopy", of a GaN material which has been grown from an Si substrate.
• SEM scanning Electron Microscopy
• FIG. 2 illustrates the evolution of the breakdown voltage as a function of the surface of a device and the number of surface defects that it comprises for a GaN material which has been grown from an Si substrate. .
• Other research teams have demonstrated the harmful effect of such defects and in particular have described such defects in GaN on silicon substrates: SL Selvaraj, T. Suzue, Egawa T., Applied Physics Express 2, p1 1 1005 (2009)),
• CMP Certical Mechanical Planarization
• Chemical Mechanical Polishing is a process of smoothing and planarizing surfaces combining chemical and mechanical actions (a mixture of etching chemical and mechanical polishing to free abrasive). Mechanical lapping alone causes too much damage to surfaces and wet etching alone does not provide good planarization. The chemical reactions being isotropic, they attack the materials indifferently in all directions.
• the "CMP” process combines both effects at the same time;
• the Applicant proposes a solution for filling crystallographic surface defects that may be of "inverted pyramid" type in III-N materials, to prevent these defects have an impact on the devices incorporating them.
• the subject of the present invention is a method of manufacturing a device comprising at least one layer made of a semiconductor material III-N having surface defects of crystallographic growth and a substrate, said process comprising:
• a barrier layer of a second material III-N on the surface of a layer made of a first III-N semiconductor material, said second III-N material having a gap between the valence band and the conduction band; more important than the gap between the valence band and the conduction band of said first material III-N;
• This barrier layer is deposited conformably to the layer of a first material that can be considered as the main layer.
• the barrier layer may have a thickness of a few tens of nanometers.
• the contact may be an ohmic contact and / or a contact
• the material III-N can meet the formula
• the deposition of the dielectric layer is a deposition conforming to the surface of the layer of semiconductor material of material III-N, it makes it possible to fill the surface defects, in order to make contacts which support the fact of possibly being positioned on it. look.
• This layer is intended to withstand a voltage that can be applied between a surface contact and the substrate.
• the surface defects may typically be of the "inverted pyramid" type, which may have sizes of the order of one micron.
• the method comprises depositing a first passivation layer in a first dielectric material and depositing a second layer of a second dielectric material.
• the method further comprises depositing a third layer of a third dielectric material.
• the method comprises an operation of selective etching of a dielectric material with respect to another dielectric material.
• the first dielectric material is identical to the third dielectric material.
• the semiconductor material is GaN or AIGaN or AlN.
• the barrier layer may typically have a thickness of the order of a few tens of nanometers.
• the main layer may typically have a thickness of several microns, for example 2 microns.
• the second semiconductor material is AIGaN or AlN, the first material being GaN.
• the dielectric material or materials are chosen from the following materials: SiO x , AlN, Al 2 O 3 , SiN y .
• the first dielectric layer is SiN
• the second dielectric layer is Si0 2 .
• the first dielectric layer is SiN
• the second dielectric layer is Si0 2
• the third dielectric layer is SiN.
• the dielectric material layer or the set of layers of dielectric materials has a thickness greater than one micron, the defect can typically have a defect depth of the order of 800 nm.
• the substrate is made of silicon.
• the substrate is separated from the layer of a III-N semiconductor material by at least one buffer layer.
• the thickness of the buffer layer may be of the order of several microns. It can also have a thickness of 2 microns, or 5 to 6 microns, the thickness of the so-called main layer being of the same order.
• the substrate is made of silicon
• a set of buffer layers comprises a nucleation layer of AlN, then one or more layers of GaN, or AIGaN, or AlN, or other buffer layers on the basis of materials.
• III-N the material of the layer made of a semiconductor material being GaN.
• the layer (s) of dielectric material (s) is (are) produced by a low-pressure chemical vapor deposition (LPCVD) operation.
• LPCVD low-pressure chemical vapor deposition
• the layer (s) of dielectric material (s) is (are) produced by an atomic thin film deposition (ALD) operation.
• ALD atomic thin film deposition
• the layer (s) of dielectric material (s) is (are) produced by an operation of chemical vapor deposition of organometallic (MOCVD).
• the layer (s) of dielectric material (s) is (are) produced by a plasma enhanced chemical vapor deposition (PECVD) operation.
• PECVD plasma enhanced chemical vapor deposition
• the invention also relates to the device obtained according to the method of the present invention.
• the invention also relates to a method for manufacturing a transistor comprising the method of the invention and also to the object of the transistor obtained by said method of manufacturing said transistor.
• the invention also relates to a method of manufacturing a diode comprising the method of the invention and also to the diode object obtained by said method of manufacturing said diode.
• FIG. 1 illustrates the image of a defect of the "inverted pyramid” type produced by electron microscopy, still commonly referred to as “SEM” for “Scanning Electron Microscopy”;
• FIG. 2 illustrates the evolution of the breakdown voltage as a function of the surface of a device and the number of surface defects it comprises;
• FIG. 3 illustrates simulations produced by the Applicant which show that with a GaN layer on a Si substrate showing the effect of "inverted pyramid" type defects on the generated electric fields;
• FIG. 4 illustrates the evolution of the "inverted pyramid" type of defect density as a function of wafer curvature, both of which are typically modified by the quality of the GaN layers;
• FIG. 5 schematizes a structure of a device comprising a substrate, for example made of silicon, a layer of GaN semiconductor material having surface defects of the "inverted pyramid" type, of the prior art;
• FIGS. 6a to 6f illustrate the main steps of a method of manufacturing a device according to the invention
• FIG. 7 illustrates a transistor obtained according to the method of the invention.
• the method of the present invention addresses the manufacture of devices comprising a layer of III-N material having surface defects resulting from its crystalline growth, this layer being intended to support a contact. It may be an ohmic contact and / or a Schottky contact. The impact of such faults is illustrated below in the context of a transistor.
• FIG. 5 thus schematizes a device of the prior art comprising a substrate, for example made of silicon 10, a buffer layer 20, a layer 30 of GaN semiconductor material having surface defects of the "inverted pyramid" type, a dielectric layer 40 a contact 50, said dielectric is not located in the defect at the contact (and conferring a structural difference with respect to the device obtained according to the method of the invention).
• This figure highlights the problem generated by the surface defect represented by a "flash" E and illustrating a problem of premature breakdown. Typically with a voltage of 600V, this phenomenon can be observed with a total thickness structure of 3.6 ⁇ (1.8 ⁇ of buffer layer 20 and 1.8 ⁇ of GaN layer 30). Indeed, the electric field is high around the defect, which will lead to premature failure.
• the method of the invention relates to the production of a device comprising at least one layer of material III-N that can in particular be on the surface of a silicon substrate, and limiting.
• an intermediate layer is produced on the surface of the silicon substrate in order to then make the layer of III-N material.
• this layer may be AIN or AIGaN, it may also be a set of buffer layers having different stoichiometries of the same alloy, without limitation
• the set of layers may typically comprise a total thickness of between 100 nm and 10 ⁇ .
• the surface defects present in the layer of material III-N are filled with at least one dielectric.
• the Applicant hereinafter describes an example comprising the successive deposits of several dielectric materials so as to be able to benefit from selective etching behaviors, thus making it possible to master very well the stopping of the etching operation.
• a layer 301 of GaN material is produced on the surface of a set 200 of AlN and AlGaN buffer layers, themselves made on the surface of a Si substrate 100, as illustrated in FIG. 6a.
• a barrier layer 302 which may be made of AIGaN or AlN or other variants of III-V materials and has a gap greater than that of the GaN material, is produced in a standard manner on the surface of the GaN layer.
• the barrier layer may typically have a thickness of between 3 nm and 50 nm, the thickness of the GaN layer being typically between 100 nm and 6 ⁇ m.
• a lower layer 401 of SiN with a thickness of between 10 nm and 10,000 nm, preferably between 100 nm and 200 nm
• the "inverted pyramid" type defects are thus filled by SiN of Si0 2 and SiN.
• the lower layer 401 in SiN makes it possible to ensure very good control of the stop of the etching of the layer 402 of Si0 2 .
• the upper layer 403 of SiN is thick. All the thicknesses must make it possible to fill the defects to their full depth.
• the minimum thickness of the layers and in particular that of the intermediate layer of SiO 2 is dependent on the variations in thickness induced by the thinning process of the upper layer 403.
• the removal by CMP of 1 ⁇ of these layers can induce variations in their thickness of the order of +/- 70 nm (+ / - ⁇ ) - These variations in thickness removed cause certain areas of the barrier layer (for example oxide Si0 2 ) to be reached before the other zones during the CMP process.
• CMP Chemical Mechanical Planarization
• the minimum thickness of the barrier layer (e ar -min) is:
• the layer underlying the barrier layer is not partially thinned.
• e ox > (V ox / V ni t) ⁇ ⁇ ⁇ . If we consider a nitride film with a mean thickness of 1 ⁇ , an average thickness removed of 1 ⁇ , a non-homogeneity of removal of +/- 70 nm, an oxide removal rate of 200 nm / min and a nitride removal rate of 50 nm / min, a minimum thickness of the barrier layer of 280 nm is calculated.
• the "CMP" type operation is performed to obtain a flat surface, free from surface defects, as illustrated in FIG. 6c, which shows that the layer 402 is used as a stop layer of the CMP operation.
• a selective etching step is then carried out to remove the remaining SiO 2 .
• the layers 401, 402 and 403 are locally removed as shown in FIG. 6e. More precisely, the layer 401 is etched into SiN in the zone in which the ohmic contacts will be formed.
• the layer 402 for example of SiO 2, is etched directly before the etching of the SiN layer 401 with either wet etching or dry etching.
• the ohmic contact is made.
• the dielectric is well present in the defects, as illustrated by zone Z in FIG. 6f and the metal 500 can be deposited on it. Since the holes formed by the defects generally occupy a very small percentage of the total area, filling them with one or more dielectric materials does not modify the conduction behavior of the entire device.
• the dielectric (s) avoids (s) premature failure because there is no increased electric field at the point of the defect.
• the electric field goes around the defect. Unlike the phenomenon illustrated in Figure 5, in which case, the electric field is high around the defect, which will cause premature failure.
• Atomic Layer Deposition is a process for the deposition of atomic thin films. The principle consists of exposing a surface successively to different chemical precursors in order to obtain ultra-thin layers. It is used in the semiconductor industry. The interest of the ALD technique is to be able to make a monolayer on a surface having a very strong aspect ratio (depressions and bumps). Notably because the CVD reaction takes place directly on the surface, on a monolayer of adsorbed precursor gases
• MOCVD Organometallic vapor phase epitaxy (EPVOM), also known as MOVPE (metalorganic vapor phase epitaxy or MOCVD - metalorganic chemical vapor deposition, a more general term) is a crystalline growth technique in which the elements to be deposited, in the form of organometallic compounds or hydrides, are fed to the monocrystalline substrate by a carrier gas.
• PECVD Plasma-Enhanced Chemical Vapor Deposition (PECVD) is a process used to deposit thin layers on a substrate from a gaseous (vapor) state. Chemical reactions take place during the process after the formation of a plasma from the reactor gases. Plasma is generally created from this gas by an electric discharge that can be generated from radio frequency sources (13.56 MHz), microwaves (2.45 GHz) or by a continuous electrical discharge between two electrodes.
• the LPCVD process may be favored, the ALD process being slower, the PECVD process being of lower quality, and the MOCVD process being more rare for SiN or SiO 2.
• the "inverted pyramid" type surface defects occupy a very small proportion of the surface area of the III-INI material layer (less than 1/1 ⁇ 10 6 at a density of 1 / mm 2 ), they can be filled with at least one insulating dielectric, in order to stop these defects affecting the breakdown voltage, which contributes to greatly increase the efficiency of large devices such as GaN on silicon wafers.
• the production of components such as power transistors comprises the deposition of a dielectric layer on the surface of the layers based on material III-N
• the method of the present invention thus remains in this type of technological sector, since it comprises a similar step of deposition of thicker dielectric (of the order of 150 nm for example without use of CMP process at this stage). This then has no effect on the fragility of the wafer (unlike thick layers of GaN or AIGaN that would be attacked by a "CMP" process).
• FIG. 7 illustrates an exemplary transistor of the invention comprising a substrate 100 made of silicon, a set of buffer layers 200, a layer 301 of GaN, a barrier layer 302 made of AIGaN, a passivation dielectric layer 400, an ohmic contact (source) 501, a gate 502 and an ohmic contact (drain) 503.

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• Engineering & Computer Science (AREA)
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• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Junction Field-Effect Transistors (AREA)
• Formation Of Insulating Films (AREA)
• Electrodes Of Semiconductors (AREA)

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