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FR3060837B1 - Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface - Google Patents

Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface Download PDF

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Publication number
FR3060837B1
FR3060837B1 FR1662492A FR1662492A FR3060837B1 FR 3060837 B1 FR3060837 B1 FR 3060837B1 FR 1662492 A FR1662492 A FR 1662492A FR 1662492 A FR1662492 A FR 1662492A FR 3060837 B1 FR3060837 B1 FR 3060837B1
Authority
FR
France
Prior art keywords
layer
iii
manufacturing
materials
surface defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1662492A
Other languages
English (en)
Other versions
FR3060837A1 (fr
Inventor
Matthew Charles
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1662492A priority Critical patent/FR3060837B1/fr
Priority to PCT/EP2017/082283 priority patent/WO2018108840A1/fr
Priority to EP17822597.5A priority patent/EP3555924A1/fr
Publication of FR3060837A1 publication Critical patent/FR3060837A1/fr
Application granted granted Critical
Publication of FR3060837B1 publication Critical patent/FR3060837B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/57—Physical imperfections the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un dispositif comprenant au moins une couche en un matériau semiconducteur III-N présentant des défauts surfaciques de croissance cristallographique et un substrat, ledit procédé comprenant : - le dépôt d'au moins une couche de diélectrique à la surface de ladite couche de matériau semiconducteur en matériau III-N ; - une opération de gravure « CMP » définissant un ensemble de matériaux ; - la réalisation d'au moins un contact à la surface dudit ensemble de matériaux. Le dispositif peut être un transistor. Le procédé peut avantageusement comprendre plusieurs dépôts de matériaux diélectriques pouvant être du SiN et du SiO2.
FR1662492A 2016-12-15 2016-12-15 Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface Expired - Fee Related FR3060837B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1662492A FR3060837B1 (fr) 2016-12-15 2016-12-15 Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface
PCT/EP2017/082283 WO2018108840A1 (fr) 2016-12-15 2017-12-11 Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface
EP17822597.5A EP3555924A1 (fr) 2016-12-15 2017-12-11 Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1662492A FR3060837B1 (fr) 2016-12-15 2016-12-15 Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface
FR1662492 2016-12-15

Publications (2)

Publication Number Publication Date
FR3060837A1 FR3060837A1 (fr) 2018-06-22
FR3060837B1 true FR3060837B1 (fr) 2019-05-10

Family

ID=58054315

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1662492A Expired - Fee Related FR3060837B1 (fr) 2016-12-15 2016-12-15 Procede de fabrication d'un dispositif comprenant une couche de materiau iii-n avec des defauts de surface

Country Status (3)

Country Link
EP (1) EP3555924A1 (fr)
FR (1) FR3060837B1 (fr)
WO (1) WO2018108840A1 (fr)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6805614B2 (en) * 2000-11-30 2004-10-19 Texas Instruments Incorporated Multilayered CMP stop for flat planarization
US7795630B2 (en) * 2003-08-07 2010-09-14 Panasonic Corporation Semiconductor device with oxidized regions and method for fabricating the same
US8178427B2 (en) * 2009-03-31 2012-05-15 Commissariat A. L'energie Atomique Epitaxial methods for reducing surface dislocation density in semiconductor materials
JP5306904B2 (ja) * 2009-05-28 2013-10-02 シャープ株式会社 窒化物半導体発光ダイオード素子およびその製造方法
US20110221039A1 (en) * 2010-03-12 2011-09-15 Sinmat, Inc. Defect capping for reduced defect density epitaxial articles
CN102487111B (zh) * 2010-12-04 2014-08-27 展晶科技(深圳)有限公司 半导体发光芯片制造方法
FR2969815B1 (fr) * 2010-12-27 2013-11-22 Soitec Silicon On Insulator Tech Procédé de fabrication d'un dispositif semi-conducteur

Also Published As

Publication number Publication date
EP3555924A1 (fr) 2019-10-23
WO2018108840A1 (fr) 2018-06-21
FR3060837A1 (fr) 2018-06-22

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