Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
  • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
  • C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
  • C09J5/02—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving pretreatment of the surfaces to be joined
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
  • C09J5/00—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers
  • C09J5/06—Adhesive processes in general; Adhesive processes not provided for elsewhere, e.g. relating to primers involving heating of the applied adhesive
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
• • C—CHEMISTRY; METALLURGY
  • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
  • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
  • C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
  • C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors

Definitions

• the invention relates to a method for assembling a first substrate and a second substrate, the assembly being intended for use in the fields of energy, optoelectronics, and microelectronics.
• Figure 1 shows an assembly method known from the state of the art and described by Shiro Uchida et al. [1] which comprises the following steps:
• a heterostructure 4 comprising an assembly interface 3 between the first face and the second face, is obtained.
• the cleaning step c) comprises cleaning in an alkaline solution.
• this method provides removal of the native oxides on said first and second faces before the assembly step e).
• step d), argon ion beam bombardment activation, and assembly step e) are performed in the same high vacuum chamber ("high vacuum chamber"). According to the English terminology), and at a pressure of less than 10 ⁇ 5 Pa. The maintenance of such a vacuum throughout these two steps then prevents the re-growth of native oxide on the first and second faces after step d), activation by bombardment with an argon ion beam.
• argon ion beam bombardment activation increases the risk of particulate abrasive contamination of the surfaces of the indium phosphide and gallium arsenide 2 substrates to be contacted.
• ion beam bombardment activation degrades crystalline quality near the surface of substrates subjected to this treatment.
• thermocompression it has also been proposed to perform the assembly step e) by thermocompression.
• thermocompression assembly requires the implementation of heavy equipment and expensive.
• thermocompression assembly is generally performed at high temperature, under a low oxygen environment, and requires the application of an external mechanical pressure on the substrates during said assembly step,. These operating conditions also limit production rates and are not always compatible with the requirements of the microelectronics, or optronics industries.
• heterostructures comprising a stack of indium phosphide and gallium arsenide having a low electrical and thermal resistance at the bonding interface is of great interest in the fields of energy, optoelectronics and microelectronics.
• substrates of indium phosphide 1 on gallium arsenide 2 are well adapted to form epitaxially grown junctions for transforming light energy into electrical energy.
• An object of the invention is therefore to propose a method for assembling, at ambient temperature and without recourse to the application of an external mechanical pressure, a substrate comprising a first crystalline indium phosphide face with a substrate. crystalline to obtain a low electrical and / or thermal interface resistivity, and compatible with the requirements of the microelectronics industry in terms of costs, production rates and ease of implementation.
• step d subjecting the assembly, formed in step d), to a heat treatment.
• ambient temperature is meant a temperature between 15 ° C and 25 ° C, preferably between 18 ° C and 22 ° C, for example 20 ° C.
• the Applicant has found that the method implemented according to the invention does not require performing an ion beam bombardment, or even a high vacuum to perform the step d) assembly, and allows despite all to obtain electrical resistivity and / or thermal interface sufficiently low.
• the formation of the intermediate layer on the second substrate makes it possible to perform the assembly step in an atmosphere having a pressure greater than 10 -4 Pa, preferably greater than 10 ⁇ 3 Pa.
• step d) can be performed under a moderate vacuum, the production rates are not penalized, unlike the known method of the state of the art.
• the process according to the invention makes it possible to obtain heterostructures that can not be obtained according to the assembly methods known from the prior art.
• the process according to the invention makes it possible to obtain heterostructures comprising crystalline indium phosphide on a silicon substrate.
• the first face and the second face of the second substrate are monocrystalline, and the intermediate layer is formed in a coherent growth mode.
• a coherent growth mode makes it possible to obtain a monocrystalline intermediate layer.
• the formation of the intermediate layer by a coherent growth mode prevents or reduces the generation of crystal defects, such as dislocations, in said intermediate layer.
• This advantageously allows to maintain a roughness of the exposed surface of the relatively low intermediate layer and therefore compatible with a direct bonding step.
• an absence or a reduced number of crystalline defects is very favorable for the realization of an assembly interface having low electrical, thermal and optical resistivities, and in particular limiting carrier recombinations at the bonding interface. . Consequently, obtaining an intermediate layer in a coherent growth mode makes it possible to further reduce the electrical and thermal resistivities of the interface interface formed by the first face and the intermediate layer, and to limit the recombinations of carriers at this interface.
• this configuration is particularly advantageous when monocrystalline structures are required.
• the heat treatment step e) is adapted to allow at least partial connection of the crystal lattices to the interface formed by the first face and the intermediate layer.
• connection at least partial crystalline networks at the interface formed by the assembly of the first face and the intermediate layer.
• connection, at least partially, crystalline networks is made possible monocrystalline character of the first face and the intermediate layer.
• the at least partial connection of the crystal lattices is also a factor for improving the electrical, thermal and optical resistivities of the assembly interface.
• step d) is performed according to one of the following conditions: under an atmosphere having a partial pressure in water of less than 10 1 Pa,
• the partial vacuum having a pressure of less than 10 Pa, preferably less than 1 Pa, still more preferably less than
• this mode of implementation has the advantage of reducing the amount of water present at the bonding interface during step d).
• step c) of formation of the intermediate layer is carried out by an epitaxial process, advantageously by MOCVD.
• the heat treatment step e) is carried out at a temperature of between 200 ° C. and 600 ° C., preferably between 300 ° C. and 600 ° C., even more preferentially between 300 ° C. and 500 ° C.
• step d), of direct bonding is preceded by a step c), of preparing the exposed surface of the intermediate layer and of the first face, step c) being adapted to preserve the crystallinity of the intermediate layer and the first face.
• step c1) is also adapted to make the exposed surface of the intermediate layer and the first face hydrophilic.
• the second layer has a thickness of less than 5 nm, preferably less than 2 nm.
• the first substrate is indium phosphide, advantageously monoblock.
• the second substrate comprises at least one of the following materials: gallium arsenide, silicon, silicon and germanium alloy, germanium, sapphire, alumina, silicon carbide, alloy of elements III and V.
• FIG. 1 is a schematic representation of the process for manufacturing the heterostructure 4 according to a method known from the prior art
• FIGS. 2a and 2b are diagrammatic representations of a step of the assembly method according to the first embodiment of the invention.
• FIG. 3 is a schematic representation of a step of the assembly method according to the first embodiment of the invention.
• FIG. 4 is a schematic representation of a step of the assembly method according to the first embodiment of the invention.
• FIG. 5 is a graph representing, along the ordinate axis, the electrical resistivity (in mOhm.cm 2 ) of assemblies as a function of the temperature (in ° C.) of heat treatment given along the abscissa axis;
• FIG. 6 is a graph representing, according to the ordinate axis, the bonding energy of assemblies (in mJ.m 2 ) as a function of the temperature (in ° C) of heat treatment given along the axis of the abscissa
• FIG. 7 is an image obtained by transmission electron microscope of the assembly interface formed according to the invention.
• FIG. 8 is a schematic representation of the assembly method according to a second embodiment of the invention.
• Indium Phosphide means any alloy with the following chemical formula: lni- x (Eiii) x Pi-y (Ev) y, Em and Ev being, respectively, elements of column III and column V of the periodic table of elements, and with x and y less than 0.5, preferably less than 0.2, more preferably less than 0.05.
• the indium phosphide may also comprise doping elements, for example sulfur, iron or silicon.
• Coherent growth mode coherent growth mode of a layer is understood to mean the epitaxial growth of a monocrystalline layer on a monocrystalline substrate, and for which the monocrystalline layer has a thickness less than its critical thickness.
• the layer having a thickness less than its critical thickness, is in mesh with the substrate.
• the monocrystalline layer has the same mesh parameter as the substrate at any point in its volume. Therefore, the monocrystalline layer may be constrained.
• a monocrystalline layer, having a thickness greater than its critical thickness will relax (“relaxation” according to the Anglo-Saxon terminology) its internal stresses so as to recover its natural mesh parameter. This relaxation phenomenon is accompanied by the generation of dislocation dislocations mesh ("misfit dislocations" according to the English terminology), as well as a degradation (increase) roughness of the exposed surface of the epitaxial layer.
• Monobloc substrate by monoblock substrate is meant a substrate having a chemical composition essentially identical at any point in its volume.
• the assembly method comprises a step a) of providing a first substrate 10.
• the first substrate 10 comprises a first face 11.
• the first face 11 is made of crystalline indium phosphide, advantageously the indium phosphide is monocrystalline.
• the roughness of the first face 11 is adapted to direct bonding.
• the roughness of the first face 11 is less than 1 nm RMS ("RMS” being the abbreviation of "Root Mean Square"), preferably less than 0.5 nm RMS, and very preferably less than 0.3 nm RMS, measured by atomic force microscopy ("Atomic Force Microscopy" according to the English terminology), and according to a measuring field of 5 ⁇ x 5 ⁇ .
• the first substrate 10 may comprise a support substrate 10a on which a crystalline indium phosphide layer 10b rests.
• the exposed surface of the crystalline indium phosphor layer 10b, advantageously monocrystalline, is then the first face 11.
• the indium phosphide layer 10b may have a thickness of between 0.2 nm and 5 nm, preferably less than 2 nm.
• the first face 11 has the chemical composition InP.
• the support substrate 10a can comprise at least one of the materials chosen from: indium phosphide, gallium arsenide, silicon, germanium silicon alloy, germanium, sapphire, alumina, silicon carbide, alloy of elements III and V.
• the support substrate 10a may comprise indium phosphide.
• the first substrate 10 may be a monoblock indium phosphide substrate ("bulk” according to the Anglo-Saxon terminology).
• the support substrate 10a can be laminated and comprise a stack of layers of functional semiconductor materials, such as junctions, diodes, tunnel diodes.
• the assembly method comprises a step b) which comprises providing a second substrate 20.
• the second substrate 20 comprises a second crystalline face 21 different from the indium phosphide.
• the chemical composition of the substrate 20 does not correspond to the chemical formula of the indium phosphide given in definition.
• the second substrate 20 may, for example, comprise at least one of the materials: gallium arsenide, silicon, silicon and germanium alloy, germanium, sapphire, alumina, silicon carbide, alloy of elements III and V.
• the second substrate 20 may be laminated and comprise a stack of layers of functional semiconductor materials, such as junctions, diodes, tunnel diodes
• the process according to the invention comprises a step c), represented in FIG. 3, which comprises the formation of a crystalline intermediate layer (by crystalline means, polycrystalline or monocrystalline) formed on the second face 21, also called front face 21, the second substrate 20.
• the intermediate layer 22 is made of crystalline indium phosphide.
• the formation of the intermediate layer 22 may be preceded by a step of preparing the second face 21 so as to reduce its roughness and / or deoxidize it.
• the skilled person is able to determine the conditions for reducing the roughness and / or deoxidize a surface, and can in this regard refer to reference [3] cited at the end of the description.
• the intermediate layer 22 will be polycrystalline if it is formed on a second face 21 also polycrystalline.
• the second face 21 of the second substrate 20 and the intermediate layer 22 are monocrystalline.
• the intermediate layer 22 is formed by epitaxy in a coherent growth mode.
• an intermediate layer 22 of indium phosphide on a gallium arsenide substrate by metalorganic chemical vapor deposition ("MOCVD” or “Metalorganic Chemical Vapor Deposition” according to English terminology. Saxon).
• the intermediate layer 22 can thus be formed using triethylindium (Teln) or trimethylindium (TMIn) and PH3 as precursor gases, under a working pressure of between 50 and 150 mbar, for example 100 mbar, and at a temperature of between 500 and 700 ° C, preferably between 500 and 600 ° C, for example 550 ° C.
• the thickness of the intermediate layer 22 of indium phosphide formed on a gallium arsenide substrate is less than 5 nm, according to the model described by Matthews et al. [2]. It is also possible to form the intermediate layer 22 by other techniques known to those skilled in the art such as: liquid phase epitaxy ("Liquid Phase Epitaxy” according to the Anglo-Saxon terminology), jet epitaxy Molecular Beam Epitaxy (Anglo-Saxon terminology), spraying, plasma-assisted chemical deposition ("Plasma Enhanced Chemical Vapor Deposition” in Anglo-Saxon terminology), laser ablation (“Pulsed Laser Deposition "according to Anglo-Saxon terminology).
• the intermediate layer 22 may have a thickness of less than 5 nm, preferably less than 2 nm.
• the defectivity (dislocations, surface roughness) of the intermediate layer 22 is relatively low.
• the intermediate layer 22 formed by epitaxy in a coherent growth mode, retains its constraint. Therefore, there is no generation of dislocations in the intermediate layer 22, and the roughness of the exposed surface of said intermediate layer 22 is not degraded.
• the roughness of the exposed surface of the intermediate layer 22 is suitable for direct bonding.
• the roughness of the exposed surface of the intermediate layer 22 is less than 1 nm RMS, preferably less than 0.5 nm RMS, measured by atomic force microscopy, and according to a measurement field of 5 ⁇ ⁇ 5 ⁇ .
• the intermediate layer 22 may have the chemical composition InP.
• the intermediate layer 22 may be thicker than desired after its formation. It is then possible to adapt its thickness by a thinning step. Said thinning step may be carried out by dry or wet etching according to techniques well known to those skilled in the art, and may consult the reference [3] cited at the end of the description.
• the method according to the invention comprises a step d), represented in FIG. 4, which comprises a step of direct bonding of the first face 11 of the first substrate 10 with the exposed surface of the intermediate layer 22.
• step d comprises a step of direct bonding of the first face 11 of the first substrate 10 with the exposed surface of the intermediate layer 22.
• the first face 11 and the exposed surface of the intermediate layer 22 are brought into contact, more particularly in intimate contact, so that they can adhere to one another.
• the assembly step d) is carried out at ambient temperature and without applying external mechanical pressure.
• the assembly step d) does not require the implementation of a non-thermocompression assembly.
• ambient temperature is meant a temperature of between 15 ° C. and 25 ° C., preferably between 18 ° C. and 22 ° C., for example 20 ° C.
• Said assembly 30 comprises the intermediate layer 22 interposed between the first substrate 10 and the second substrate 20.
• Step d) direct bonding is performed under an atmosphere having a pressure greater than 10 ⁇ 4 Pa, preferably greater than 10 ⁇ 3 Pa.
• Step d) direct bonding can be performed at atmospheric pressure.
• a bonding wave is initiated by means of a mechanical pressure exerted at a point on one of the two substrates 10 and 20 to assemble.
• the step d) of direct bonding is carried out under a humidity controlled atmosphere, namely an atmosphere having a low moisture content.
• step d) of direct bonding under a humidity controlled atmosphere can be performed under an atmosphere having a partial pressure of water less than 10 1 Pa.
• step d) of direct bonding is performed in a closed chamber, in which the humidity level is controlled.
• the humidity level can be controlled by controlling the dew point in the gluing chamber.
• the moisture content can be controlled by the implementation of a molecular sieve to ensure a dew point temperature of about -90 ° C and a water content of less than lppm in a chamber at atmospheric pressure (which corresponds to a partial pressure of water less than 0.1 Pa for a total pressure equal to atmospheric pressure).
• step d) of bonding under a controlled humidity atmosphere can be carried out under a partial vacuum, the partial vacuum having a pressure of less than 10 Pa, preferably less than 1 Pa, still more preferably less than 10 1 Pa.
• a wave Bonding initiates and propagates spontaneously so that the first face 11 and the intermediate layer 22 bond to each other by direct molecular adhesion.
• the first and second alternatives mentioned above have the advantage of reducing the amount of water present at the bonding interface during step d). Thus, little or no reaction products will be observed at the assembly interface, thus preventing degradation of the electrical, thermal and / or optical properties of the assemblies 30 thus formed.
• step d a heat treatment step e), preferably under a neutral atmosphere, for example under Argon, is carried out.
• a neutral atmosphere for example under Argon
• Step e) is intended to reinforce the bonding interface of the assembly 30.
• the heat treatment step e) can be carried out at a temperature of between 200 ° C. and 600 ° C.
• the first face 11 and the second face 21 are monocrystalline, and the intermediate layer 22 is formed in a coherent growth mode (it is therefore also monocrystalline).
• the heat treatment step e) can be adapted to allow the connection, at least partially, of the crystal lattices to the interface formed by the first face 11 and the layer Intermediate 22.
• electrical and thermal resistivities are further reduced.
• this configuration is particularly well suited when a structure comprising a monocrystalline indium phosphide substrate on a second monocrystalline substrate is required.
• the electrical resistivity of the bonding interface of the assembly comprises a monocrystalline intermediate layer (thus formed in a coherent growth mode), which is less than at 10 mQ.cm 2 .
• the order of 18 atm / cm 3 (eg sulfur atoms) is of the order of 5 m ⁇ .cm 2 , after a heat treatment step performed at 200 ° C. Bonding an InP substrate to GaAs requires heat treatment performed at at least 500 ° C to achieve an equivalent electrical resistivity level.
• the intermediate layer 22 comprises a doping, for example N type, and concentration greater than 10 18 atm / cm 3 , preferably greater than 5 x 10 18 atm / cm 3 .
• a heat treatment performed at a temperature below 600 ° C. limits the deformation of the assembly which may be caused by the differences in coefficient of thermal expansion ("CTE” or "coefficient of thermal expansion” according to the English terminology). Saxon) of the first and second substrates.
• CTE coefficient of thermal expansion
• Saxon coefficient of thermal expansion
• the heat treatment step can be carried out at a temperature between 300 ° C and 600 ° C.
• the bonding energy of an assembly 30 is greater than 600 mJ.m 2 after heat treatment of said assembly 30 carried out at a temperature above 300 ° C.
• the heat treatment step can be carried out at a temperature of between 300 ° C and 500 ° C.
• a heat treatment performed at 500 ° C makes it possible to observe a connection of the crystal lattices of the first face 11 and of the intermediate layer 22 (illustrated in FIG. 7).
• step d), of direct bonding is preceded by a step c1), of preparing the exposed surface of the intermediate layer 22, and of the first face 11.
• step c1) The preparation of the exposed surface of the intermediate layer 22, and of the first face 11 during step c1) can also be adapted to make them compatible with a direct bonding step performed at ambient temperature and without application of a external mechanical pressure.
• step c1) can also be intended to make the exposed surface of the intermediate layer 22, and the first face 11 hydrophilic.
• Step c1) is also adapted to preserve the roughness of the exposed surface of the intermediate layer (22) and the first face (11).
• the roughness of the exposed surface of the intermediate layer (22) and the first face (11) are not affected at the end of step c1). More particularly, the roughness of the exposed surface of the intermediate layer (22) and the first face (11) will be preserved during step c1).
• Step c1) may comprise deoxidation and / or passivation of the exposed surface of the intermediate layer 22 and the first face 11.
• Step c1) is adapted to preserve the crystallinity of the intermediate layer 22 and the first face 11.
• Step c1) may comprise dry etching or wet etching.
• Those skilled in the art are able to determine the conditions and the compounds adapted to perform step c1), and in this regard may consult the reference [3] cited at the end of the description.
• a step c1) carried out wet may comprise the use of a chemical solution comprising at least one of the elements:
• the aforementioned chemical solution makes it possible to remove / etch the native oxides which may be present on the first face 11 and the exposed surface of the intermediate layer 22, as well as to passivate said surfaces.
• the surface preparation step c1) can be carried out by a radical oxidation step of the first face 11 and of the exposed surface of the intermediate layer 22.
• the radical oxide formed on each of the aforementioned faces has the advantage of disappearing at least partially in step e) of heat treatment.
• the radical oxide thus has the advantage of protecting the surfaces to be assembled, and especially to allow a step d), direct bonding, without having to manage the waiting time between the different steps.
• the radical oxidation can be carried out under an atmosphere of ozone and / or oxygen illuminated by ultraviolet radiation.
• the ultraviolet radiation may comprise primary wavelengths preferably of the order of 185 nm and 254 nm (for example radiation from a low pressure mercury vapor lamp).
• the surrounding oxygen can be used as an oxidizing species, but the latter can be substituted by ozone.
• a 1.8 nm thick free radical oxide layer can be generated on indium phosphide for an exposure time of 3 minutes.
• a first application of this first embodiment makes it possible to form an InP assembly on silicon.
• the first application comprises the supply of a monocrystalline substrate of InP chemical composition and a silicon substrate.
• An InP chemical intermediate layer, 2 nm thick, is then formed on the silicon substrate in a coherent growth mode.
• the formation of the intermediate layer is carried out by MOCVD at a temperature of 550 ° C., under a pressure of 100 mbar, with PH3 and Teln as precursor gases.
• the assembly step is then carried out under partial vacuum at an atmospheric pressure of less than 10 1 Pa, and is followed by a heat treatment step at 500 ° C for 2 hours.
• an assembly of InP on silicon is obtained, with an assembly interface having a reduced defectivity, and electrical, thermal and optical properties improved compared to what is known from the state of the art.
• a second application of this first embodiment makes it possible to form an InP assembly on GaAs.
• This second mode of application differs from the first mode of application in that the second substrate is a monocrystalline GaAs substrate.
• FIG. 8 which differs from the first embodiment in that a step a2) is performed before step e), and a step f) after step e).
• Step a2) comprises the formation of an embrittlement zone 12 in the first substrate 10.
• the weakening zone 12 is substantially parallel to the first face 11.
• the embrittlement zone 12 and the first face 11 delimit a useful layer 13.
• the useful layer 13, as described below, is intended to be transferred to the exposed surface of the intermediate layer 22.
• the weakening zone 12 may be formed by implantation of gaseous species through the first face 11, and at a depth defined by the implantation energy of said species.
• the implanted species may comprise at least one of the elements included in the list: H, He.
• the weakening zone 12 is formed by implantation of hydrogen, at an energy of 10OKeV, and at a dose of 6.5 x 10 16 atm / cm 2 , in a first substrate 10 made of phosphide d 'indium.
• an embrittlement zone is formed at a distance of about 900 nm from the first face 11, thus delimiting a useful layer 13, for example 800 nm thick.
• a fracture step f) is performed after the assembly step e).
• the fracture step comprises the initiation and the propagation of a fracture wave within the weakening zone 12 so that the first substrate 10 is detached from the useful layer 13, and thus enables the transfer of said useful layer. 13 on the exposed surface of the intermediate layer 22.
• Step f) can be carried out by heat treatment, for example a treatment comprising a rise in temperature.
• the heat treatment is carried out under an inert atmosphere, for example under argon, at a temperature of between 150 ° C. and 300 ° C., and a duration of between 30 minutes and 3 hours.
• an inert atmosphere for example under argon
• a heterogeneous assembly step unlike the method according to the invention, generates an interface having no connection and therefore defects likely to degrade the electrical and thermal conduction properties, but also the optical properties, for example transparency.
• the optical properties of the bonding interface directly affect the performance of the devices, in particular photovoltaic cells, intended to be manufactured in or on the heterostructures obtained according to the invention.

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• 2015
  • 2015-11-09 FR FR1560721A patent/FR3043406B1/fr not_active Expired - Fee Related
• 2016
  • 2016-11-07 WO PCT/EP2016/076806 patent/WO2017080944A1/fr active Application Filing
  • 2016-11-07 EP EP16795267.0A patent/EP3374460A1/de not_active Withdrawn
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