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EP0007579B1 - Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière - Google Patents

Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière Download PDF

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Publication number
EP0007579B1
EP0007579B1 EP79102540A EP79102540A EP0007579B1 EP 0007579 B1 EP0007579 B1 EP 0007579B1 EP 79102540 A EP79102540 A EP 79102540A EP 79102540 A EP79102540 A EP 79102540A EP 0007579 B1 EP0007579 B1 EP 0007579B1
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EP
European Patent Office
Prior art keywords
signal
state
microprocessor
microprocessors
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP79102540A
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German (de)
English (en)
Other versions
EP0007579A1 (fr
Inventor
Heinrich Dipl.-Ing. Brunner
Peter Drebinger
Peter Dr. Höhne
Johann Hoisl
Günter Kochanowski
Walter Dipl.-Ing. Wimmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT79102540T priority Critical patent/ATE1305T1/de
Publication of EP0007579A1 publication Critical patent/EP0007579A1/fr
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Publication of EP0007579B1 publication Critical patent/EP0007579B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/097—Supervising of traffic control systems, e.g. by giving an alarm if two crossing streets have green light simultaneously

Definitions

  • the invention relates to a circuit arrangement for monitoring the state of signal systems, in particular road traffic light signal systems, with a logic circuit for the target-actual comparison of signal state signals which are derived from the individual signal transmitters of the signal system, and with at least one of the Logic circuit influenced evaluation device, which causes the signal system to switch on or off in the event of a fault.
  • Such a circuit arrangement is known, for example, from US Pat. No. 3,902,156.
  • the logic circuit is constructed from a number of logic elements which are connected to the respective signal transmitters by wiring. A change or extension of the signal system therefore requires a change in the wiring.
  • the object of the invention is to design a circuit arrangement of the type mentioned at the outset in such a way that the signal states occurring in a signaling system can be monitored reliably without any wiring work being necessary when adapting to changed circumstances or when expanding the monitored signaling system, and thereby thereby there is no deterioration in the operational safety of the monitoring circuit itself.
  • the solution to this problem results from the fact that two microprocessors operating in parallel are provided as the logic circuit, that an evaluation device is connected downstream of each of the microprocessors, that switching means of the two evaluation devices signaling a fault state are connected in series to a monitoring circuit for monitoring the signaling system are inserted that each output of each microprocessor connected to an evaluation device is connected to a control input of the other microprocessor, and that a further output of each microprocessor emitting test signals is connected to the inputs of the other microprocessor provided for receiving the signal status signals , and that the mutual control of the microprocessors takes place in such a way that the test signals are fed to the microprocessor in question during the pauses of the pulse-shaped signal state signals.
  • the signal states to be monitored change, e.g. in adaptation to changed circumstances or as a result of an expansion of the signal system, it is now sufficient to only use one e.g. to store the desired signal states of the memory, which is part of the microprocessors, to be replaced by another memory, and the use of two microprocessors operating in parallel, which mutually control one another, also ensures that faults occurring in one of the microprocessors do not have any admissible values Can pretend signal states.
  • the presence of an impermissible signal state of the signal generator of the signal system can be determined from the correspondence of a signal state signal with a stored signal, which further increases the operational reliability of the circuit arrangement because an impermissible operating state is determined by a positive test result.
  • the circuit arrangement shown in the figure is used to monitor the state of a signal system, in particular a road traffic light system.
  • This signal system includes a number of signal transmitters which, in the present case, not only emit the actual signaling signals, but also signals corresponding to their signal states, that is to say signal-state signals.
  • These signal status signals can either be emitted by the signal generators themselves or by signaling elements connected to these signal generators.
  • These detectors can be voltage detectors or current detectors.
  • the status signals emitted by the signal generators or by the signaling elements assigned to them occur at connections Ea1 to Ean and Eb1 to Ebn shown in the figure.
  • connections Ea1 to Ean and Eb1 to Ebn shown in the figure.
  • two groups of corresponding connections are provided in the present case, connections of both groups of connections corresponding to one another being supplied in each case with signal signals corresponding to one another or status signals associated with them. This means that the signal states of the individual signal transmitters are recorded redundantly.
  • Any group of Connections Ea1 to Ean or Eb1 to Ebn, it has at least as many connections as signal transmitters and / or the associated reporting elements are provided within the signal system to be monitored.
  • logic elements GUa1 to GUan with their one inputs are connected to the connections Ea1 to Ean.
  • logic elements GUb to GUbn with their one inputs are connected to the connections Eb1 to Ebn.
  • All of the link elements GUa1 to GUan, GUb1 to GUbn just mentioned are connected with their respective other inputs to the output of a clock pulse generator Tg, which makes the link elements transferable in pulses by emitting pulses.
  • the AND gates GUa1 to GUan are connected on the output side via OR gates GOa1 to GOan to the one input connections Ea1 to Ean of a first microprocessor MP1.
  • the AND gates GUb1 to GUbn are connected with their outputs via OR gates GOb1 to GObn to the one input connections eb1 to ebn of a second microprocessor MP2.
  • the two microprocessors MP 1 and MP2 may be completely corresponding microprocessors, such as those of the SAB8048 type.
  • the OR gates GOa1 to GOan just mentioned are also connected on the input side to the outputs of the register stages of a first register Reg1, which may be a shift register.
  • This shift register Regt is connected with a signal and shift input to an output connection as21 of the microprocessor MP2.
  • the OR gates GOb1 to GObn connected on the output side to the input connections eb1 to ebn of the microprocessor MP2 are connected in a corresponding manner to the outputs of register stages of a register Reg2, which may also be a shift register.
  • This shift register Reg2 is connected with a signal and shift input to an output connection as11 of the microprocessor MP1.
  • a program memory and a data memory are associated with each of the two microprocessors MP1, MP2.
  • the microprocessor MP1 is connected with an input terminal em11 to the associated program memory ROM 1, which is a read memory and which can be programmable if necessary.
  • the microprocessor MP1 is connected to an associated data memory RAM, which may also be a permanent memory or a memory with random access that is protected against power failure.
  • the other microprocessor MP2 is connected in a corresponding manner via an input connection em21 to its associated program memory ROM2 and via an input connection em22 to its associated data memory RAM2. The same applies to these two memories ROM2 and RAM2 as to the memory associated with the microprocessor MP 1.
  • a separate evaluation device Us1 or Us2 is permanently associated with each of the two microprocessors MP1, MP2.
  • the evaluation device Us1 is connected on the input side to an output connection am1 of the microprocessor MP1.
  • the evaluation device Us2 is connected on the input side to an output connection am2 of the microprocessor MP2.
  • These two evaluation devices may each contain an electromechanical device, such as a relay R1 or a relay R2, which is excited by the respective microprocessor in the presence of a signal indicating a malfunction. As already indicated above, however, it is necessary for the relays in question to be energized for the respective signal to have a certain minimum duration.
  • the two evaluation devices Us1 and Us2 control, as indicated schematically in the drawing, a monitoring circuit in which, for example, a power supply device Svg for the above-mentioned signal transmitter may be located.
  • a monitoring circuit in which, for example, a power supply device Svg for the above-mentioned signal transmitter may be located.
  • the monitoring circuit mentioned is interrupted, whereupon the voltage supply device Svg can interrupt the voltage supply to the signal transmitters.
  • the microprocessor MP1 is connected to an output connection as12 to an input connection es21 of the microprocessor MP2, which in turn has a Output terminal as22 is connected to an input terminal es11 of the microprocessor MP.
  • the microprocessor MP1 is connected with an input connection es12 to the output connection am2 of the microprocessor MP2, which is connected with an input connection es22 to the output connection am1 of the microprocessor MP1. Control processes are carried out via these connections between the two microprocessors MP1 and MP2 will be discussed in more detail below.
  • the respective microprocessor MP1 or MP2 emits a clock pulse sequence from its output connection am1 or am2 when the respective actual signal state is recognized as a permissible actual signal state.
  • the respective clock pulse sequence is then fed to the associated evaluation device Us1 or Us2, which does not signal a fault message when such a clock pulse sequence occurs.
  • the above-mentioned comparison processes which the respective microprocessor carries out can be carried out between signals indicating the actual signal states on the one hand and test signals indicating unauthorized signal states or test signals merely indicating permitted signal states on the other hand.
  • the relevant comparison processes can then be carried out with the aid of the arithmetic unit contained in the respective microprocessor.
  • each actual signal state is repeated several times with all Test signal states compared.
  • the signals indicating the individual actual signal states of the signal transmitters are now not supplied as permanent signals to the corresponding input connections of the microprocessors, but rather these signals are supplied via the pulse-controlled AND gates GUa1 to GUan or GUb1 to GUbn. Accordingly, characteristic pulses for the respective actual signal states occur at the corresponding input connections of the two microprocessors. In contrast, pulse gaps occur between these pulses.
  • the organization may now be such that the microprocessors can also determine the presence of such pulse pauses and, from the non-occurrence of such pulse pauses, can conclude that there is an incorrect transmission path for the signals indicating the actual signal states.
  • These monitoring processes can be carried out following the mentioned comparison processes, which can be carried out between the occurrence of two successive pulses of the pulses emitted by the mentioned AND gates.
  • the relevant check of the pulse pauses mentioned presupposes that the potential present during the occurrence of these pulse pauses is different from the potential that occurs when a pulse occurs. Since such a possibility of differentiation is normally only given when pulses occur which are characteristic of the presence of actual signal states with high signal levels, the just mentioned check is expediently limited to the case that actual signal states occur with such signal levels.
  • the respective microprocessor with a separate test signal for the duration of at least one of the aforementioned pulse pauses.
  • This is done via the shift registers Regl, Reg2.
  • the shift register Reg 1 is associated with the microprocessor MP 1 and the shift register Reg2 is associated with the microprocessor MP2.
  • the shift register Reg1 is loaded by the microprocessor MP2 with the test signal bits which form the separate test signal and which the microprocessor MP2 emits from its output connection as21 .
  • the shift register Reg2 is loaded in a corresponding manner with test signal bits from the output connection as11 of the microprocessor MP. The relevant charging processes do not need to be carried out at the same time.
  • test signal such a signal is used as the test signal, upon receipt of which the microprocessor in question has to emit a very specific signal.
  • the respective test signal is used to simulate the microprocessor in question, as it were, an impermissible actual signal state.
  • the output of the above-mentioned message signal also has the consequence that the clock pulse sequence normally output on the output side by the respective microprocessor is then not output.
  • the temporal relationships are chosen so that the evaluation device Us1 or Us2 associated with the respective microprocessor does not yet respond to the occurrence of the respective signal.
  • the respective signal is picked up by the other microprocessor and evaluated - ie by the microprocessor that previously triggered the test signal.
  • this microprocessor MP2 may be informed via the between the output connection as12 of the microprocessor MP1 and the input connection es21 of the microprocessor MP2 that a test signal is supplied to it on the input side.
  • this microprocessor MP 1 will be informed via the control line between the output connection as22 of the microprocessor MP2 and the input connection es11 of the microprocessor MP that a corresponding test signal has been supplied to it on the input side.
  • the control lines in question are used to report to the microprocessor in question that an output signal to be evaluated is being supplied to them from the other microprocessor (at the input connection es12 of the microprocessor MP1 or at the input connection es22 of the microprocessor MP2). .
  • each of the two microprocessors can be used to monitor whether the other microprocessor generates the associated signaling signal in response to the test signal supplied to it on the input side.
  • the monitoring microprocessor can issue a corresponding fault message and trigger the response of its associated evaluation device.
  • These monitoring measures then ensure particularly reliable monitoring of the signal states of the signal detectors, which emit the signals characteristic of their signal states to the connections Ea1 to Ean and Eb1 to Ebn mentioned.
  • the respective microprocessor sends a corresponding message signal to its associated evaluation device which - since the message signal in question occurs for a sufficiently long time - now responds and thus reports the presence of a fault.
  • the power supply device Svg of the signal transmitters can be switched off, so that the signal transmitters are then de-energized.
  • the signal transmitters it is also possible in this case for the signal transmitters to perform a specific predetermined emergency operation, e.g. a blinking operation.
  • microprocessors MP1, MP2 which the microprocessors execute sequentially have been considered.
  • the microprocessors MP1, MP2 are associated with the program memories ROM1 and ROM2 already mentioned above.
  • the data controlling the execution of the above-mentioned operating processes are stored in these program memories, which the respective microprocessor calls up in succession with the aid of the program step counter contained in it, in order then to carry out corresponding control processes.
  • the pulse-wise control of the mentioned AND gates GUa1 to GUan, GUb1 to GUbn from the clock pulse generator Tg takes place in the cycle of an AC mains voltage, which is supplied by an AC mains voltage source that feeds the signal generators.
  • the AND elements mentioned can be used to trigger pulses. Pulses occur in a time sequence of 20 ms or 10 ms, for example at zero crossings of the AC mains voltage in question.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Optical Communication System (AREA)
  • Traffic Control Systems (AREA)

Claims (2)

1. Montage pour surveiller l'état d'installations de signalisation, en particulier d'installations de signalisations lumineuses du trafic routier, du type comportant un circuit logique pour comparer les valeurs de consigne et les valeurs instantanées des états des signaux de signalisation, qui sont dérivés à partir des différents générateurs de signaux de l'installation de signalisation, ainsi qu'au moins un dispositif d'évaluation influencé par le circuit logique et qui provoque le débranchement ou la commutation de l'installation de signalisation, caractérisé par le fait qu'au titre de circuit logique sont prévus deux microprocesseurs (MP 1, MP2) opérant en fonctionnement parallèle, qu'en aval de chacun des microprocesseurs est monté un dispositif d'évaluation (Us1, Us2), que des moyens de commutation (r1, r2) des deux dispositifs d'évaluation, signalant un état de dérangement, sont insérés en série dans un circuit de surveillance en vue de surveiller l'installation de signalisation, que chaque sortie (am 1, am2) de chacun des microprocesseurs, reliée à un dispositif d'évaluation, est reliée à une entrée de commande (es22, es12), de l'autre microprocesseur, qu'en outre, une autre sortie (as11, as21) de chacun des microprocesseurs, émettant un signal de contrôle, est reliée, aux sorties (eb1-n, ea 1 -n) de l'autre microprocesseur, qui sont prévues pour recevoir des signaux de l'état de signalisation, et que la commande réciproque des microprocesseurs est opérée de telle mainière que les signaux de contrôle sont appliqués au microprocesseur concerné pendant l'intermission des signaux impulsionnels des signaux d'états des signaux de signalisation.
2. Montage selon la revendication 1, caractérisé par le fait que dans les mémoires (RAM1, RAM2) respectivement associées aux deux microprocesseurs, sont mémorisés uniquement les états des signaux admissibles et que pour la comparaison valeur de consigne- valeur instantanée de chacun des signaux d'états des signaux de signalisation, associés à chaque état instantané, qui est présent, sous la forme d'un modèle de bits aux entrées (ea1-n, eb1-n) des microprocesseurs, tous les états des signaux sont successivement comparés au signal de l'état des signaux, qui indique l'état du signal instantané.
EP79102540A 1978-08-01 1979-07-18 Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière Expired EP0007579B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT79102540T ATE1305T1 (de) 1978-08-01 1979-07-18 Schaltungsanordnung zur ueberwachung des zustands von signalanlagen, insbesondere von strassenverkehrs-lichtsignalanlagen.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2833761 1978-08-01
DE2833761A DE2833761C3 (de) 1978-08-01 1978-08-01 Schaltungsanordnung zur Überwachung des Zustands von Signalanlagen, insbesondere von Straßenverkehrs-Lichtsignalanlagen

Publications (2)

Publication Number Publication Date
EP0007579A1 EP0007579A1 (fr) 1980-02-06
EP0007579B1 true EP0007579B1 (fr) 1982-06-30

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EP79102540A Expired EP0007579B1 (fr) 1978-08-01 1979-07-18 Circuit de surveillance de l'état de systèmes de signalisation, spécialement de systèmes lumineux de signalisation de circulation routière

Country Status (4)

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US (1) US4290136A (fr)
EP (1) EP0007579B1 (fr)
AT (1) ATE1305T1 (fr)
DE (2) DE2833761C3 (fr)

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DE3337700A1 (de) * 1983-10-17 1985-05-02 Stührenberg, Rolf, 4930 Detmold Vorrichtung zur signalsicherung bei lichtzeichenanlagen
GB2150372B (en) * 1983-11-25 1986-12-10 Ferranti Plc Lamp failure detector
DE3346009A1 (de) * 1983-12-20 1985-06-27 Müller Verkehrstechnik GmbH, 7306 Denkendorf Lichtsignalsteuersystem fuer verkehrssignalanlagen
DE3428444A1 (de) * 1984-08-01 1986-02-06 Siemens AG, 1000 Berlin und 8000 München Ueberwachungseinrichtung fuer verkehrssignalanlagen
AU604804B2 (en) * 1985-09-05 1991-01-03 Adt Services Ag Improvements in and relating to conflict monitor systems
EP0214692B1 (fr) * 1985-09-05 1991-12-04 Koninklijke Philips Electronics N.V. Contrôle d'un détecteur de conflit pour feux de signalisation
DE3541549A1 (de) * 1985-11-25 1987-05-27 Stuehrenberg Rolf Verfahren und vorrichtung zur signalsicherung in lichtzeichenanlagen
ATE67621T1 (de) * 1987-04-21 1991-10-15 Siemens Ag Schaltungsanordnung zur automatischen funktionsueberpruefung einer ueberwachungseinrichtung.
FR2647932B1 (fr) * 1989-06-02 1991-09-06 Forclum Force Lumiere Elect Dispositif de telesurveillance de feux de carrefour et procede de mise en service d'un tel dispositif
DE3930877C1 (en) * 1989-09-15 1990-10-18 Stuehrenberg Gmbh, 4930 Detmold, De Traffic signal system safety circuit - has two processors receiving signal state combinations for checking their reliability
US5164904A (en) * 1990-07-26 1992-11-17 Farradyne Systems, Inc. In-vehicle traffic congestion information system
US5173691A (en) * 1990-07-26 1992-12-22 Farradyne Systems, Inc. Data fusion process for an in-vehicle traffic congestion information system
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DE19716576C1 (de) * 1997-04-21 1999-01-07 Stuehrenberg Gmbh Elektrobau S Verfahren zur Verkehrssignalsteuerung
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Also Published As

Publication number Publication date
DE2833761A1 (de) 1980-02-14
DE2833761C3 (de) 1981-12-03
DE2833761B2 (de) 1981-02-12
ATE1305T1 (de) 1982-07-15
EP0007579A1 (fr) 1980-02-06
DE2963235D1 (en) 1982-08-19
US4290136A (en) 1981-09-15

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