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DE69834762D1 - Synchronisierungsschaltung - Google Patents

Synchronisierungsschaltung

Info

Publication number
DE69834762D1
DE69834762D1 DE69834762T DE69834762T DE69834762D1 DE 69834762 D1 DE69834762 D1 DE 69834762D1 DE 69834762 T DE69834762 T DE 69834762T DE 69834762 T DE69834762 T DE 69834762T DE 69834762 D1 DE69834762 D1 DE 69834762D1
Authority
DE
Germany
Prior art keywords
synchronization circuit
synchronization
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69834762T
Other languages
English (en)
Other versions
DE69834762T2 (de
Inventor
Pieter Vorenkamp
Herve Marie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR9703999A external-priority patent/FR2761836A1/fr
Priority claimed from FR9711580A external-priority patent/FR2768581A3/fr
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of DE69834762D1 publication Critical patent/DE69834762D1/de
Application granted granted Critical
Publication of DE69834762T2 publication Critical patent/DE69834762T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
DE69834762T 1997-04-02 1998-03-26 Synchronisierungsschaltung Expired - Fee Related DE69834762T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR9703999 1997-04-02
FR9703999A FR2761836A1 (fr) 1997-04-02 1997-04-02 Dispositif de resynchronisation
FR9711580A FR2768581A3 (fr) 1997-09-17 1997-09-17 Dispositif d'interface pour un afficheur lcd
FR9711580 1997-09-17

Publications (2)

Publication Number Publication Date
DE69834762D1 true DE69834762D1 (de) 2006-07-20
DE69834762T2 DE69834762T2 (de) 2007-06-14

Family

ID=26233433

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69834762T Expired - Fee Related DE69834762T2 (de) 1997-04-02 1998-03-26 Synchronisierungsschaltung

Country Status (4)

Country Link
US (1) US5999026A (de)
EP (1) EP0869618B1 (de)
JP (1) JP4237288B2 (de)
DE (1) DE69834762T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002043245A2 (en) 2000-11-23 2002-05-30 Koninklijke Philips Electronics N.V. Clock generation circuit and integrated circuit for reproducing an audio signal comprising such a clock generation circuit
US7382823B1 (en) * 2002-02-22 2008-06-03 Xilinx, Inc. Channel bonding control logic architecture
KR101971287B1 (ko) * 2011-08-30 2019-04-23 매그나칩 반도체 유한회사 Ｌｅｄ구동장치
CN110897590B (zh) 2014-03-28 2021-11-16 直观外科手术操作公司 带有基于定量三维成像的触觉反馈的手术系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220581A (en) * 1991-03-28 1993-06-15 International Business Machines Corporation Digital data link performance monitor
US5212601A (en) * 1991-05-03 1993-05-18 Western Digital Corporation Disk drive data synchronizer with window shift synthesis
US5245637A (en) * 1991-12-30 1993-09-14 International Business Machines Corporation Phase and frequency adjustable digital phase lock logic system
KR970002949B1 (ko) * 1994-05-25 1997-03-13 삼성전자 주식회사 디지탈 통신시스템의 클럭발생방법 및 그 회로
FR2728118A1 (fr) * 1994-12-08 1996-06-14 Matra Mhs Comparateur de phase entre un signal numerique et un signal d'horloge, et boucle a verrouillage de phase correspondante
US5638015A (en) * 1995-06-21 1997-06-10 Unisys Corporation Avoiding instability
US5781480A (en) * 1997-07-29 1998-07-14 Motorola, Inc. Pipelined dual port integrated circuit memory

Also Published As

Publication number Publication date
DE69834762T2 (de) 2007-06-14
JP4237288B2 (ja) 2009-03-11
JPH113069A (ja) 1999-01-06
EP0869618B1 (de) 2006-06-07
US5999026A (en) 1999-12-07
EP0869618A1 (de) 1998-10-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee