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DE69332333D1 - Synchronisierungsschaltung - Google Patents

Synchronisierungsschaltung

Info

Publication number
DE69332333D1
DE69332333D1 DE69332333T DE69332333T DE69332333D1 DE 69332333 D1 DE69332333 D1 DE 69332333D1 DE 69332333 T DE69332333 T DE 69332333T DE 69332333 T DE69332333 T DE 69332333T DE 69332333 D1 DE69332333 D1 DE 69332333D1
Authority
DE
Germany
Prior art keywords
synchronization circuit
synchronization
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69332333T
Other languages
English (en)
Other versions
DE69332333T2 (de
Inventor
Joannes Mathilda Jos Sevenhans
Hans Andre Maria Naert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA filed Critical Alcatel SA
Application granted granted Critical
Publication of DE69332333D1 publication Critical patent/DE69332333D1/de
Publication of DE69332333T2 publication Critical patent/DE69332333T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69332333T 1993-10-12 1993-10-12 Synchronisierungsschaltung Expired - Fee Related DE69332333T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93202867A EP0648033B1 (de) 1993-10-12 1993-10-12 Synchronisierungsschaltung

Publications (2)

Publication Number Publication Date
DE69332333D1 true DE69332333D1 (de) 2002-10-31
DE69332333T2 DE69332333T2 (de) 2003-05-15

Family

ID=8214129

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69332333T Expired - Fee Related DE69332333T2 (de) 1993-10-12 1993-10-12 Synchronisierungsschaltung

Country Status (5)

Country Link
US (1) US5528637A (de)
EP (1) EP0648033B1 (de)
AU (1) AU683285B2 (de)
DE (1) DE69332333T2 (de)
ES (1) ES2183808T3 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1284718B1 (it) * 1996-07-31 1998-05-21 Cselt Centro Studi Lab Telecom Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati.
JP2993463B2 (ja) 1997-05-08 1999-12-20 日本電気株式会社 同期回路制御装置
US6377575B1 (en) 1998-08-05 2002-04-23 Vitesse Semiconductor Corporation High speed cross point switch routing circuit with word-synchronous serial back plane
US6182237B1 (en) 1998-08-31 2001-01-30 International Business Machines Corporation System and method for detecting phase errors in asics with multiple clock frequencies
EP1188263B1 (de) * 1999-06-28 2003-06-25 Siemens Aktiengesellschaft Einrichtung zur detektion von polarisationsmodendispersion
US6946948B2 (en) * 2000-06-06 2005-09-20 Vitesse Semiconductor Corporation Crosspoint switch with switch matrix module
US7027545B2 (en) * 2001-05-09 2006-04-11 Tropian, Inc. Data sampler for digital frequency/phase determination
US7260001B2 (en) * 2003-03-20 2007-08-21 Arm Limited Memory system having fast and slow data reading mechanisms
US7278080B2 (en) * 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
DE602004001869T2 (de) * 2003-03-20 2007-05-03 Arm Ltd., Cherry Hinton Fehlererkennung und fehlerbehebung für systematische und zufällige fehler innerhalb einer verarbeitungsstufe einer integrierten schaltung
US8185812B2 (en) * 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
AU2003230507A1 (en) 2003-04-29 2004-12-13 Telefonaktiebolaget Lm Ericsson (Publ) Multiphase clock recovery
US7643593B1 (en) * 2005-10-14 2010-01-05 National Semiconductor Corporation System and method for read data recovery in a serial interface
US8171386B2 (en) * 2008-03-27 2012-05-01 Arm Limited Single event upset error detection within sequential storage circuitry of an integrated circuit
US8161367B2 (en) * 2008-10-07 2012-04-17 Arm Limited Correction of single event upset error within sequential storage circuitry of an integrated circuit
US8493120B2 (en) 2011-03-10 2013-07-23 Arm Limited Storage circuitry and method with increased resilience to single event upsets
US8653868B2 (en) * 2012-06-28 2014-02-18 Intel Corporation Low power data recovery

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4012598A (en) * 1976-01-14 1977-03-15 Bell Telephone Laboratories, Incorporated Method and means for pulse receiver synchronization
FR2377729A1 (fr) * 1977-01-14 1978-08-11 Thomson Csf Dispositif de decodage de signaux numeriques, et systeme comportant un tel dispositif
NL183214C (nl) * 1980-01-31 1988-08-16 Philips Nv Inrichting voor het synchroniseren van de fase van een lokaal opgewekt kloksignaal met de fase van een ingangssignaal.
FR2604043B1 (fr) * 1986-09-17 1993-04-09 Cit Alcatel Dispositif de recalage d'un ou plusieurs trains de donnees binaires de debits identiques ou sous-multiples sur un signal de reference d'horloge synchrone
US4756011A (en) * 1986-12-24 1988-07-05 Bell Communications Research, Inc. Digital phase aligner
US4841551A (en) * 1987-01-05 1989-06-20 Grumman Aerospace Corporation High speed data-clock synchronization processor
JPH01501752A (ja) * 1987-01-05 1989-06-15 グラマン　エアロスペース　コーポレーション 高速データクロック同期プロセッサ
US5034967A (en) * 1988-11-14 1991-07-23 Datapoint Corporation Metastable-free digital synchronizer with low phase error
US4984249A (en) * 1989-05-26 1991-01-08 First Pacific Networks Method and apparatus for synchronizing digital data symbols
US5197086A (en) * 1990-12-28 1993-03-23 International Business Machines Corporation High speed digital clock synchronizer

Also Published As

Publication number Publication date
EP0648033A1 (de) 1995-04-12
EP0648033B1 (de) 2002-09-25
US5528637A (en) 1996-06-18
DE69332333T2 (de) 2003-05-15
AU7291494A (en) 1995-05-04
ES2183808T3 (es) 2003-04-01
AU683285B2 (en) 1997-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee