DE69429059D1 - Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem - Google Patents

Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem

Info

Publication number: DE69429059D1
Authority: DE; Germany
Prior art keywords: cache; cache line; control device; memory control; specified address
Prior art date: 1993-04-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69429059T

Other languages

English (en)

Inventor

James Bertone

Bruno Diplacido

Thomas Joyce

Martin Massucci

Lance Mcnally

L Murray

Nibby, Jr

Michelle Pence

Marc Sanfacon

Jian-Kuo Shen

Jeffrey Somers

Lewis Steiner

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

PB Electronics Inc

Original Assignee

Packard Bell NEC Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1993-04-30

Filing date

1994-04-28

Publication date

2001-12-20

1994-04-28 Application filed by Packard Bell NEC Inc filed Critical Packard Bell NEC Inc

2001-12-20 Application granted granted Critical

2001-12-20 Publication of DE69429059D1 publication Critical patent/DE69429059D1/de

2014-04-29 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0653—Configuration or reconfiguration with centralised address assignment
- G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Memory System Of A Hierarchy Structure (AREA)
Multi Processors (AREA)
Memory System (AREA)
Bus Control (AREA)
Exchange Systems With Centralized Control (AREA)
Hardware Redundancy (AREA)
Complex Calculations (AREA)
Feedback Control In General (AREA)

DE69429059T 1993-04-30 1994-04-28 Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem Expired - Lifetime DE69429059D1 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US5705293A	1993-04-30	1993-04-30
PCT/US1994/004836 WO1994025914A2 (en)	1993-04-30	1994-04-28	Symmetric multiprocessing system with unified environment and distributed system functions

Publications (1)

Publication Number	Publication Date
DE69429059D1 true DE69429059D1 (de)	2001-12-20

Family

ID=22008220

Family Applications (3)

Application Number	Title	Priority Date	Filing Date
DE69434144T Expired - Lifetime DE69434144D1 (de)	1993-04-30	1994-04-28	Symmetrisches Mehrprozessorsystem mit vereinheitlichter Umgebung und verteilten Systemfunktionen
DE69429059T Expired - Lifetime DE69429059D1 (de)	1993-04-30	1994-04-28	Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem
DE69433147T Expired - Lifetime DE69433147D1 (de)	1993-04-30	1994-04-28	Symmetrisches Mehrprozessorsystem mit vereinheitlichter Umgebung und verteilten Systemfunktionen

Family Applications Before (1)

Application Number	Title	Priority Date	Filing Date
DE69434144T Expired - Lifetime DE69434144D1 (de)	1993-04-30	1994-04-28	Symmetrisches Mehrprozessorsystem mit vereinheitlichter Umgebung und verteilten Systemfunktionen

Family Applications After (1)

Application Number	Title	Priority Date	Filing Date
DE69433147T Expired - Lifetime DE69433147D1 (de)	1993-04-30	1994-04-28	Symmetrisches Mehrprozessorsystem mit vereinheitlichter Umgebung und verteilten Systemfunktionen

Country Status (6)

Country	Link
EP (4)	EP0648355B1 (de)
JP (8)	JP3255922B2 (de)
AT (3)	ATE208926T1 (de)
CA (3)	CA2138537C (de)
DE (3)	DE69434144D1 (de)
WO (1)	WO1994025914A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0648355B1 (de) *	1993-04-30	2001-11-14	Packard Bell NEC, Inc.	Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem
US6282647B1 (en) *	1999-06-02	2001-08-28	Adaptec, Inc.	Method for flashing a read only memory (ROM) chip of a host adapter with updated option ROM bios code
JP2006293969A (ja) *	2005-03-17	2006-10-26	Fujitsu Ltd	データ転送装置
JP4443474B2 (ja)	2005-06-14	2010-03-31	株式会社ソニー・コンピュータエンタテインメント	コマンド転送制御装置およびコマンド転送制御方法
JP5168800B2 (ja) *	2006-03-08	2013-03-27	富士通株式会社	マルチプロセッサシステム
JP5079342B2 (ja) *	2007-01-22	2012-11-21	ルネサスエレクトロニクス株式会社	マルチプロセッサ装置
US7979616B2 (en) *	2007-06-22	2011-07-12	International Business Machines Corporation	System and method for providing a configurable command sequence for a memory interface device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4760515A (en) *	1985-10-28	1988-07-26	International Business Machines Corporation	Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis
JPS6462741A (en) *	1987-09-02	1989-03-09	Mitsubishi Electric Corp	Main storage device
JPH01102661A (ja) *	1987-10-15	1989-04-20	Hitachi Ltd	記憶装置のバンク制御方式
JPH0212541A (ja) *	1988-04-29	1990-01-17	Internatl Business Mach Corp <Ibm>	コンピユーテイング・システム及びその動作方法
US5111423A (en) *	1988-07-21	1992-05-05	Altera Corporation	Programmable interface for computer system peripheral circuit card
US5117350A (en) *	1988-12-15	1992-05-26	Flashpoint Computer Corporation	Memory address mechanism in a distributed memory architecture
US5155824A (en) *	1989-05-15	1992-10-13	Motorola, Inc.	System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
JPH0373040A (ja) *	1989-08-14	1991-03-28	Nec Corp	キャッシュメモリ
JPH03167649A (ja) *	1989-11-28	1991-07-19	Nec Corp	ウエイト・サイクル制御装置
JPH0435540A (ja) *	1990-05-31	1992-02-06	Fujitsu Ltd	バス調停装置
US5283877A (en) *	1990-07-17	1994-02-01	Sun Microsystems, Inc.	Single in-line DRAM memory module including a memory controller and cross bar switches
US5522064A (en) *	1990-10-01	1996-05-28	International Business Machines Corporation	Data processing apparatus for dynamically setting timings in a dynamic memory system
JPH0715665B2 (ja) *	1991-06-10	1995-02-22	インターナショナル・ビジネス・マシーンズ・コーポレイション	パーソナルコンピユータ
US5327570A (en) *	1991-07-22	1994-07-05	International Business Machines Corporation	Multiprocessor system having local write cache within each data processor node
EP0648355B1 (de) *	1993-04-30	2001-11-14	Packard Bell NEC, Inc.	Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem

1994
- 1994-04-28 EP EP94915976A patent/EP0648355B1/de not_active Expired - Lifetime
- 1994-04-28 AT AT94915976T patent/ATE208926T1/de not_active IP Right Cessation
- 1994-04-28 CA CA002138537A patent/CA2138537C/en not_active Expired - Lifetime
- 1994-04-28 DE DE69434144T patent/DE69434144D1/de not_active Expired - Lifetime
- 1994-04-28 DE DE69429059T patent/DE69429059D1/de not_active Expired - Lifetime
- 1994-04-28 JP JP52461794A patent/JP3255922B2/ja not_active Expired - Lifetime
- 1994-04-28 EP EP00202733.2A patent/EP1067459B1/de not_active Expired - Lifetime
- 1994-04-28 EP EP00203455A patent/EP1071018B1/de not_active Expired - Lifetime
- 1994-04-28 CA CA002215701A patent/CA2215701C/en not_active Expired - Lifetime
- 1994-04-28 DE DE69433147T patent/DE69433147D1/de not_active Expired - Lifetime
- 1994-04-28 WO PCT/US1994/004836 patent/WO1994025914A2/en active IP Right Grant
- 1994-04-28 AT AT00203455T patent/ATE249643T1/de not_active IP Right Cessation
- 1994-04-28 CA CA002215844A patent/CA2215844C/en not_active Expired - Lifetime
- 1994-04-28 EP EP00202734A patent/EP1056020B1/de not_active Expired - Lifetime
- 1994-04-28 AT AT00202734T patent/ATE282856T1/de not_active IP Right Cessation
1998
- 1998-06-09 JP JP16104798A patent/JP3957240B2/ja not_active Expired - Lifetime
- 1998-06-09 JP JP10161058A patent/JPH11126183A/ja active Pending
- 1998-06-09 JP JP10161033A patent/JPH1153254A/ja active Pending
1999
- 1999-01-04 JP JP11000197A patent/JPH11338760A/ja active Pending
2003
- 2003-12-22 JP JP2003425646A patent/JP4209764B2/ja not_active Expired - Lifetime
2004
- 2004-07-21 JP JP2004212884A patent/JP2004310794A/ja active Pending
2005
- 2005-10-18 JP JP2005302835A patent/JP4106664B2/ja not_active Expired - Lifetime

Also Published As

Publication number	Publication date
JPH1153254A (ja)	1999-02-26
CA2138537C (en)	2003-02-25
EP1056020A2 (de)	2000-11-29
EP0648355A1 (de)	1995-04-19
JP2004280787A (ja)	2004-10-07
EP1071018A3 (de)	2001-02-07
ATE208926T1 (de)	2001-11-15
JP3255922B2 (ja)	2002-02-12
JPH1185681A (ja)	1999-03-30
WO1994025914A3 (en)	1995-01-05
CA2215844C (en)	2001-09-04
JP4106664B2 (ja)	2008-06-25
CA2215701C (en)	2002-02-26
CA2215844A1 (en)	1994-11-10
ATE249643T1 (de)	2003-09-15
JP2006085728A (ja)	2006-03-30
EP1056020A3 (de)	2001-12-05
EP1067459A3 (de)	2001-02-07
WO1994025914A2 (en)	1994-11-10
EP1071018B1 (de)	2003-09-10
JP4209764B2 (ja)	2009-01-14
DE69433147D1 (de)	2003-10-16
JP3957240B2 (ja)	2007-08-15
EP0648355B1 (de)	2001-11-14
JPH07508611A (ja)	1995-09-21
ATE282856T1 (de)	2004-12-15
DE69434144D1 (de)	2004-12-23
EP1056020B1 (de)	2004-11-17
EP1067459A2 (de)	2001-01-10
CA2138537A1 (en)	1994-04-28
JPH11126183A (ja)	1999-05-11
JPH11338760A (ja)	1999-12-10
EP1067459B1 (de)	2013-08-28
EP1071018A2 (de)	2001-01-24
CA2215701A1 (en)	1994-11-10
JP2004310794A (ja)	2004-11-04

Publication	Publication Date	Title
CA2027226A1 (en)	1991-04-13	Information Processing System
KR920000040A (ko)	1992-01-10	카피-백 데이타 캐시를 구비한 데이타 치리기
CA2066454A1 (en)	1991-03-12	Apparatus and method for maintaining cache/main memory consistency
JPH04220738A (ja)	1992-08-11	高速書き込み方法
KR860000595A (ko)	1986-01-29	정보처리장치를 위한 메모리액세스 제어방식
KR960015368A (ko)	1996-05-22	데이타 프로세싱 시스템
DE69429059D1 (de)	2001-12-20	Adaptive speichersteureinrichtung für ein symmetrisches mehrprozessorsystem
ES8606688A1 (es)	1986-04-01	Procedimiento para controlar una memoria intermedia de un aparato de proceso de datos
DE69227267D1 (de)	1998-11-19	Datencache-Speicher und Verfahren zur Speicherfehlerbehandlung während Zurückschreiben
TW324800B (en)	1998-01-11	Dual-directory virtual cache and control method thereof
JPS6476346A (en)	1989-03-22	Disk cache control system
ATE273536T1 (de)	2004-08-15	Verfahren und vorrichtung zur zugriffsteuerung von gemeinsamem speicher
DE69028474D1 (de)	1996-10-17	Verfahren und System zur dynamischen Programmbetriebssteuerung
JPS57189398A (en)	1982-11-20	Control system for memory system
KR950000312A (ko)	1995-01-03	로보트의 제어 방법
JPH07152650A (ja)	1995-06-16	キャッシュ制御装置
JPS5794974A (en)	1982-06-12	Buffer memory control system
JPH0433060B2 (de)	1992-06-02
KR970071241A (ko)	1997-11-07	다중처리 시스템의 캐시 스테이트 램(ram) 관리방법
JPS5729164A (en)	1982-02-17	Computer system
JPS5712469A (en)	1982-01-22	Buffer memory control system
JPS56145583A (en)	1981-11-12	Buffer memory device
JPS6243737A (ja)	1987-02-25	割り込み制御方式
JPH02253358A (ja)	1990-10-12	キャッシュメモリ
JPS62127943A (ja)	1987-06-10	命令バツフア制御方式

Legal Events

Date	Code	Title	Description
2002-07-11	8332	No legal effect for de