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DE68926256D1 - Komplementäre Halbleiteranordnung - Google Patents

Komplementäre Halbleiteranordnung

Info

Publication number
DE68926256D1
DE68926256D1 DE68926256T DE68926256T DE68926256D1 DE 68926256 D1 DE68926256 D1 DE 68926256D1 DE 68926256 T DE68926256 T DE 68926256T DE 68926256 T DE68926256 T DE 68926256T DE 68926256 D1 DE68926256 D1 DE 68926256D1
Authority
DE
Germany
Prior art keywords
semiconductor device
complementary semiconductor
complementary
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68926256T
Other languages
English (en)
Other versions
DE68926256T2 (de
Inventor
Yuji Awano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63000742A external-priority patent/JP2668373B2/ja
Priority claimed from JP63188908A external-priority patent/JP2611358B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE68926256D1 publication Critical patent/DE68926256D1/de
Application granted granted Critical
Publication of DE68926256T2 publication Critical patent/DE68926256T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/801—FETs having heterojunction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
DE68926256T 1988-01-07 1989-01-05 Komplementäre Halbleiteranordnung Expired - Fee Related DE68926256T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63000742A JP2668373B2 (ja) 1988-01-07 1988-01-07 相補型半導体装置
JP63188908A JP2611358B2 (ja) 1988-07-28 1988-07-28 半導体装置

Publications (2)

Publication Number Publication Date
DE68926256D1 true DE68926256D1 (de) 1996-05-23
DE68926256T2 DE68926256T2 (de) 1996-09-19

Family

ID=26333790

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68926256T Expired - Fee Related DE68926256T2 (de) 1988-01-07 1989-01-05 Komplementäre Halbleiteranordnung

Country Status (3)

Country Link
US (1) US4994866A (de)
EP (1) EP0323896B1 (de)
DE (1) DE68926256T2 (de)

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US5241197A (en) * 1989-01-25 1993-08-31 Hitachi, Ltd. Transistor provided with strained germanium layer
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US5155571A (en) * 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
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FR2686455A1 (fr) * 1992-01-22 1993-07-23 Picogiga Sa Transistor a effet de champ a canal p a heterojonction, et circuit integre a transistors complementaires.
WO1993015523A1 (fr) * 1992-01-22 1993-08-05 Picogiga Sa Transistor a effet de champ a canal p a puits quantique, et circuit integre a transistors complementaires
US5192698A (en) * 1992-03-17 1993-03-09 The United State Of America As Represented By The Secretary Of The Air Force Making staggered complementary heterostructure FET
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JP3144032B2 (ja) * 1992-03-30 2001-03-07 ソニー株式会社 薄膜トランジスタ及びその製造方法
US5268324A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Modified silicon CMOS process having selectively deposited Si/SiGe FETS
US5354700A (en) * 1993-07-26 1994-10-11 United Microelectronics Corporation Method of manufacturing super channel TFT structure
US5500391A (en) * 1994-08-09 1996-03-19 At&T Corp. Method for making a semiconductor device including diffusion control
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US5849621A (en) * 1996-06-19 1998-12-15 Advanced Micro Devices, Inc. Method and structure for isolating semiconductor devices after transistor formation
US6399970B2 (en) * 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
DE19720008A1 (de) * 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US5863824A (en) * 1997-12-18 1999-01-26 Advanced Micro Devices Method of forming semiconductor devices using gate electrode length and spacer width for controlling drivecurrent strength
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
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EP1672700A2 (de) * 1999-11-15 2006-06-21 Matsushita Electric Industrial Co., Ltd. Feldeffekt-Halbleiterbauelement
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US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
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US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
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US6713819B1 (en) * 2002-04-08 2004-03-30 Advanced Micro Devices, Inc. SOI MOSFET having amorphized source drain and method of fabrication
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JP3506694B1 (ja) * 2002-09-02 2004-03-15 沖電気工業株式会社 Ｍｏｓｆｅｔデバイス及びその製造方法
US7023018B2 (en) * 2004-04-06 2006-04-04 Texas Instruments Incorporated SiGe transistor with strained layers
US7338834B2 (en) * 2006-03-17 2008-03-04 Acorn Technologies, Inc. Strained silicon with elastic edge relaxation
US8471244B2 (en) * 2006-12-05 2013-06-25 Atmel Corporation Method and system for providing a metal oxide semiconductor device having a drift enhanced channel
US8288756B2 (en) * 2007-11-30 2012-10-16 Advanced Micro Devices, Inc. Hetero-structured, inverted-T field effect transistor
US8454653B2 (en) * 2008-02-20 2013-06-04 Covidien Lp Compound barb medical device and method
JP2009206123A (ja) * 2008-02-26 2009-09-10 Sanken Electric Co Ltd Ｈｆｅｔおよびその製造方法
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Also Published As

Publication number Publication date
US4994866A (en) 1991-02-19
EP0323896A2 (de) 1989-07-12
EP0323896A3 (de) 1992-04-08
EP0323896B1 (de) 1996-04-17
DE68926256T2 (de) 1996-09-19

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8339 Ceased/non-payment of the annual fee