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DE3888937D1 - Verfahren zum Herstellen von integrierten Schaltungen mit FET. - Google Patents

Verfahren zum Herstellen von integrierten Schaltungen mit FET.

Info

Publication number
DE3888937D1
DE3888937D1 DE88311215T DE3888937T DE3888937D1 DE 3888937 D1 DE3888937 D1 DE 3888937D1 DE 88311215 T DE88311215 T DE 88311215T DE 3888937 T DE3888937 T DE 3888937T DE 3888937 D1 DE3888937 D1 DE 3888937D1
Authority
DE
Germany
Prior art keywords
fet
integrated circuits
manufacturing integrated
manufacturing
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88311215T
Other languages
English (en)
Other versions
DE3888937T2 (de
Inventor
Kuo-Hua Lee
Chih-Yuan Lu
David Stanley Yaney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22437208&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3888937(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of DE3888937D1 publication Critical patent/DE3888937D1/de
Application granted granted Critical
Publication of DE3888937T2 publication Critical patent/DE3888937T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE3888937T 1987-12-04 1988-11-25 Verfahren zum Herstellen von integrierten Schaltungen mit FET. Expired - Fee Related DE3888937T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/128,834 US4844776A (en) 1987-12-04 1987-12-04 Method for making folded extended window field effect transistor

Publications (2)

Publication Number Publication Date
DE3888937D1 true DE3888937D1 (de) 1994-05-11
DE3888937T2 DE3888937T2 (de) 1994-07-21

Family

ID=22437208

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3888937T Expired - Fee Related DE3888937T2 (de) 1987-12-04 1988-11-25 Verfahren zum Herstellen von integrierten Schaltungen mit FET.

Country Status (8)

Country Link
US (1) US4844776A (de)
EP (1) EP0319215B1 (de)
JP (1) JP2780986B2 (de)
KR (1) KR960001602B1 (de)
CA (1) CA1284235C (de)
DE (1) DE3888937T2 (de)
ES (1) ES2050712T3 (de)
HK (1) HK43495A (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2780179B2 (ja) * 1988-10-14 1998-07-30 セイコーエプソン株式会社 半導体装置及び半導体装置の製造方法
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
US4954214A (en) * 1989-01-05 1990-09-04 Northern Telecom Limited Method for making interconnect structures for VLSI devices
EP0422824A1 (de) * 1989-10-12 1991-04-17 AT&T Corp. Feldeffekttransistor mit Fenster aus Polysilizium
US5036378A (en) * 1989-11-01 1991-07-30 At&T Bell Laboratories Memory device
FR2655194B1 (fr) * 1989-11-28 1992-04-10 Sgs Thomson Microelectronics Procede de fabrication de circuits integres constituant des memoires eprom.
DE4038177A1 (de) * 1989-12-18 1991-06-20 Telefunken Electronic Gmbh Halbleiteranordnung und verfahren zu ihrer herstellung
JPH03230531A (ja) * 1990-02-06 1991-10-14 Matsushita Electron Corp 半導体装置の製造方法
US5879997A (en) * 1991-05-30 1999-03-09 Lucent Technologies Inc. Method for forming self aligned polysilicon contact
US5219793A (en) * 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
US5880022A (en) * 1991-12-30 1999-03-09 Lucent Technologies Inc. Self-aligned contact window
KR950011982B1 (ko) * 1992-11-06 1995-10-13 현대전자산업주식회사 전도물질 패드를 갖는 반도체 접속장치 및 그 제조방법
JPH06333944A (ja) * 1993-05-25 1994-12-02 Nippondenso Co Ltd 半導体装置
US5731218A (en) * 1993-11-02 1998-03-24 Siemens Aktiengesellschaft Method for producing a contact hole to a doped region
DE4337355C2 (de) * 1993-11-02 1997-08-21 Siemens Ag Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5395787A (en) * 1993-12-01 1995-03-07 At&T Corp. Method of manufacturing shallow junction field effect transistor
US5420058A (en) * 1993-12-01 1995-05-30 At&T Corp. Method of making field effect transistor with a sealed diffusion junction
US5407859A (en) * 1993-12-01 1995-04-18 At&T Corp. Field effect transistor with landing pad
JP3238820B2 (ja) * 1994-02-18 2001-12-17 富士通株式会社 半導体装置
US5633196A (en) * 1994-05-31 1997-05-27 Sgs-Thomson Microelectronics, Inc. Method of forming a barrier and landing pad structure in an integrated circuit
US5956615A (en) * 1994-05-31 1999-09-21 Stmicroelectronics, Inc. Method of forming a metal contact to landing pad structure in an integrated circuit
US5702979A (en) * 1994-05-31 1997-12-30 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
US5945738A (en) * 1994-05-31 1999-08-31 Stmicroelectronics, Inc. Dual landing pad structure in an integrated circuit
US5705427A (en) * 1994-12-22 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad structure in an integrated circuit
JP4156044B2 (ja) * 1994-12-22 2008-09-24 エスティーマイクロエレクトロニクス，インコーポレイテッド 集積回路におけるランディングパッド構成体の製造方法
JP2790167B2 (ja) * 1995-01-09 1998-08-27 日本電気株式会社 半導体装置及びその製造方法
US5686761A (en) * 1995-06-06 1997-11-11 Advanced Micro Devices, Inc. Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
US5719071A (en) * 1995-12-22 1998-02-17 Sgs-Thomson Microelectronics, Inc. Method of forming a landing pad sturcture in an integrated circuit
US6001726A (en) * 1997-03-24 1999-12-14 Motorola, Inc. Method for using a conductive tungsten nitride etch stop layer to form conductive interconnects and tungsten nitride contact structure
US6001697A (en) * 1998-03-24 1999-12-14 Mosel Vitelic Inc. Process for manufacturing semiconductor devices having raised doped regions
JP3939314B2 (ja) 2004-06-10 2007-07-04 三星電子株式会社 空気調和装置及びその均油運転方法
DE102005063092B3 (de) * 2005-12-30 2007-07-19 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einer Kontaktstruktur mit erhöhter Ätzselektivität
DE102006004412B3 (de) * 2006-01-31 2007-08-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Ätzselektivität in einer Kontaktstruktur in Halbleiterbauelementen
JP2008058628A (ja) * 2006-08-31 2008-03-13 Ricoh Co Ltd 光走査装置および光走査装置を備えた画像形成装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4384301A (en) * 1979-11-07 1983-05-17 Texas Instruments Incorporated High performance submicron metal-oxide-semiconductor field effect transistor device structure
US4324038A (en) * 1980-11-24 1982-04-13 Bell Telephone Laboratories, Incorporated Method of fabricating MOS field effect transistors
JPS5830147A (ja) * 1981-08-18 1983-02-22 Toshiba Corp 半導体装置
US4453306A (en) * 1983-05-27 1984-06-12 At&T Bell Laboratories Fabrication of FETs
US4478679A (en) * 1983-11-30 1984-10-23 Storage Technology Partners Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors
JPH0612822B2 (ja) * 1984-07-27 1994-02-16 株式会社日立製作所 半導体装置
CA1235824A (en) * 1985-06-28 1988-04-26 Vu Q. Ho Vlsi mosfet circuits using refractory metal and/or refractory metal silicide
JPS62169480A (ja) * 1986-01-22 1987-07-25 Hitachi Ltd 半導体装置とその製造方法
JPH0773127B2 (ja) * 1986-01-31 1995-08-02 株式会社東芝 半導体装置の製造方法
JPS62224075A (ja) * 1986-03-26 1987-10-02 Hitachi Ltd 半導体集積回路装置の製造方法
JPS62224077A (ja) * 1986-03-26 1987-10-02 Hitachi Micro Comput Eng Ltd 半導体集積回路装置

Also Published As

Publication number Publication date
JP2780986B2 (ja) 1998-07-30
KR960001602B1 (ko) 1996-02-02
EP0319215B1 (de) 1994-04-06
HK43495A (en) 1995-03-31
ES2050712T3 (es) 1994-06-01
KR890011110A (ko) 1989-08-12
CA1284235C (en) 1991-05-14
JPH022139A (ja) 1990-01-08
EP0319215A3 (en) 1990-01-03
EP0319215A2 (de) 1989-06-07
US4844776A (en) 1989-07-04
DE3888937T2 (de) 1994-07-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee