DE3871823D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number: DE3871823D1
Authority: DE; Germany
Prior art keywords: semiconductor memory; memory arrangement; arrangement; semiconductor; memory
Prior art date: 1987-03-13
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE8888103704T

Other languages

English (en)

Other versions

DE3871823T2 (de

Inventor

Shinichi C O Patent Div Tanaka

Masayuki C O Patent Divis Hori

Kazunori C O Patent D Kanebako

Noriyoshi C O Patent Di Tozawa

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Toshiba Corp

Original Assignee

Toshiba Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1987-03-13

Filing date

1988-03-09

Publication date

1992-07-16

1988-03-09 Application filed by Toshiba Corp filed Critical Toshiba Corp

1992-07-16 Publication of DE3871823D1 publication Critical patent/DE3871823D1/de

1992-12-10 Application granted granted Critical

1992-12-10 Publication of DE3871823T2 publication Critical patent/DE3871823T2/de

2008-03-10 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
- H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel

DE8888103704T 1987-03-13 1988-03-09 Halbleiterspeicheranordnung. Expired - Lifetime DE3871823T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP62058109A JPH0640587B2 (ja)	1987-03-13	1987-03-13	半導体記憶装置

Publications (2)

Publication Number	Publication Date
DE3871823D1 true DE3871823D1 (de)	1992-07-16
DE3871823T2 DE3871823T2 (de)	1992-12-10

Family

ID=13074805

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8888103704T Expired - Lifetime DE3871823T2 (de)	1987-03-13	1988-03-09	Halbleiterspeicheranordnung.

Country Status (4)

Country	Link
EP (1)	EP0282023B1 (de)
JP (1)	JPH0640587B2 (de)
KR (1)	KR910007375B1 (de)
DE (1)	DE3871823T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH0640588B2 (ja) *	1987-03-13	1994-05-25	株式会社東芝	半導体記憶装置
US5332914A (en) *	1988-02-05	1994-07-26	Emanuel Hazani	EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
US5162247A (en) *	1988-02-05	1992-11-10	Emanuel Hazani	Process for trench-isolated self-aligned split-gate EEPROM transistor and memory array
US5166904A (en) *	1988-02-05	1992-11-24	Emanuel Hazani	EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
US5303185A (en) *	1988-02-05	1994-04-12	Emanuel Hazani	EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells
KR910005235B1 (ko) *	1988-12-01	1991-07-24	재단법인 한국화학연구소	흡수성 고분자 물질 및 그의 제조방법
JP2679389B2 (ja) *	1990-10-12	1997-11-19	日本電気株式会社	不揮発性半導体記憶セルのデータ消去方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0054355B1 (de) *	1980-12-08	1986-04-16	Kabushiki Kaisha Toshiba	Halbleiterspeicheranordnung
DE3171836D1 (en) *	1980-12-08	1985-09-19	Toshiba Kk	Semiconductor memory device
JPS60250676A (ja) *	1984-05-25	1985-12-11	Toshiba Corp	半導体記憶装置
JPH0697695B2 (ja) *	1984-11-16	1994-11-30	株式会社日立製作所	半導体集積回路装置の製造方法
JPS61136274A (ja) *	1984-12-07	1986-06-24	Toshiba Corp	半導体装置
JPS61225872A (ja) *	1985-03-29	1986-10-07	Nippon Denso Co Ltd	半導体不揮発性記憶装置の製造方法
JPH0640588B2 (ja) *	1987-03-13	1994-05-25	株式会社東芝	半導体記憶装置

1987
- 1987-03-13 JP JP62058109A patent/JPH0640587B2/ja not_active Expired - Fee Related
1988
- 1988-03-09 DE DE8888103704T patent/DE3871823T2/de not_active Expired - Lifetime
- 1988-03-09 EP EP88103704A patent/EP0282023B1/de not_active Expired - Lifetime
- 1988-03-12 KR KR1019880002643A patent/KR910007375B1/ko not_active IP Right Cessation

Also Published As

Publication number	Publication date
JPS63224366A (ja)	1988-09-19
EP0282023A2 (de)	1988-09-14
EP0282023B1 (de)	1992-06-10
DE3871823T2 (de)	1992-12-10
KR880011928A (ko)	1988-10-31
JPH0640587B2 (ja)	1994-05-25
EP0282023A3 (en)	1989-05-17
KR910007375B1 (ko)	1991-09-25

Publication	Publication Date	Title
DE3778439D1 (de)	1992-05-27	Halbleiterspeicheranordnung.
DE3751002D1 (de)	1995-03-02	Halbleiterspeicher.
DE68911044D1 (de)	1994-01-13	Halbleiterspeicher.
DE3585711D1 (de)	1992-04-30	Halbleiterspeicheranordnung.
DE3788747D1 (de)	1994-02-24	Halbleiterspeicher.
DE3875767D1 (de)	1992-12-17	Halbleiter-festwertspeichereinrichtung.
DE3887224D1 (de)	1994-03-03	Halbleiterspeicheranordnung.
DE3583091D1 (de)	1991-07-11	Halbleiterspeicheranordnung.
DE3577944D1 (de)	1990-06-28	Halbleiterspeicheranordnung.
DE3884022D1 (de)	1993-10-21	Halbleiterspeicheranordnung.
DE3582376D1 (de)	1991-05-08	Halbleiterspeicheranordnung.
DE3772137D1 (de)	1991-09-19	Halbleiter-speicheranordnung.
DE3586377D1 (de)	1992-08-27	Halbleiterspeicheranordnung.
DE3771238D1 (de)	1991-08-14	Halbleiterspeicher.
DE3778408D1 (de)	1992-05-27	Halbleiterspeicheranordnung.
DE3576236D1 (de)	1990-04-05	Halbleiterspeicheranordnung.
DE68918193D1 (de)	1994-10-20	Halbleiterspeicher.
DE3889872D1 (de)	1994-07-07	Halbleiterspeicheranordnung.
DE3787616D1 (de)	1993-11-04	Halbleiterspeicheranordnung.
DE3577367D1 (de)	1990-05-31	Halbleiterspeicheranordnung.
DE3783666D1 (de)	1993-03-04	Halbleiterspeicheranordnung.
DE3887823D1 (de)	1994-03-24	Halbleiterspeicher.
DE3878370D1 (de)	1993-03-25	Nichtfluechtige halbleiterspeicheranordnung.
DE3586556D1 (de)	1992-10-01	Halbleiterspeicheranordnung.
DE3580993D1 (de)	1991-02-07	Halbleiterspeicheranordnung.

Legal Events

Date	Code	Title	Description
1993-07-08	8364	No opposition during term of opposition
2000-05-11	8339	Ceased/non-payment of the annual fee