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DE3780369D1 - Verfahren zum herstellen einer halbleiterstruktur. - Google Patents

Verfahren zum herstellen einer halbleiterstruktur.

Info

Publication number
DE3780369D1
DE3780369D1 DE8787101113T DE3780369T DE3780369D1 DE 3780369 D1 DE3780369 D1 DE 3780369D1 DE 8787101113 T DE8787101113 T DE 8787101113T DE 3780369 T DE3780369 T DE 3780369T DE 3780369 D1 DE3780369 D1 DE 3780369D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor structure
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787101113T
Other languages
English (en)
Other versions
DE3780369T2 (de
Inventor
Hideo Homma
Yutaka Misawa
Naohiro Momma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3780369D1 publication Critical patent/DE3780369D1/de
Publication of DE3780369T2 publication Critical patent/DE3780369T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • H10D10/051Manufacture or treatment of vertical BJTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/258Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0107Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/017Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE8787101113T 1986-07-09 1987-01-27 Verfahren zum herstellen einer halbleiterstruktur. Expired - Fee Related DE3780369T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61159631A JPH0628266B2 (ja) 1986-07-09 1986-07-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3780369D1 true DE3780369D1 (de) 1992-08-20
DE3780369T2 DE3780369T2 (de) 1993-03-04

Family

ID=15697933

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787101113T Expired - Fee Related DE3780369T2 (de) 1986-07-09 1987-01-27 Verfahren zum herstellen einer halbleiterstruktur.

Country Status (4)

Country Link
US (1) US4735916A (de)
EP (1) EP0252206B1 (de)
JP (1) JPH0628266B2 (de)
DE (1) DE3780369T2 (de)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2193036B (en) * 1986-07-24 1990-05-02 Mitsubishi Electric Corp Method of fabricating a semiconductor integrated circuit device
JPS63184364A (ja) * 1987-01-27 1988-07-29 Toshiba Corp 半導体装置の製造方法
GB2202370B (en) * 1987-02-27 1990-02-21 British Telecomm Self-aligned bipolar fabrication process
US4826782A (en) * 1987-04-17 1989-05-02 Tektronix, Inc. Method of fabricating aLDD field-effect transistor
US4902640A (en) * 1987-04-17 1990-02-20 Tektronix, Inc. High speed double polycide bipolar/CMOS integrated circuit process
JPS63268258A (ja) * 1987-04-24 1988-11-04 Nec Corp 半導体装置
US4829025A (en) * 1987-10-02 1989-05-09 Advanced Micro Devices, Inc. Process for patterning films in manufacture of integrated circuit structures
US5017995A (en) * 1987-11-27 1991-05-21 Nec Corporation Self-aligned Bi-CMOS device having high operation speed and high integration density
US5225355A (en) * 1988-02-26 1993-07-06 Fujitsu Limited Gettering treatment process
JP2727557B2 (ja) * 1988-03-25 1998-03-11 ソニー株式会社 半導体装置の製造方法
EP0346543A1 (de) * 1988-06-15 1989-12-20 BRITISH TELECOMMUNICATIONS public limited company Bipolarer Transistor
KR900001034A (ko) * 1988-06-27 1990-01-31 야마무라 가쯔미 반도체장치
JPH0223648A (ja) * 1988-07-12 1990-01-25 Seiko Epson Corp 半導体装置
US5015594A (en) * 1988-10-24 1991-05-14 International Business Machines Corporation Process of making BiCMOS devices having closely spaced device regions
JP2918205B2 (ja) * 1988-11-09 1999-07-12 三菱電機株式会社 半導体装置およびその製造方法
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
US4945070A (en) * 1989-01-24 1990-07-31 Harris Corporation Method of making cmos with shallow source and drain junctions
US5238857A (en) * 1989-05-20 1993-08-24 Fujitsu Limited Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure
JPH03141645A (ja) * 1989-07-10 1991-06-17 Texas Instr Inc <Ti> ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子
US5294822A (en) * 1989-07-10 1994-03-15 Texas Instruments Incorporated Polycide local interconnect method and structure
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
US5024959A (en) * 1989-09-25 1991-06-18 Motorola, Inc. CMOS process using doped glass layer
US4960726A (en) * 1989-10-19 1990-10-02 International Business Machines Corporation BiCMOS process
US5182225A (en) * 1990-01-10 1993-01-26 Microunity Systems Engineering, Inc. Process for fabricating BICMOS with hypershallow junctions
US5112761A (en) * 1990-01-10 1992-05-12 Microunity Systems Engineering Bicmos process utilizing planarization technique
US5483104A (en) * 1990-01-12 1996-01-09 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5166771A (en) * 1990-01-12 1992-11-24 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
US5102816A (en) * 1990-03-27 1992-04-07 Sematech, Inc. Staircase sidewall spacer for improved source/drain architecture
DE69109919T2 (de) * 1990-04-02 1996-01-04 Nat Semiconductor Corp BiCMOS-Bauelement mit engbenachbarten Kontakten und dessen Herstellungsverfahren.
US5234847A (en) * 1990-04-02 1993-08-10 National Semiconductor Corporation Method of fabricating a BiCMOS device having closely spaced contacts
US5071780A (en) * 1990-08-27 1991-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse self-aligned transistor integrated circuit
KR100307272B1 (ko) * 1990-12-04 2002-05-01 하라 레이노스케 Mos소자제조방법
KR940009357B1 (ko) * 1991-04-09 1994-10-07 삼성전자주식회사 반도체 장치 및 그 제조방법
JPH05110005A (ja) * 1991-10-16 1993-04-30 N M B Semiconductor:Kk Mos型トランジスタ半導体装置およびその製造方法
KR100281346B1 (ko) * 1992-04-28 2001-03-02 칼 하인쯔 호르닝어 도핑된 영역내 비아 홀 제조방법
JP2886420B2 (ja) * 1992-10-23 1999-04-26 三菱電機株式会社 半導体装置の製造方法
US5407841A (en) * 1992-10-30 1995-04-18 Hughes Aircraft Company CBiCMOS fabrication method using sacrificial gate poly
US5338750A (en) * 1992-11-27 1994-08-16 Industrial Technology Research Institute Fabrication method to produce pit-free polysilicon buffer local oxidation isolation
US5496750A (en) * 1994-09-19 1996-03-05 Texas Instruments Incorporated Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition
FR2756103B1 (fr) * 1996-11-19 1999-05-14 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos et d'un condensateur
US6352899B1 (en) * 2000-02-03 2002-03-05 Sharp Laboratories Of America, Inc. Raised silicide source/drain MOS transistors having enlarged source/drain contact regions and method
JP4870873B2 (ja) * 2001-03-08 2012-02-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
FR2854494A1 (fr) * 2003-05-02 2004-11-05 St Microelectronics Sa Procede de fabrication d'un transistor bipolaire
US7772653B1 (en) * 2004-02-11 2010-08-10 National Semiconductor Corporation Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors
WO2006109221A2 (en) * 2005-04-13 2006-10-19 Nxp B.V. Lateral bipolar transistor
US8999791B2 (en) * 2013-05-03 2015-04-07 International Business Machines Corporation Formation of semiconductor structures with variable gate lengths

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4127931A (en) * 1974-10-04 1978-12-05 Nippon Electric Co., Ltd. Semiconductor device
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production
JPS54140483A (en) * 1978-04-21 1979-10-31 Nec Corp Semiconductor device
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US4381953A (en) * 1980-03-24 1983-05-03 International Business Machines Corporation Polysilicon-base self-aligned bipolar transistor process
JPS56160034A (en) * 1980-05-14 1981-12-09 Fujitsu Ltd Impurity diffusion
JPS5748269A (en) * 1980-09-05 1982-03-19 Toshiba Corp Semiconductor device
FR2508704B1 (fr) * 1981-06-26 1985-06-07 Thomson Csf Procede de fabrication de transistors bipolaires integres de tres petites dimensions
US4483726A (en) * 1981-06-30 1984-11-20 International Business Machines Corporation Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area
JPS59161069A (ja) * 1983-03-04 1984-09-11 Oki Electric Ind Co Ltd Mos型半導体装置の製造方法
DE3330895A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen
JPS59139678A (ja) * 1984-01-17 1984-08-10 Hitachi Ltd 半導体装置
JPH06101475B2 (ja) * 1984-02-27 1994-12-12 株式会社日立製作所 半導体装置の製造方法
JPS60245171A (ja) * 1984-05-18 1985-12-04 Matsushita Electric Ind Co Ltd 半導体集積回路装置の製造方法
JPS615580A (ja) * 1984-06-19 1986-01-11 Toshiba Corp 半導体装置の製造方法
EP0166923A3 (de) * 1984-06-29 1987-09-30 International Business Machines Corporation Hochleistungsbipolartransistor mit einem zwischen dem Emitter und der Extrinsic-Basiszone angeordneten leicht dotierten Schutzring
DE3580206D1 (de) * 1984-07-31 1990-11-29 Toshiba Kawasaki Kk Bipolarer transistor und verfahren zu seiner herstellung.

Also Published As

Publication number Publication date
EP0252206A3 (en) 1988-08-31
EP0252206A2 (de) 1988-01-13
EP0252206B1 (de) 1992-07-15
JPS6316673A (ja) 1988-01-23
DE3780369T2 (de) 1993-03-04
JPH0628266B2 (ja) 1994-04-13
US4735916A (en) 1988-04-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee