KR100307272B1 - Mos소자제조방법 - Google Patents
Mos소자제조방법 Download PDFInfo
- Publication number
- KR100307272B1 KR100307272B1 KR1019910022101A KR910022101A KR100307272B1 KR 100307272 B1 KR100307272 B1 KR 100307272B1 KR 1019910022101 A KR1019910022101 A KR 1019910022101A KR 910022101 A KR910022101 A KR 910022101A KR 100307272 B1 KR100307272 B1 KR 100307272B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- gate electrode
- insulating film
- conductor
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
- H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (6)
- 반도체 기판 상에 게이트 절연막을 형성하는 단계,상기 게이트 절연막 상에 게이트 전극막을 형성하는 단계,상기 게이트 전극막 상에 제 1 절연막을 형성하는 단계,제 1 패턴화된 포토레지스트 막을 마스크로서 사용하여, 상기 게이트 전극막과 제 1 절연막을 패턴화하는 단계,패턴화된 게이트 전극막을 마스크로서 사용하여, 상기 반도체 기판의 표면상에 불순물 소스 및 드레인층을 형성하는 단계,상기 게이트 절연막과 제 1 절연막의 노출된 표면 상에 제 2 절연막을 형성하는 단계,상기 게이트 전극의 측벽 상에 측벽 절연막을 형성하기 위하여 상기 제 2 절연막을 에칭하는 단계,상기 반도체 기판, 제 1 절연막 및 측벽 절연막의 노출된 표면 상에 도체막을 형성하는 단계,상기 도체막의 편평면을 가진 평탄화막을 형성하는 단계 및,제 2 패턴화된 포토레지스트 막을 마스크로서 사용하여, 상기 게이트 전극막위에 있는 도체막과 평탄화막의 영역을 에칭하는 단계를 포함하는 MOS 소자 제조 방법.
- 제 1 항에 있어서,상기 제 1 및 제 2 절연막들은 질화 실리콘막들인 MOS 소자 제조 방법,
- 제 1 항에 있어서,상기 측벽 절연막은 이방성 에칭에 의해 형성되는 MOS 소자 제조 방법.
- 반도체 기판 상에 게이트 절연막을 형성하는 단계,상기 게이트 절연막 상에 게이트 전극막을 형성하는 단계,상기 게이트 전극막 상에 제 1 절연막을 형성하는 단계,제 1 패턴화된 포토레지스트 막을 마스크로서 사용하여, 상기 게이트 전극막과 제 1 절연막을 패턴화하는 단계,패턴화된 게이트 전극막을 마스크로서 사용하여, 상기 반도체 기판의 표면상에 저농도 불순물 소스 및 드레인층을 형성하는 단계,상기 게이트 절연막과 제 1 절연막의 노출된 표면 상에 제 2 절연막을 형성하는 단계,상기 게이트 전극의 측벽 상에 측벽 절연막을 형성하기 위하여 상기 제 2 절연막을 에칭하는 단계,상기 측벽 절연막이 있는 상기 패턴화된 게이트 전극막을 마스크로서 사용하여, 상기 반도체 기판의 표면 상에 고농도 불순물 소스 및 드레인층을 형성하는 단계,상기 반도체 기판, 제 1 절연막 및 측벽 절연막의 노출된 표면 상에 도체막을 형성하는 단계,상기 도체막 상에 편평한 면을 가진 평탄화막을 형성하는 단계 및,형성된 제 2 패턴화된 포토레지스트 막을 마스크로서 사용하여, 상기 게이트 전극막 위에 있는 상기 평탄화막과 도체막의 영역을 에칭하는 단계를 포함하는 MOS 소자 제조 방법.
- 제 4 항에 있어서,상기 제 1 및, 제 2 절연막들은 질화 실리콘막들인 MOS 소자 제조 방법.
- 제 4 항에 있어서,상기 측벽 절연막은 이방성 에칭에 의해 형성되는 MOS 소자 제조 방법.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP90-400357 | 1990-12-04 | ||
| JP2400357A JP3007994B2 (ja) | 1990-12-04 | 1990-12-04 | Ｍｏｓ半導体装置の製造方法 |
| JP90-400711 | 1990-12-06 | ||
| JP2400712A JPH04209544A (ja) | 1990-12-06 | 1990-12-06 | 半導体装置の製造方法 |
| JP90-400712 | 1990-12-06 | ||
| JP40071190A JPH04209543A (ja) | 1990-12-06 | 1990-12-06 | 半導体装置の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR100307272B1 true KR100307272B1 (ko) | 2002-05-01 |
Family
ID=27480869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910022101A Expired - Lifetime KR100307272B1 (ko) | 1990-12-04 | 1991-12-04 | Mos소자제조방법 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6544852B1 (ko) |
| KR (1) | KR100307272B1 (ko) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9089323B2 (en) | 2005-02-22 | 2015-07-28 | P Tech, Llc | Device and method for securing body tissue |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6116571A (ja) * | 1984-07-03 | 1986-01-24 | Ricoh Co Ltd | 半導体装置の製造方法 |
| KR890004962B1 (ko) * | 1985-02-08 | 1989-12-02 | 가부시끼가이샤 도오시바 | 반도체장치 및 그 제조방법 |
| JPH0628266B2 (ja) * | 1986-07-09 | 1994-04-13 | 株式会社日立製作所 | 半導体装置の製造方法 |
| FR2603128B1 (fr) * | 1986-08-21 | 1988-11-10 | Commissariat Energie Atomique | Cellule de memoire eprom et son procede de fabrication |
| US4902640A (en) * | 1987-04-17 | 1990-02-20 | Tektronix, Inc. | High speed double polycide bipolar/CMOS integrated circuit process |
| JPS63276271A (ja) * | 1987-05-08 | 1988-11-14 | Fujitsu Ltd | Ｍｏｓ電界効果トランジスタの製造方法 |
| US4994402A (en) * | 1987-06-26 | 1991-02-19 | Hewlett-Packard Company | Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device |
| JPS6410772A (en) * | 1987-07-02 | 1989-01-13 | Tokyo Electric Co Ltd | Original reader |
| US5236851A (en) * | 1988-07-14 | 1993-08-17 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor devices |
| US5010039A (en) * | 1989-05-15 | 1991-04-23 | Ku San Mei | Method of forming contacts to a semiconductor device |
| FR2654258A1 (fr) * | 1989-11-03 | 1991-05-10 | Philips Nv | Procede pour fabriquer un dispositif a transistor mis ayant une electrode de grille en forme de "t" inverse. |
| US5022958A (en) * | 1990-06-27 | 1991-06-11 | At&T Bell Laboratories | Method of etching for integrated circuits with planarized dielectric |
| US5180689A (en) * | 1991-09-10 | 1993-01-19 | Taiwan Semiconductor Manufacturing Company | Tapered opening sidewall with multi-step etching process |
-
1991
- 1991-12-04 KR KR1019910022101A patent/KR100307272B1/ko not_active Expired - Lifetime
-
1993
- 1993-07-19 US US08/093,983 patent/US6544852B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6544852B1 (en) | 2003-04-08 |
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