DE3587843D1 - Speicherzugriffsteuerungsanordnung. - Google Patents

Speicherzugriffsteuerungsanordnung.

Info

Publication number: DE3587843D1
Authority: DE; Germany
Prior art keywords: access control; memory access; control arrangement; arrangement; memory
Prior art date: 1984-06-21
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE3587843T

Other languages

English (en)

Other versions

DE3587843T2 (de

Inventor

Takashi Chiba

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Fujitsu Ltd

Original Assignee

Fujitsu Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-06-21

Filing date

1985-06-21

Publication date

1994-07-14

1985-06-21 Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd

1994-07-14 Publication of DE3587843D1 publication Critical patent/DE3587843D1/de

1994-09-15 Application granted granted Critical

1994-09-15 Publication of DE3587843T2 publication Critical patent/DE3587843T2/de

2005-06-22 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Dram (AREA)
Multi Processors (AREA)
Memory System (AREA)
Memory System Of A Hierarchy Structure (AREA)

DE3587843T 1984-06-21 1985-06-21 Speicherzugriffsteuerungsanordnung. Expired - Fee Related DE3587843T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP59127805A JPS618785A (ja)	1984-06-21	1984-06-21	記憶装置アクセス制御方式

Publications (2)

Publication Number	Publication Date
DE3587843D1 true DE3587843D1 (de)	1994-07-14
DE3587843T2 DE3587843T2 (de)	1994-09-15

Family

ID=14969111

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE3587843T Expired - Fee Related DE3587843T2 (de)	1984-06-21	1985-06-21	Speicherzugriffsteuerungsanordnung.

Country Status (9)

Country	Link
US (1)	US4866603A (de)
EP (1)	EP0165822B1 (de)
JP (1)	JPS618785A (de)
KR (1)	KR910001448B1 (de)
AU (1)	AU560427B2 (de)
BR (1)	BR8502966A (de)
CA (1)	CA1240069A (de)
DE (1)	DE3587843T2 (de)
ES (1)	ES8609770A1 (de)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4791552A (en) *	1986-01-29	1988-12-13	Digital Equipment Corporation	Apparatus and method for addressing semiconductor arrays in a main memory unit on consecutive system clock cycles
EP0261751A3 (de) *	1986-09-25	1990-07-18	Tektronix, Inc.	Simultanes Speicherzugriffssystem
EP0315550A3 (de) *	1987-11-06	1989-10-25	Oryx Corporation	Hochparallele Rechnerbauweise unter Verwendung eines Koordinatenschalters mit ausgewählter Pipelineverzögerung
US5081575A (en) *	1987-11-06	1992-01-14	Oryx Corporation	Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
US4918587A (en) *	1987-12-11	1990-04-17	Ncr Corporation	Prefetch circuit for a computer memory subject to consecutive addressing
GB2216307B (en) *	1988-03-01	1992-08-26	Ardent Computer Corp	Vector register file
JP2895488B2 (ja) *	1988-04-18	1999-05-24	株式会社東芝	半導体記憶装置及び半導体記憶システム
USRE39529E1 (en) *	1988-04-18	2007-03-27	Renesas Technology Corp.	Graphic processing apparatus utilizing improved data transfer to reduce memory size
JPH02156349A (ja) *	1988-12-08	1990-06-15	Nec Corp	メモリ制御装置
KR930007185B1 (ko) *	1989-01-13	1993-07-31	가부시키가이샤 도시바	레지스터뱅크회로
JPH0740241B2 (ja) *	1989-01-17	1995-05-01	富士通株式会社	リクエストキャンセル方式
CA1324679C (en) *	1989-02-03	1993-11-23	Michael A. Gagliardo	Method and means for interfacing a system control unit for a multi-processor system with the system main memory
JPH0775006B2 (ja) *	1989-03-16	1995-08-09	株式会社日立製作所	記憶装置の制御方法
US5091851A (en) *	1989-07-19	1992-02-25	Hewlett-Packard Company	Fast multiple-word accesses from a multi-way set-associative cache memory
JP3039557B2 (ja) *	1989-11-01	2000-05-08	日本電気株式会社	記憶装置
DE69122520T2 (de) *	1990-01-31	1997-02-13	Hewlett Packard Co	Vielfachbus-Systemspeicherarchitektur
JP3215105B2 (ja) *	1990-08-24	2001-10-02	富士通株式会社	メモリアクセス装置
GB9018990D0 (en) *	1990-08-31	1990-10-17	Ncr Co	Register control for workstation interfacing means
US5303309A (en) *	1990-09-18	1994-04-12	E-Mu Systems, Inc.	Digital sampling instrument
JPH04270440A (ja) *	1991-02-26	1992-09-25	Fujitsu Ltd	アクセス方式
US5289584A (en) *	1991-06-21	1994-02-22	Compaq Computer Corp.	Memory system with FIFO data input
CA2116985C (en) *	1993-03-11	1999-09-21	Cynthia J. Burns	Memory system
TW357295B (en) *	1994-02-08	1999-05-01	United Microelectronics Corp	Microprocessor's data writing, reading operations
US6301299B1 (en) *	1994-10-28	2001-10-09	Matsushita Electric Industrial Co., Ltd.	Memory controller for an ATSC video decoder
US5644780A (en) *	1995-06-02	1997-07-01	International Business Machines Corporation	Multiple port high speed register file with interleaved write ports for use with very long instruction word (vlin) and n-way superscaler processors
FR2748595B1 (fr) *	1996-05-10	1998-07-10	Sgs Thomson Microelectronics	Memoire a acces parallele
US6026473A (en) *	1996-12-23	2000-02-15	Intel Corporation	Method and apparatus for storing data in a sequentially written memory using an interleaving mechanism
US5959929A (en) *	1997-12-29	1999-09-28	Micron Technology, Inc.	Method for writing to multiple banks of a memory device
KR100313503B1 (ko) *	1999-02-12	2001-11-07	김영환	멀티-뱅크 메모리 어레이를 갖는 반도체 메모리 장치
KR100328726B1 (ko) *	1999-04-29	2002-03-20	한탁돈	메모리 엑세스 시스템 및 그 제어방법
US6377502B1 (en) *	1999-05-10	2002-04-23	Kabushiki Kaisha Toshiba	Semiconductor device that enables simultaneous read and write/erase operation
US6438024B1 (en) *	2001-01-11	2002-08-20	Sun Microsystems, Inc.	Combining RAM and ROM into a single memory array
DE10121745A1 (de)	2001-05-04	2002-11-14	Systemonic Ag	Verfahren und Anordnung zu einem Stack mit einem, in Datengruppen mit mehreren Elementen aufgeteilten Speicher
US6839797B2 (en)	2001-12-21	2005-01-04	Agere Systems, Inc.	Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem
US8250295B2 (en)	2004-01-05	2012-08-21	Smart Modular Technologies, Inc.	Multi-rank memory module that emulates a memory module having a different number of ranks
US7289386B2 (en) *	2004-03-05	2007-10-30	Netlist, Inc.	Memory module decoder
US7532537B2 (en) *	2004-03-05	2009-05-12	Netlist, Inc.	Memory module with a circuit providing load isolation and memory domain translation
US7916574B1 (en)	2004-03-05	2011-03-29	Netlist, Inc.	Circuit providing load isolation and memory domain translation for memory module
US8595459B2 (en) *	2004-11-29	2013-11-26	Rambus Inc.	Micro-threaded memory
US20060277355A1 (en) *	2005-06-01	2006-12-07	Mark Ellsberry	Capacity-expanding memory device
KR20090065504A (ko)	2006-12-25	2009-06-22	파나소닉 주식회사	메모리 제어 장치, 메모리 장치 및 메모리 제어 방법
US8154901B1 (en)	2008-04-14	2012-04-10	Netlist, Inc.	Circuit providing load isolation and noise reduction
US8516185B2 (en)	2009-07-16	2013-08-20	Netlist, Inc.	System and method utilizing distributed byte-wise buffers on a memory module
US8417870B2 (en)	2009-07-16	2013-04-09	Netlist, Inc.	System and method of increasing addressable memory space on a memory board
US9128632B2 (en)	2009-07-16	2015-09-08	Netlist, Inc.	Memory module with distributed data buffers and method of operation
KR101292309B1 (ko) *	2011-12-27	2013-07-31	숭실대학교산학협력단	반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
KR20160038034A (ko)	2013-07-27	2016-04-06	넷리스트 인코포레이티드	로컬 동기화를 갖는 메모리 모듈
WO2019134028A1 (en)	2018-01-02	2019-07-11	Reed Scientific Services Ltd.	A soil-based flow-through rhizosphere system for treatment of contaminated water and soil
DE102021107045B4 (de)	2021-03-10	2024-11-21	Elmos Semiconductor Se	Rechnersystem für eine Motorsteuerung mit einem Programmspeicher und einem Datenspeicher

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
BE755034A (fr) *	1969-08-19	1971-02-19	Siemens Ag	Installation de traitement d'informations a commande centrale programmepar memoire
JPS5410219B2 (de) *	1973-12-07	1979-05-02
US4099231A (en) *	1975-10-01	1978-07-04	Digital Equipment Corporation	Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle
JPS5475941A (en) *	1977-11-30	1979-06-18	Fujitsu Ltd	Control system for memory unit
US4298929A (en) *	1979-01-26	1981-11-03	International Business Machines Corporation	Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability
US4317168A (en) *	1979-11-23	1982-02-23	International Business Machines Corporation	Cache organization enabling concurrent line castout and line fetch transfers with main storage
JPS5736353A (ja) *	1980-08-13	1982-02-27	Toshiba Corp	Memoriakusesuhoshiki
JPS57105879A (en) *	1980-12-23	1982-07-01	Hitachi Ltd	Control system for storage device
JPS57113165A (en) *	1980-12-29	1982-07-14	Fujitsu Ltd	Data processor
US4438493A (en) *	1981-07-06	1984-03-20	Honeywell Information Systems Inc.	Multiwork memory data storage and addressing technique and apparatus
US4439827A (en) *	1981-12-28	1984-03-27	Raytheon Company	Dual fetch microsequencer
JPS58149548A (ja) *	1982-03-02	1983-09-05	Hitachi Ltd	メモリ制御方式
US4513372A (en) *	1982-11-15	1985-04-23	Data General Corporation	Universal memory
JPS6015771A (ja) *	1983-07-08	1985-01-26	Hitachi Ltd	ベクトルプロセッサ
JPS60157646A (ja) *	1984-01-27	1985-08-17	Mitsubishi Electric Corp	メモリバンク切換装置
JPH0670773B2 (ja) *	1984-11-01	1994-09-07	富士通株式会社	先行制御方式
JPS62194561A (ja) *	1986-02-21	1987-08-27	Toshiba Corp	半導体記憶装置

1984
- 1984-06-21 JP JP59127805A patent/JPS618785A/ja active Granted
1985
- 1985-06-14 CA CA000484012A patent/CA1240069A/en not_active Expired
- 1985-06-17 AU AU43733/85A patent/AU560427B2/en not_active Ceased
- 1985-06-20 KR KR1019850004386A patent/KR910001448B1/ko not_active IP Right Cessation
- 1985-06-20 ES ES544377A patent/ES8609770A1/es not_active Expired
- 1985-06-20 BR BR8502966A patent/BR8502966A/pt not_active IP Right Cessation
- 1985-06-21 EP EP85304442A patent/EP0165822B1/de not_active Expired - Lifetime
- 1985-06-21 DE DE3587843T patent/DE3587843T2/de not_active Expired - Fee Related
1988
- 1988-01-20 US US07/147,071 patent/US4866603A/en not_active Expired - Lifetime

Also Published As

Publication number	Publication date
ES544377A0 (es)	1986-07-16
EP0165822A2 (de)	1985-12-27
EP0165822A3 (en)	1989-02-22
EP0165822B1 (de)	1994-06-08
BR8502966A (pt)	1986-03-04
JPH0363096B2 (de)	1991-09-30
AU560427B2 (en)	1987-04-09
US4866603A (en)	1989-09-12
KR910001448B1 (ko)	1991-03-07
ES8609770A1 (es)	1986-07-16
KR860000601A (ko)	1986-01-29
DE3587843T2 (de)	1994-09-15
JPS618785A (ja)	1986-01-16
CA1240069A (en)	1988-08-02
AU4373385A (en)	1986-01-02

Publication	Publication Date	Title
DE3587843D1 (de)	1994-07-14	Speicherzugriffsteuerungsanordnung.
DE3687787D1 (de)	1993-03-25	Speicherzugriff-steuerungsschaltung.
DE3584694D1 (de)	1992-01-02	Dynamischer direktzugriffspeicher.
DE3485166D1 (de)	1991-11-21	Speichersteuergeraet.
DE3585711D1 (de)	1992-04-30	Halbleiterspeicheranordnung.
FI861686A0 (fi)	1986-04-22	Kontroll av blodfloede.
DE3587400D1 (de)	1993-07-22	Datenspeicherungsanordnung.
DE3782756D1 (de)	1993-01-07	Direktzugriffspeichereinrichtung.
DE3582141D1 (de)	1991-04-18	Speicheranordnung.
DE3587329D1 (de)	1993-06-17	Speicheranordnung mit datenzugriffsteuerung.
DE3583091D1 (de)	1991-07-11	Halbleiterspeicheranordnung.
DE3577944D1 (de)	1990-06-28	Halbleiterspeicheranordnung.
DE3582376D1 (de)	1991-05-08	Halbleiterspeicheranordnung.
DE3586377D1 (de)	1992-08-27	Halbleiterspeicheranordnung.
DE3576236D1 (de)	1990-04-05	Halbleiterspeicheranordnung.
DE3577367D1 (de)	1990-05-31	Halbleiterspeicheranordnung.
DE3585811D1 (de)	1992-05-14	Direktzugriffsspeicher.
DE3586556D1 (de)	1992-10-01	Halbleiterspeicheranordnung.
DE3575225D1 (de)	1990-02-08	Halbleiterspeicheranordnung.
DE3580993D1 (de)	1991-02-07	Halbleiterspeicheranordnung.
DE3576754D1 (de)	1990-04-26	Halbleiterspeicheranordnung.
DE68925048D1 (de)	1996-01-25	Direktspeicherzugriffssteuerung
DE3586675D1 (de)	1992-10-29	Halbleiterspeicheranordnung.
DE3578254D1 (de)	1990-07-19	Halbleiterspeicheranordnung.
DE3582960D1 (de)	1991-07-04	Halbleiterspeicheranordnung.

Legal Events

Date	Code	Title	Description
1995-07-06	8364	No opposition during term of opposition
2003-04-10	8339	Ceased/non-payment of the annual fee