CN1428818A

CN1428818A - Method for realizing planarization of ceramic substrate surface by using porous material

Info

Publication number: CN1428818A
Application number: CN 01138678
Authority: CN
Inventors: 徐文泰; 卢荣宏; 廖圣茹; 张怀禄; 洪松慰; 黄瑞呈
Original assignee: Industrial Technology Research Institute ITRI
Current assignee: Industrial Technology Research Institute ITRI
Priority date: 2001-12-28
Filing date: 2001-12-28
Publication date: 2003-07-09
Anticipated expiration: 2021-12-28
Also published as: CN1196174C

Abstract

The invention relates to a method for realizing ceramic substrate surface planarization by using porous material, which can meet the requirement of providing subsequent film layer adhesive force, can be applied to structures such as a substrate, a buffer layer, a porous nanostructure layer and the like, and provides the flat surface required by a film processing technology, the adhesive force of subsequent metallization and electronic material, heat conduction, electric insulation, dielectric and other characteristics required by integrated electronic elements on the porous nanostructure layer; the buffer layer is used for connecting the substrate and the porous nanostructure layer; the ceramic substrate provides structural strength and surface anchoring.

Description

Utilize porous material to realize the method for ceramic base plate surface planarization

Technical field

The present invention relates to a kind of method of utilizing porous material to realize the ceramic base plate surface planarization,, especially can be applicable to the planarization of base material in present electronic information communication, photoelectricity, the display industry to satisfy the requirement that subsequent film adhesive force is provided.

Background technology

In present thin-film component processing procedure, the requirement of surface flatness is quite important, is the manufacturing industry of base material with wafer or glass especially, and the processing of substrate surface planarization need be paid suitable cost; In addition, the planarization of metallization module in the integrated circuit manufacture process also is the key that element is made success or not.

At present, processing method about flattening surface, general mechanical milling method, chemical mechanical milling method (the chemical mechanical polishing of adopting, CMP), the high temperature density current of chemical method for etching, boron-phosphorosilicate glass (BPSG) or spin-on glasses method (SOG), utilize surface flatness or adhesion of thin film (adhesion) after these modes are handled that certain limitation is all arranged, and processing procedure complexity, manufacturing cost are too high, Figure 1 shows that prior art flattening method comparison sheet.

Summary of the invention

Main purpose of the present invention, be to solve above-mentioned defective, avoid the existence of defective, the invention provides a kind of method of utilizing porous material to realize the ceramic base plate surface planarization, to satisfy the requirement that subsequent film adhesive force is provided, utilize porous material to impel the ceramic base plate surface planarization and promote the adhesive force of rete, simplify existing planarization processing procedure, reduce manufacturing cost.

For realizing above-mentioned purpose, a kind of method of utilizing porous material to realize the ceramic base plate surface planarization provided by the invention, form a resilient coating 20 and a porous nanometer structure layer 10 in regular turn in a substrate 30, this porous nanometer structure layer 10 provides the required smooth surperficial and required pinning effect of following of thin film manufacture process technology, adhesive force and heat conduction, electric insulation, dielectric and the required characteristic of other integration electronic component to meet follow-up metallization and electronic material.

Description of drawings

Fig. 1 is a prior art flattening method comparison sheet.

Fig. 2 is the structural representation of porous nanometer structure of the present invention to substrate planarization mechanism.

Fig. 3 is the collection of illustrative plates that the X-x-ray diffraction observation post of the embodiment of the invention one gets.

Fig. 4 is the sem observation photo of the embodiment of the invention one.

Fig. 5 is the result of the surface measurements flatness gained of the embodiment of the invention one.

Fig. 6-1 is the adhesive force resolution chart of the embodiment of the invention one, is illustrated in the planarization substrate and plates 6.5 μ m aluminium films and etch the aluminum steel schematic diagram with the light shield etching mode.

Fig. 6-2 is the optics picture that plates 6.5 μ m aluminium films on the embodiment of the invention one planarization substrate and etch aluminum steel with the light shield etching mode.

The electric characteristics figure of Fig. 7-1 diode of on flat substrate, making for the embodiment of the invention one.

Fig. 7-2 is that the embodiment of the invention one is made the integrated circuit schematic diagram on flat substrate.

Embodiment

The invention provides a kind of method of utilizing porous material to realize the ceramic base plate surface planarization, be on substrate 30, to form a resilient coating 20 and a porous nanometer structure layer 10 in regular turn, utilize porous material to realize the requirement of ceramic base plate surface planarization with coupling subsequent film adhesive force, wherein porous nanometer structure layer 10 provides the thin film manufacture process technology required smooth surface and the required pinning effect of following, with adhesive force and the heat conduction that meets follow-up metallization and electronic material, electric insulation, dielectric and other are integrated the required characteristic of electronic component, its material is selected from zeolite, the class zeolite, mesoporous material, the group that porous materials such as mesoporous multiple material are formed, or formed by at least a above material in this group.Resilient coating 20 provide substrate 30 and porous nanometer structure layer 10 then, its material is selected from the group that glaze, glass, pottery, mesoporous material, mesoporous multiple material are formed, or is made up of wherein at least a above material of this group; Substrate 30 provides structural strength and surperficial set, and resilient coating 20 can with porous nanometer structure layer 10 by being constituted with one deck or by multilayer.

The method of utilizing porous material to realize the ceramic base plate surface planarization of the present invention is to utilize control porous nanometer structure layer 10 structure to provide substrate to have heat conduction, electric insulation, dielectric and other to integrate the required characteristic of electronic component and can be applicable to low-temp ceramics and burn any integrated component substrates that combine such as (LTCC), chip carrier, passive device, active member, light-emitting component, light passive device and light active member altogether.

Now concrete technology of the present invention is divided into three aspects such as flatness, adhesion strength and exploitativeness, conjunction with figs. is described as follows.

Embodiment one: the flatness test

Be illustrated in figure 2 as the structural representation of porous nanometer structure of the present invention to substrate planarization mechanism, can form a resilient coating 20 and a porous nanometer structure layer 10 on a substrate 30 in regular turn, substrate 30 is that aluminium oxide material, resilient coating 20 are the class zeolite for glaze, porous nanometer structure layer 10.The collection of illustrative plates that Fig. 3 gets with X-x-ray diffraction (XRD) observation post for present embodiment, wherein the crest of X-x-ray diffraction collection of illustrative plates is caused from forming the structural cycle arrangement by the class zeolite.As shown in Figure 4, the photo that gets with sweep electron microscope (SEM) observation post for present embodiment, but clear view is to the structure of this substrate 30, resilient coating 20 and porous nanometer structure layer 10 after sweep electron microscope amplifies, Fig. 5 then is the result of surface measurements flatness gained, the maximum drop amount of curve in its collection of illustrative plates (curve) dipping and heaving is shown in the collection of illustrative plates, this measurement result confirmation the present invention surface flatness that planarization has a dust () size level to substrate surface.

Embodiment two: the absorption affinity test

Be depicted as the adhesive force resolution chart of the embodiment of the invention one as Fig. 6-1, being illustrated in the planarization substrate plates 6.5 μ m aluminium films and etches the aluminum steel schematic diagram with the light shield etching mode, and Fig. 6-2 etches the optics picture of aluminum steel for plating 6.5 μ m aluminium films on the planarization substrate of present embodiment and with the light shield etching mode, shows that by α-step measurement result this sample had both made the aluminium thickness reach 6.5 μ m and still had splendid adhesive force.

Embodiment three: the exploitativeness test

Be depicted as the electric characteristics figure of the diode that the embodiment of the invention makes on flat substrate as Fig. 7-1, Fig. 7-2 is that the embodiment of the invention is made RLCD integrated circuit schematic diagram on flat substrate, be presented at can make on the planarization substrate and have diode (diode) and RLCD integrated circuit, the substrate after the planarization of confirmation present embodiment possesses exploitativeness.

The present invention discloses and has described selected preferred embodiment especially, can not limit scope of the invention process with it, be that all persons skilled in the art all can understand, do variation possible on any form or the details according to the present patent application claim, all do not break away from spirit and scope that patent of the present invention contains.

Claims

1. A method for using a porous material to planarize the surface of a ceramic substrate, characterized in that: a buffer layer 20 and a porous nanostructure layer 10 are sequentially formed on the substrate 30 .

2. The method for planarizing the surface of a ceramic substrate by using a porous material according to claim 1, wherein the material of the porous nanostructure layer 10 can be a zeolite, a zeolite, a mesoporous substance, or a mesoporous composite material.

3. The method for using porous materials to planarize the surface of ceramic substrates according to claim 1, wherein the material of the buffer layer 20 can be selected from glazes, glass, ceramics, mesoporous substances, and mesoporous composite materials, and the buffer layer 20 can be the same layer as the porous nanostructure layer 10 or consist of multiple layers.

4. The method for utilizing porous materials to realize ceramic substrate surface planarization according to claim 1, characterized in that: the control of the porous nanostructure layer structure is used to provide the substrate with thermal conductivity, electrical insulation, dielectric and other integrated electronic components. The required characteristics are used as the substrate of passive components such as resistors (R), inductors (L), capacitors (C) and integrated passive components.

5. The method of utilizing porous materials to realize the flattening of ceramic substrate surfaces according to claim 1, characterized in that: the control of the structure of the porous nanostructure layer 10 is used to provide the substrate with thermal conductivity, electrical insulation, dielectric and other integrated electronic components The required characteristics serve as a substrate for active components such as transistors, diodes, and storage elements, and integrated active components.

6. The method for utilizing porous materials to realize ceramic substrate surface planarization according to claim 1, characterized in that: utilizing the structure of the porous nanostructure layer 10 to provide the substrate with thermal conductivity, electrical insulation, dielectric and other integrated electronic components The required characteristics are used as substrates for light-emitting elements such as laser diodes, light-emitting diodes (LEDs), and field emission sources (Field Emitter).

7. The method of utilizing porous materials to realize the flattening of the ceramic substrate surface according to claim 1, characterized in that: utilizing the control of the structure of the porous nanostructure layer 10, the substrate has thermal conductivity, electrical insulation, dielectric and other integrated electronic components The required characteristics are used as substrates for optical passive components such as optical waveguides and photodetectors, and integrated optical passive components.

8. The method for utilizing porous materials to realize planarization of the surface of ceramic substrates according to claim 1, characterized in that: the structure of the control porous nanostructure layer 10 is used to provide the substrate with thermal conductivity, electrical insulation, dielectric and other integrated electronic components The required characteristics are used as substrates for optical active components such as optical amplifiers, optical switches, and optical adjustments, and integrated optical active components.

9. The method of utilizing porous materials to realize the flattening of the ceramic substrate surface according to claim 1, characterized in that: the control of the structure of the porous nanostructure layer 10 is used to provide the substrate with thermal conductivity, electrical insulation, dielectric and other integrated electronic components The required characteristics are used as the substrate of an integrated component formed by any combination of passive components, active components, light-emitting components, optical passive components, and optical active components described in claims 4 to 8.

10. The method of utilizing porous materials to realize the flattening of the ceramic substrate surface according to claim 1, characterized in that: the structure of the control porous nanostructure layer 10 is used to provide the substrate with thermal conductivity, electrical insulation, dielectric and other integrated electronic components The required properties are integrated as a chip carrier (Chip-Carrier) with any one of claims 4 to 9.

11. The method of utilizing porous materials to realize the flattening of ceramic substrate surfaces according to claim 1, characterized in that: the control of the structure of the porous nanostructure layer 10 provides the substrate with thermal conductivity, electrical insulation, dielectric and other integrated electronic components The required characteristics are performed on low-temperature ceramic co-firing (LTCC), which can be integrated with any one of claims 4 to 10, so as to establish a thick-film and thin-film process integration technology.