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CN1266277A - 形成cmos器件的双金属栅结构的方法 - Google Patents

形成cmos器件的双金属栅结构的方法 Download PDF

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CN1266277A
CN1266277A CN00103629A CN00103629A CN1266277A CN 1266277 A CN1266277 A CN 1266277A CN 00103629 A CN00103629 A CN 00103629A CN 00103629 A CN00103629 A CN 00103629A CN 1266277 A CN1266277 A CN 1266277A
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G·D·维尔克
S·R·萨默费尔特
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Abstract

在半导体衬底上形成分别具有第一和第二栅极的第一和第二晶体管的方法,包括:形成绝缘地置于半导体衬底上的有一功函数的导电材料;转换导电材料的一部分从而改变其功函数,导电材料和被转换的导电材料分别形成第一和第二栅极。第一和第二晶体管分别为NMOS和PMOS器件,第一和第二晶体管形成CMOS器件。导电材料包括Ta、Mo、Ti及其任意组合。转换步骤包括使导电材料的这部分经受包括含氮气体的等离子体。

Description

形成CMOS器件的双金属栅结构的方法
这里通过参考而引入以下共同转让的专利/专利申请：
专利号/序号    申请日       TI文件号
               **/**/1996   TI-22027
               **/**/1998   TI-22748
               **/**/1998   TI-24776
本发明属于半导体器件制造和加工，尤其涉及制造CMOS器件的金属栅结构的方法。
随着电子器件变得越来越复杂，器件上不断地需要越来越多的晶体管。此外，需要减少功耗，同时提高器件的速度。对这些需求的至少部分答案包括减少每个晶体管所占据的面积。然而，这可能对一个或多个其它需求造成不利影响。更具体来说，随着晶体管按比例缩小，使得栅结构也按比例缩小，这增加了栅极的电阻。因此，功耗增大且器件速度降低。
过去为减少栅结构的片电阻率已进行了几种尝试。首先，以n型或p型杂质对多晶硅进行更重的掺杂。然后，使栅极上部的钨或钛变成硅化物。目前，使用硅化钴从而减少较小几何图形的电阻率。下一个类似的解决方案将涉及金属栅结构。
金属栅结构提供了实际上与栅极宽度无关的较低的片电阻率。然而，必须在把许多金属栅材料应用于标准半导体工艺流程前克服几个问题。一个问题是的许多金属的不稳定性仅次于SiO2，后者通常用于栅介电层。另一个问题是许多金属在氧化时导电率变小。
已使用铝和钨来形成栅结构。由于上述问题，所以铝可能不是一个好的选择，钨具有在p型多晶硅(多晶)和n型多晶的功函数之间的功函数。然而，与钨有关的问题是，随着所加电压变得越来越小，此功函数为中等禁带(midgap)且不可变(与n型和p型多晶相比)，可能难于提供比PMOS和NMOS器件的阈值大的栅极电势。
在对PMOS和NMOS器件使用一中等禁带宽度金属来克服此阈值电压问题的尝试中，已把铝用于一种类型的器件，而把铂用于另一种类型的器件。然而，铂很昂贵且难于加工，而铝将遭受上述问题。因此，需要一种栅极材料，这种材料的导电率与栅极宽度无关，且对PMOS器件和NMOS器件具有不同的功函数。
本发明的一个实施例是一种在半导体衬底上形成具有第一栅极的第一晶体管和具有第二栅极的第二晶体管的方法，该方法包括以下步骤：形成绝缘地置于半导体衬底的第一部分上的第一导电材料，此第一导电材料具有第一功函数；形成绝缘地置于半导体衬底的第二部分上的第二导电材料，此第二导电材料包括第一导电材料但具有不同于第一功函数的第二功函数；其中第一导电材料用于形成第一栅极，而第二导电材料用于形成第二栅极。在一可选实施例中，第一导电材料包括Ta，第二导电材料包括TaxNy。在另一可选实施例中，第一导电材料包括Mo，第二导电材料包括MoxNy。在又一个可选实施例中，第一导电材料包括Ti，第二导电材料包括TixNy。
本发明的另一个实施例是一种在半导体衬底上形成具有第一栅极的第一晶体管和具有第二栅极的第二晶体管的方法，该方法包括以下步骤：形成绝缘地置于半导体衬底上的导电材料，此导电材料具有一功函数；转换此导电材料的一部分，从而改变被转换的导电材料的功函数，此导电材料形成第一栅极而被转换的导电材料形成第二栅极。最好，第一晶体管为NMOS器件，第二晶体管为PMOS器件，且第一晶体管和第二晶体管形成一CMOS器件。导电材料最好包括从以下构成的组中选出的导体：Ta、Mo、Ti及其任意组合。最好，转换导电材料的一部分的步骤包括：使导电材料的这部分经受包括含氮气体的等离子体。
图1是本发明一个实施例的方法的部分制成的CMOS器件的剖面图。
图2是本发明一个实施例的方法的流程图。
图3a-3e是使用图2所示本发明的方法的部分制成的半导体器件的剖面图。
图4是示出不同材料的功函数的图表。
除非特指，不同图中的相同标号指相应的结构。这些图仅仅是说明本发明的概念。这些图不按比例绘制。
大体上，本发明涉及CMOS器件及其制造方法，该器件包括用于NMOS器件或PMOS器件的金属栅极及可用于其它器件即PMOS器件或NMOS器件(分别)栅极的金属转换形式。最好，本发明涉及形成NMOS器件的栅极(至少部.分为钽)以及形成PMOS晶体管的栅极(至少部分为氮化钽)。因此，本发明涉及例如钽等同一种碱金属，但对一种器件的栅极使用碱金属的转换形式。本发明可使用一次性(disposable)栅的方法(基本上如图2和3a-3e所示)或以传统的栅形成方法(基本上如图1所示)来制成本发明。
参考图1，可使用传统的金属来制造本发明的CMOS器件100，或者它可用图2和3a-3e所示的一次性栅的方法来制造。形成栅结构的传统方法包括形成隔离结构118，它可以是LOCOS型隔离结构、浅沟槽隔离结构(STI-在图1中作为隔离结构118示出)或掺杂的隔离区。栅绝缘层与与上面的栅导体层一起形成。在本发明中，栅绝缘层最好包括二氧化硅、氮化硅、介电常数高的材料(诸如PZT、BST、五氧化二钽或其它通常使用的材料)、硅酸盐、以上一种或多种材料的组合、氮氧化合物或其堆层(stack)。栅导电层最好包括可选择性地转换从而改变其功函数的金属。其例子是钛、钽、钼或其它类似金属。在对栅结构进行构图并蚀刻前或在这些步骤后，转化栅导体的一部分，从而改变其功函数。最好，这是通过对这部分导电层(或已构图和蚀刻的栅结构的一部分)进行氮化或使用这部分栅结构上的金属/氮化物/金属堆层从而对这层金属进行退火将使氮四处散布来实现的。由于导电材料相对薄(最好在5到50nm的数量级)，所以可通过在含氮气氛(诸如氨)中对该层的这部分(或已被构图和蚀刻的这些特定栅导体)进行退火，或者使导电层或栅结构的选中部分经受混合成等离子体的含氮气体(最好是N2)对将要氮化的这些部分进行氮化。然而，可与NMOS栅结构分开地形成PMOS栅结构，而非已形成的导电层的氮化部分。因此，一个栅结构可由Ta、Mo或Ti来形成，另一个栅结构可与Ta、Mo或Ti和含氮源(诸如N2)共同淀积。或者，氮化物的形式可包括Ta、Mo或Ti以及含氮层(诸如TaN、MoN或TiN)的堆层，然后可对此氮化物进行退火从而使氮在这些栅结构中四处散布。最好，NMOS器件102的栅导体106将包括Ta、Mo或Ti，而PMOS器件104的栅导体108将包括氮和Ta、Mo、Ti或其组合。
在形成栅结构后，形成源/漏外延(如果使用)和源/漏区114和116。此后接着是标准处理。
本发明的另一个实施例如图2和3a-3e所示。本实施例的细节适用于以上实施例。参考图2的步骤202和图3a，形成隔离结构316。隔离结构316可包括LOCOS、STI或掺杂的隔离区。接着，形成第一和第二无效(dummy)层。第一无效层可包括形成栅绝缘体的材料，或者它可以仅为无效层。如果第一层包括栅绝缘材料(最好为二氧化硅、氮化硅、氮氧化合物、BST、五氧化二钽、硅酸盐或其它栅绝缘材料)，则今后将不除去该层且在步骤214中不形成栅绝缘层324。对第一和第二无效层进行构图和蚀刻，从而形成PMOS器件302和NMOS器件304的无效栅结构。此无效栅结构包括两层。如果底层(层310和311)实际上不包括栅绝缘材料，则底层应包括可被除去而不损坏衬底301或在步骤212中除去时不对周围结构产生不利影响的材料。如果第一层是可除去的层，则第一和第二层可包括相同的材料。因此，结构310和306及311和308将包括相同的材料。最好，这些结构包括在除去时基本上不对下面的衬底301或周围结构(诸如侧壁绝缘体318和319以及平面绝缘材料322)产生不利影响的材料。因此，结构310、306、311和308可包括对下面的硅衬底和氧化物或氮化物侧壁绝缘体可选择性地除去的氮化硅、二氧化硅、多晶硅、硅锗或任何其它材料。
参考图2的步骤204，使用隔离结构316及与其对准的栅结构(结构310/306和311/308)来形成源/漏外延(如果全部)。PMOS器件302的源/漏外延312最好包括p型杂质(诸如硼)，NMOS器件304的源/漏外延314最好包括n型杂质(诸如磷或砷)。
参考图2的步骤206和图3b，形成侧壁绝缘体318和319。侧壁绝缘体318和319可包括热生长的氧化硅、淀积的氧化硅、氮化硅、氮氧化合物或其组合或堆层。参考步骤208，通过把硼掺入衬底来形成源/漏区313，通过把砷或磷掺入衬底来形成源/漏区315。
参考图2的步骤210和图3c，形成绝缘层322。最好，绝缘层322流到晶片上，从而其顶面与一次性的栅结构和侧壁绝缘体大致处于相同高度。然而，绝缘层322可被淀积或流到晶片上，然后使用化学机械抛光(CMP)把它抛光到与一次性的栅结构和侧壁绝缘体同延(co-extensive)。最好，绝缘层包括可流动的氧化物(诸如气凝胶、干凝胶或HSQ)、BPSG、TEOS、PETEOS、PSG、FSG或其它氧化硅材料。
参考图3d和图2的步骤212，除去一次性的栅结构(如果不包括栅绝缘材料，则为结构306和308及结构310和311)。最好，这是如此实现的，从而衬底301、侧壁绝缘体318和319、绝缘层322或栅绝缘体310和311(如果它们是由这些器件所需的栅绝缘材料形成的)基本上不退化或不被蚀刻掉。
参考图2的步骤214，如果结构310和311不包括所需的栅材料且在步骤212中被除去，则形成栅绝缘层324。栅绝缘层324最好包括二氧化硅、氮化硅、氮氧化合物、硅酸盐或k高的材料(诸如BST、五氧化二钽或其它适当的材料)。
在图2的步骤216中形成导体326。最好，导体326包括可选择性地转换从而选择性地改变其功函数的Ta、Mo、Ti或其它适当的导体。然而，导体326的一部分可包括Ta、Mo或Ti，而其它部分包括转换形式的Ta、Mo或Ti(最好是氮化物的形式)。转换的形式可以是Ta、Mo或Ti与氮共同淀积，或者可以是Ta、Mo和/或Ti与氮化物的堆层。最好，导体326包括Ta、Mo或Ti且在后来转换。导体326应足够厚，从而其功函数限定栅极的作用。最好，导体326的厚度在5到50nm左右的数量级(厚度为大致8到10个单位晶胞左右或更大)
在对导体326和绝缘层324进行构图和蚀刻前或在此步骤后，转换一部分(或栅导体之一-导体327)从而改变其功函数。这可通过掩蔽导体326(或导体329)的这一部分并使导体326的暴露部分或导体327经受转换剂来实现。最好，这种转换是通过使晶片经受混合成等离子体的氮气(最好是N2)来产生。此步骤最好在环境温度或300到500℃下进行20秒到2分钟左右。此步骤的目的是基本上把Ta、Mo或Ti完全转化成TaxNy、MoxNy或TixNy。
一旦此转换完成并已对栅结构进行构图和蚀刻，可形成另一导电材料，从而填充栅极的其余部分(如果需要)。最好，此附加的导电材料包括钨、铝或其它导电材料。
虽然这里描述了本发明的特定实施例，但不把它们作为对本发明范围的限制。根据说明书的方法，将使本发明的许多实施例对本领域内的技术人员变得明显起来。本发明的范围仅限于所附的权利要求书。

Claims (9)

1.一种在半导体衬底上形成具有第一栅极的第一晶体管和具有第二栅极的第二晶体管的方法，其特征在于所述方法包括以下步骤：
形成绝缘地置于所述半导体衬底的第一部分上的第一导电材料，所述第一导电材料具有第一功函数；
形成绝缘地置于所述半导体衬底的第二部分上的第二导电材料，所述第二导电材料包括所述第一导电材料但具有不同于所述第一功函数的第二功函数；
其中所述第一导电材料用于形成所述第一栅极，而所述第二导电材料用于形成所述第二栅极。
2.如权利要求1所述的方法，其特征在于所述第一导电材料包括Ta，所述第二导电材料包括TaxNy。
3.如权利要求1所述的方法，其特征在于所述第一导电材料包括Mo，第二导电材料包括MoxNy。
4.如权利要求1所述的方法，其特征在于所述第一导电材料包括Ti，第二导电材料包括TixNy。
5.一种在半导体衬底上形成具有第一栅极的第一晶体管和具有第二栅极的第二晶体管的方法，其特征在于所述方法包括以下步骤：
形成绝缘地置于所述半导体衬底上的导电材料，所述导电材料具有一功函数；以及
转换所述导电材料的一部分，从而改变所述被转换的导电材料的功函数，所述导电材料形成所述第一栅极而所述被转换的导电材料形成所述第二栅极。
6.如权利要求5所述的方法，其特征在于所述第一晶体管为NMOS器件，所述第二晶体管为PMOS器件。
7.如权利要求6所述的方法，其特征在于所述第一晶体管和所述第二晶体管形成一CMOS器件。
8.如权利要求5所述的方法，其特征在于所述导电材料最好包括从以下构成的组中选出的导体：Ta、Mo、Ti及其任意组合。
9.如权利要求5所述的方法，其特征在于转换所述导电材料的一部分的所述步骤包括：使所述导电材料的所述部分经受包括含氮气体的等离子体。
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