CN115579438A - LED chip with inverted silver mirror and preparation method thereof - Google Patents
LED chip with inverted silver mirror and preparation method thereof Download PDFInfo
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Abstract
本发明涉及半导体器件技术领域,尤其涉及一种倒装银镜发光二极管芯片及其制备方法,所述芯片包括:衬底及外延层,所述外延层自下而上依次包括N型半导体层、有源发光层、P型半导体层;所述芯片还包括电流阻挡层、电流扩展层、第一银反射层、布拉格反射层、第二银反射层、金属保护层、第一绝缘保护层、串联金属层、第二绝缘保护层、焊盘层、锡球;其中,布拉格反射层设有布拉格反射层通孔,所述第二银反射层置于布拉格反射层上面,所述第一银反射层置于布拉格反射层通孔下面,所述第一银反射层的正投影面积大于布拉格反射层通孔的面积。本发明通过设置第一银反射层加布拉格反射层加第二银反射层的结构,增强了蓝光发光二极管芯片的发光亮度。
The present invention relates to the technical field of semiconductor devices, in particular to a flip-chip silver mirror light-emitting diode chip and a preparation method thereof. The chip includes: a substrate and an epitaxial layer, and the epitaxial layer includes an N-type semiconductor layer, an N-type semiconductor layer, and a semiconductor layer from bottom to top. Active light-emitting layer, P-type semiconductor layer; the chip also includes a current blocking layer, a current spreading layer, a first silver reflective layer, a Bragg reflective layer, a second silver reflective layer, a metal protection layer, a first insulating protection layer, a series Metal layer, second insulating protection layer, pad layer, tin ball; Wherein, Bragg reflective layer is provided with Bragg reflective layer through hole, and described second silver reflective layer is placed on Bragg reflective layer, and described first silver reflective layer Placed under the through hole of the Bragg reflective layer, the orthographic projection area of the first silver reflective layer is larger than the area of the through hole of the Bragg reflective layer. The invention enhances the luminance of the blue light emitting diode chip by setting the structure of the first silver reflective layer plus the Bragg reflective layer plus the second silver reflective layer.
Description
技术领域technical field
本发明属于半导体器件的技术领域,具体地涉及一种倒装银镜发光二极管芯片及其制备方法。The invention belongs to the technical field of semiconductor devices, and in particular relates to a flip-chip silver mirror light-emitting diode chip and a preparation method thereof.
背景技术Background technique
近年来,发光二极管技术越来越成熟,应用逐渐多元化,照明、背光显示、直接显示等应用越来越多,照明或者背光显示,都需要将蓝光的发光二极管芯片进行荧光粉封装成白光应用。In recent years, light-emitting diode technology has become more and more mature, and its applications have gradually diversified. There are more and more applications such as lighting, backlight display, and direct display. For lighting or backlight display, it is necessary to package blue light-emitting diode chips with phosphor powder into white light applications. .
现有的倒装发光二极管芯片,采用金属Al加布拉格反射镜的方式,实现全反射,但是金属Al在可见光波段随着波长的增加,反射率逐渐降低,导致蓝光发光二极管芯片封装成白光后,发光效率降低,且布拉格反射层底部会制备一层SiO2或SiN材料用于化学湿法腐蚀,防止化学干法刻蚀时,等离子气体损伤布拉格反射层下面的电流扩展层,造成芯片失效,但是在布拉格反射层底部制备SiO2或SiN材料会造成布拉格反射层反射率低,导致蓝光发光二极管芯片亮度低。The existing flip-chip light-emitting diode chips use metal Al plus a Bragg reflector to achieve total reflection, but the reflectivity of metal Al decreases gradually with the increase of wavelength in the visible light band, resulting in blue light-emitting diode chips being packaged into white light. The luminous efficiency is reduced, and a layer of SiO 2 or SiN material will be prepared at the bottom of the Bragg reflective layer for chemical wet etching to prevent the plasma gas from damaging the current spreading layer below the Bragg reflective layer during chemical dry etching, resulting in chip failure, but Preparation of SiO 2 or SiN material at the bottom of the Bragg reflective layer will result in low reflectivity of the Bragg reflective layer, resulting in low brightness of the blue light emitting diode chip.
发明内容Contents of the invention
为了解决上述技术问题,本发明提供了一种倒装银镜发光二极管芯片及其制备方法。In order to solve the above technical problems, the present invention provides a flip-chip silver mirror light-emitting diode chip and a preparation method thereof.
本发明采用以下技术方案:一种倒装银镜发光二极管芯片,所述芯片包括:The present invention adopts the following technical solutions: a flip-chip silver mirror light-emitting diode chip, said chip comprising:
衬底;Substrate;
层叠于所述衬底上的外延层;an epitaxial layer stacked on the substrate;
依次层叠在所述外延层上的电流阻挡层、电流扩展层、第一银反射层、布拉格反射层、第二银反射层、金属保护层、第一绝缘保护层、串联金属层、第二绝缘保护层、焊盘层、锡球;A current blocking layer, a current spreading layer, a first silver reflective layer, a Bragg reflective layer, a second silver reflective layer, a metal protective layer, a first insulating protective layer, a series metal layer, a second insulating Protective layer, pad layer, solder ball;
其中,所述布拉格反射层设有布拉格反射层通孔,所述第一银反射层置于所述布拉格反射层通孔下面,所述第二银反射层至少部分穿过所述布拉格反射层通孔与所述第一银反射层抵触以形成电性连接,且所述第一银反射层在所述电流扩展层上的正投影面积大于所述布拉格反射层通孔的底面积。Wherein, the Bragg reflective layer is provided with a through hole of the Bragg reflective layer, the first silver reflective layer is placed under the through hole of the Bragg reflective layer, and the second silver reflective layer at least partially passes through the through hole of the Bragg reflective layer. The hole interferes with the first silver reflective layer to form an electrical connection, and the orthographic area of the first silver reflective layer on the current spreading layer is larger than the bottom area of the through hole of the Bragg reflective layer.
相比现有技术,本发明的有益效果为:通过设置第一银反射层加布拉格反射层加第二银反射层的结构,可以实现100%发光区面积的全反射,反射面积增加,相应的蓝光发光二极管发光亮度也随之增加;而且因为金属银反射率在可见光波段随波长增加而增加,在可见光波段金属Ag的反射率大于金属Al的反射率,所以采用金属银的发光二极管芯片封装成白光后,发光效率可大幅提升;并且第一银反射层的正向投影面积大于布拉格反射层通孔的面积,使得布拉格反射层底部不需要制备用于湿法腐蚀的SiO2层或SiN层,即可防止干法刻蚀布拉格反射层时对电流扩展层造成损伤,从而提升了布拉格反射层的反射率,增加了蓝光发光二极管芯片的发光亮度。Compared with the prior art, the beneficial effect of the present invention is: by setting the structure of the first silver reflective layer plus the Bragg reflective layer plus the second silver reflective layer, the total reflection of 100% light-emitting area area can be realized, the reflective area increases, and the corresponding The luminance of blue light-emitting diodes also increases; and because the reflectivity of metallic silver increases with the increase of wavelength in the visible light band, the reflectivity of metal Ag in the visible light band is greater than that of metal Al, so metal silver light-emitting diode chips are used. After white light, the luminous efficiency can be greatly improved; and the front projection area of the first silver reflective layer is larger than the area of the through hole of the Bragg reflective layer, so that the bottom of the Bragg reflective layer does not need to be prepared for wet etching. SiO2 layer or SiN layer, It can prevent the current spreading layer from being damaged when the Bragg reflection layer is etched by dry method, thereby improving the reflectivity of the Bragg reflection layer and increasing the luminance of the blue light emitting diode chip.
优选的,所述外延层自下而上依次包括N型半导体层、有源发光层、P型半导体层,所述第一绝缘保护层上设有N型第一绝缘保护层通孔和P型第一绝缘保护层通孔,所述串联金属层包括N型串联金属层和P型串联金属层,所述N型串联金属层透过所述N型第一绝缘保护层通孔与所述N型半导体层抵触以形成电性连接,所述P型串联金属层透过所述P型第一绝缘保护层通孔与所述金属保护层抵触以形成电性连接。Preferably, the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer from bottom to top, and the first insulating protection layer is provided with an N-type first insulating protection layer through hole and a P-type The through hole in the first insulating protection layer, the series metal layer includes an N-type series metal layer and a P-type series metal layer, and the N-type series metal layer passes through the N-type first insulating protection layer through hole and the N-type series metal layer. The P-type semiconductor layer interferes to form an electrical connection, and the P-type series metal layer interferes with the metal protection layer through the through hole of the P-type first insulating protection layer to form an electrical connection.
优选的,所述第二绝缘保护层上设有N型第二绝缘保护层通孔和P型第二绝缘保护层通孔,所述焊盘层包括N型焊盘层和P型焊盘层,所述N型焊盘层透过所述N型第二绝缘保护层通孔与所述N型串联金属层抵触以形成电性连接,所述P型焊盘层透过所述P型第二绝缘保护层通孔与所述P型串联金属层抵触以形成电性连接。Preferably, the second insulating protective layer is provided with an N-type second insulating protective layer via hole and a P-type second insulating protective layer via hole, and the pad layer includes an N-type pad layer and a P-type pad layer , the N-type pad layer is electrically connected to the N-type series metal layer through the through hole of the N-type second insulating protection layer, and the P-type pad layer is connected through the P-type first The through hole of the two insulating protection layers is in conflict with the P-type series metal layer to form an electrical connection.
优选的,所述电流阻挡层包括若干个间隔分布于所述P型半导体层上的电流阻挡子层,所述第一银反射层包括若干个间隔分布于所述电流扩展层上的第一银反射子层,所述第一银反射子层位于对应所述电流阻挡子层的正上方且其在所述外延层上的正投影面积小于所述电流阻挡子层在所述外延层上的正投影面积。Preferably, the current blocking layer includes several current blocking sublayers distributed on the P-type semiconductor layer at intervals, and the first silver reflective layer includes several first silver sublayers distributed at intervals on the current spreading layer. Reflective sublayer, the first silver reflective sublayer is located directly above the corresponding current blocking sublayer and its orthographic projection area on the epitaxial layer is smaller than the orthographic area of the current blocking sublayer on the epitaxial layer shadow area.
优选的,所述第一银反射层和所述第二银反射层均由Ag层或Ag层与Ni层、Ti层、Pt层中的一种或多种依次层叠组成。Preferably, both the first silver reflective layer and the second silver reflective layer are composed of an Ag layer or an Ag layer and one or more of a Ni layer, a Ti layer, and a Pt layer stacked in sequence.
优选的,所述第一银反射层和第二银反射层Ag层厚度介于1000-3000 Å,Ni层厚度介于100-2000 Å,Ti层厚度介于500-5000 Å,Pt层厚度介于100-3000 Å。Preferably, the thickness of the Ag layer of the first silver reflective layer and the second silver reflective layer is between 1000-3000 Å, the thickness of the Ni layer is between 100-2000 Å, the thickness of the Ti layer is between 500-5000 Å, and the thickness of the Pt layer is between at 100-3000 Å.
优选的,所述布拉格反射层厚度介于1-5um,所述布拉格反射层通孔直径介于1-20um。Preferably, the thickness of the Bragg reflection layer is between 1-5um, and the diameter of the hole of the Bragg reflection layer is between 1-20um.
优选的,所述电流阻挡层为SiO2层、SiN层、Al2O3层中的一种或多种层叠组成。Preferably, the current blocking layer is composed of one or more stacks of SiO 2 layer, SiN layer and Al 2 O 3 layer.
优选的,所述焊盘层为Al层、AlCu层、Ti层、Pt层、Ni层、Au层、Sn层、SnAg层、SnCu层中的一种或多种层叠组成。Preferably, the pad layer is composed of one or more stacks of Al layer, AlCu layer, Ti layer, Pt layer, Ni layer, Au layer, Sn layer, SnAg layer, and SnCu layer.
本发明还提供一种倒装银镜发光二极管芯片的制备方法,所述制备方法用于制备上述技术方案当中所述的倒装银镜发光二极管芯片,所述制备方法包括:The present invention also provides a method for preparing a flip-chip silver mirror light-emitting diode chip. The preparation method is used to prepare the flip-chip silver mirror light-emitting diode chip described in the above technical solution. The preparation method includes:
提供一衬底,在所述衬底上制作外延层,所述外延层自下而上依次包括N型半导体层、有源发光层、P型半导体层;A substrate is provided, and an epitaxial layer is formed on the substrate, and the epitaxial layer sequentially includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer from bottom to top;
对所述N型半导体层、有源发光层、P型半导体层进行刻蚀以暴露出N型半导体导电台阶;Etching the N-type semiconductor layer, active light-emitting layer, and P-type semiconductor layer to expose N-type semiconductor conductive steps;
在所述P型半导体层上制作电流阻挡层;forming a current blocking layer on the P-type semiconductor layer;
在所述电流阻挡层上制作电流扩展层;making a current spreading layer on the current blocking layer;
在所述电流扩展层上制作第一银反射层;making a first silver reflective layer on the current spreading layer;
在所述第一银反射层上制作布拉格反射层,对所述布拉格反射层进行刻蚀,形成布拉格反射层通孔;Fabricating a Bragg reflection layer on the first silver reflection layer, etching the Bragg reflection layer to form through holes in the Bragg reflection layer;
在所述布拉格反射层上制作第二银反射层;making a second silver reflective layer on the Bragg reflective layer;
在所述第二银反射层上制作金属保护层;Making a metal protection layer on the second silver reflective layer;
在所述金属保护层上制作第一绝缘保护层,并对所述第一绝缘保护层进行刻蚀形成N型第一绝缘保护层通孔和P型第一绝缘保护层通孔;forming a first insulating protective layer on the metal protective layer, and etching the first insulating protective layer to form an N-type first insulating protective layer via hole and a P-type first insulating protective layer via hole;
在所述第一绝缘保护层上制作串联金属层,所述串联金属层包括N型串联金属层和P型串联金属层;Fabricating a series metal layer on the first insulating protection layer, the series metal layer including an N-type series metal layer and a P-type series metal layer;
在所述串联金属层上制作第二绝缘保护层,并对所述第二绝缘保护层进行刻蚀形成N型第二绝缘保护层通孔和P型第二绝缘保护层通孔;forming a second insulating protective layer on the series metal layer, and etching the second insulating protective layer to form an N-type second insulating protective layer via hole and a P-type second insulating protective layer via hole;
在所述第二绝缘保护层上制作焊盘层,所述焊盘层包括N型焊盘层和P型焊盘层;Making a pad layer on the second insulating protection layer, the pad layer including an N-type pad layer and a P-type pad layer;
在所述焊盘层上制作锡球。Solder balls are formed on the pad layer.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the descriptions of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only of the present invention. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative efforts.
图1为本发明第一实施例的剖面结构示意图;Fig. 1 is the schematic cross-sectional structure diagram of the first embodiment of the present invention;
图2为本发明第一实施例的俯面结构示意图;Fig. 2 is a schematic view of the top structure of the first embodiment of the present invention;
图3为图2中局部A的放大示意图;Fig. 3 is an enlarged schematic diagram of part A in Fig. 2;
图4为图2中局部B的放大示意图;Fig. 4 is the enlarged schematic diagram of part B in Fig. 2;
图5为本发明第一实施例中倒装银镜发光二极管芯片的制备方法的流程图。FIG. 5 is a flow chart of a method for manufacturing a flip-chip silver mirror light-emitting diode chip in the first embodiment of the present invention.
附图标记说明:Explanation of reference signs:
11衬底、12外延层、121 N型半导体层、122有源发光层、123 P型半导体层、124 N型半导体导电台阶、13电流阻挡层、14电流扩展层、15第一银反射层、16布拉格反射层、161布拉格反射层通孔、17第二银反射层、18金属保护层、19第一绝缘保护层、191 N型第一绝缘保护层通孔、192 P型第一绝缘保护层通孔、20串联金属层、201 N型串联金属层、202 P型串联金属层、21第二绝缘保护层、211 N型第二绝缘保护层通孔、212 P型第二绝缘保护层通孔、22焊盘层、221 N型焊盘层、222 P型焊盘层、23锡球。11 substrate, 12 epitaxial layer, 121 N-type semiconductor layer, 122 active light-emitting layer, 123 P-type semiconductor layer, 124 N-type semiconductor conductive step, 13 current blocking layer, 14 current spreading layer, 15 first silver reflective layer, 16 Bragg reflection layer, 161 Bragg reflection layer through hole, 17 Second silver reflection layer, 18 Metal protection layer, 19 First insulation protection layer, 191 N-type first insulation protection layer through hole, 192 P-type first insulation protection layer Through hole, 20 series metal layer, 201 N type series metal layer, 202 P type series metal layer, 21 second insulating protective layer, 211 N type second insulating protective layer through hole, 212 P type second insulating protective layer through hole , 22 pad layers, 221 N-type pad layers, 222 P-type pad layers, 23 solder balls.
具体实施方式detailed description
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,旨在用于解释本发明的实施例,而不能理解为对本发明的限制。Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the embodiments of the present invention and should not be construed as limitations of the present invention.
在本发明实施例的描述中,需要理解的是,术语“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明实施例和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical ", "horizontal", "top", "bottom", "inner", "outer" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying Describes, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and operate in a specific orientation, and therefore should not be construed as limiting the invention.
此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明实施例的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present invention, "plurality" means two or more, unless otherwise specifically defined.
在本发明实施例中,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或成一体;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明实施例中的具体含义。In the embodiments of the present invention, terms such as "installation", "connection", "connection" and "fixation" should be interpreted in a broad sense unless otherwise clearly specified and limited. Disassembled connection, or integration; it can be mechanical connection or electrical connection; it can be direct connection or indirect connection through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the embodiments of the present invention according to specific situations.
实施例一Embodiment one
参照图1至图4,一种倒装银镜发光二极管芯片,芯片包括:衬底11;层叠于衬底11上的外延层12;依次层叠在外延层12上的电流阻挡层13、电流扩展层14、第一银反射层15、布拉格反射层16、第二银反射层17、金属保护层18、第一绝缘保护层19、串联金属层20、第二绝缘保护层21、焊盘层22、锡球23;1 to 4, a flip-chip silver mirror light-emitting diode chip, the chip includes: a
其中,布拉格反射层16设有布拉格反射层通孔161,第一银反射层15置于布拉格反射层通孔161下面,第二银反射层17的至少部分穿过布拉格反射层通孔161与第一银反射层15抵触以形成电性连接,且第一银反射层15在电流扩展层14上的正投影面积大于布拉格反射层通孔161的底面积。Wherein, the Bragg
在本实施例中,通过设置第一银反射层15加布拉格反射层16加第二银反射层17的结构,可以实现100%发光区面积的全反射,反射面积增加,相应的蓝光发光二极管发光亮度也随之增加;而且因为金属银反射率在可见光波段随波长增加而增加,在可见光波段金属Ag的反射率大于金属Al的反射率,所以采用金属银的发光二极管芯片封装成白光后,发光效率可大幅提升;并且第一银反射层15的正向投影面积大于布拉格反射层通孔161的面积,使得布拉格反射层16底部不需要制备用于湿法腐蚀的SiO2层或SiN层,即可防止干法刻蚀布拉格反射层16时对电流扩展层14造成损伤,从而提升了布拉格反射层16的反射率,增加了蓝光发光二极管芯片的发光亮度。In this embodiment, by setting the structure of the first silver
本实施例中,外延层自下而上依次包括N型半导体层、有源发光层、P型半导体层;第一绝缘保护层19上设有N型第一绝缘保护层通孔191和P型第一绝缘保护层通孔192,串联金属层20包括N型串联金属层201和P型串联金属层202, N型串联金属层201透过N型第一绝缘保护层通孔191与N型半导体层121抵触以形成电性连接,P型串联金属层202透过P型第一绝缘保护层通孔192与金属保护层18抵触以形成电性连接;第二绝缘保护层21上设有N型第二绝缘保护层通孔211和P型第二绝缘保护层通孔212,焊盘层22包括N型焊盘层221和P型焊盘层222,N型焊盘层221透过N型第二绝缘保护层通孔211与N型串联金属层201抵触以形成电性连接,P型焊盘层222透过P型第二绝缘保护层通孔212与P型串联金属层202抵触以形成电性连接。In this embodiment, the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer from bottom to top; the first insulating
本实施例中,电流阻挡层13包括9个间隔分布于P型半导体层123上的电流阻挡子层,第一银反射层15包括9个间隔分布于电流扩展层14上的第一银反射子层,第一银反射子层位于对应电流阻挡子层的正上方且其在外延层12上的正投影面积小于电流阻挡子层在外延层12上的正投影面积。In this embodiment, the
本实施例中,衬底11可以为蓝宝石衬底,第一银反射层15和第二银反射层17为由Ag层、Ni层、Ti层、Pt层依次层叠组成,第一银反射层15和第二银反射层17的最下层为Ag层,以此可以保证第一银反射层15及第二银反射层17的反射率。In this embodiment, the
本实施例中,第一银反射层15和第二银反射层17的 Ag层厚度为2000 Å,Ni层厚度为1050 Å,Ti层厚度为3000 Å,Pt层厚度为2550 Å;布拉格反射层16厚度为3um;布拉格反射层通孔161直径为10um。In this embodiment, the thickness of the Ag layer of the first silver
本实施例中,电流阻挡层13为SiN层组成;电流扩展层14为ITO层;金属保护层18为AlCu层组成;串联金属层20为Cr层组成;焊盘层22为Al层组成;第一绝缘保护层19和第二绝缘保护层21为SiN层组成;锡球23为Sn层。In this embodiment, the
参照图5,本发明提供了一种倒装银镜发光二极管芯片的制备方法,该制备方法用于制备上述实施例当中的倒装银镜发光二极管芯片,该制备方法包括以下步骤:Referring to FIG. 5, the present invention provides a method for preparing a flip-chip silver mirror light-emitting diode chip. The preparation method is used to prepare the flip-chip silver mirror light-emitting diode chip in the above embodiment. The preparation method includes the following steps:
S1:提供一衬底11,在衬底11上制作外延层12,外延层12自下而上依次包括N型半导体层121、有源发光层122、P型半导体层123;S1: A
S2:对P型半导体层123进行刻蚀以暴露出N型半导体导电台阶124;S2: Etching the P-
S3:在P型半导体层123上制作电流阻挡层13;S3: making the
S4:在电流阻挡层13上制作电流扩展层14;S4: making the current spreading
S5:在电流扩展层14上制作第一银反射层15;S5: make the first
S6:在第一银反射层15上制作布拉格反射层16,对布拉格反射层16进行刻蚀,形成布拉格反射层通孔161;S6: make the
S7:在布拉格反射层16上制作第二银反射层17;S7: making the second silver
S8:在第二银反射层17上制作金属保护层18;S8: make metal
S9:在金属保护层18上制作第一绝缘保护层19,并对第一绝缘保护层19进行刻蚀形成N型第一绝缘保护层通孔191和P型第一绝缘保护层通孔192;S9: making the first insulating
S10:在第一绝缘保护层19上制作串联金属层20,串联金属层20包括N型串联金属层201和P型串联金属层202;S10: Fabricate a
S11:在串联金属层20上制作第二绝缘保护层21,并对第二绝缘保护层21进行刻蚀形成N型第二绝缘保护层通孔211和P型第二绝缘保护层通孔212;S11: making a second insulating
S12:在第二绝缘保护层21上制作焊盘层22,焊盘层22包括N型焊盘层221和P型焊盘层222;S12: making
S13:在焊盘层22上制作锡球23。S13: making
具体的,本实施例当中所示的倒装银镜发光二极管芯片的制备方法的步骤,具体包括:Specifically, the steps of the method for preparing a flip-chip silver mirror light-emitting diode chip shown in this embodiment specifically include:
提供一衬底11,在衬底11上制备N型半导体层121、有源发光层122、P型半导体层123;Provide a
利用光刻及电感耦合等离子体刻蚀工艺制备N型半导体导电台阶124;Using photolithography and inductively coupled plasma etching processes to prepare N-type semiconductor
利用等立体化学气象沉积工艺上述步骤的基础上沉积SiN层,然后利用光刻和化学湿法腐蚀工艺去除掉部分SiN层形成电流阻挡层13;Depositing a SiN layer on the basis of the above steps using an isostereochemical vapor deposition process, and then removing part of the SiN layer by photolithography and chemical wet etching to form a
利用磁控溅射或电子束蒸镀工艺在上述步骤的基础上镀ITO薄膜,然后利用光刻和化学湿法腐蚀工艺去除掉部分ITO薄膜,形成电流扩展层14;Using a magnetron sputtering or electron beam evaporation process to coat an ITO film on the basis of the above steps, and then using a photolithography and chemical wet etching process to remove part of the ITO film to form a current spreading
利用光刻工艺在上述步骤的基础上形成图形,然后利用电子束蒸镀工艺蒸镀Ag层、Ni层、Ti层、Pt层金属层,然后利用Lift-Off工艺去除掉多余的金属层,形成第一银反射层15;Use the photolithography process to form patterns on the basis of the above steps, then use the electron beam evaporation process to evaporate the Ag layer, Ni layer, Ti layer, Pt layer metal layer, and then use the Lift-Off process to remove the excess metal layer to form The first silver
利用电子束蒸镀工艺蒸镀4-60层由SiO2和Ti3O5交替的叠层,形成布拉格反射层16,然后利用光刻和电感耦合等离子体刻蚀工艺制备布拉格反射层通孔161;Using an electron beam evaporation process to vapor-deposit 4-60 layers of alternating layers of SiO2 and Ti3O5 to form a
利用光刻工艺在上述步骤的基础上形成图形,然后利用电子束蒸镀工艺蒸镀Ag层、Ni层、Ti层、Pt层金属层,然后利用Lift-Off工艺去除掉多余的金属层,形成第二银反射层17;Use the photolithography process to form patterns on the basis of the above steps, then use the electron beam evaporation process to evaporate the Ag layer, Ni layer, Ti layer, Pt layer metal layer, and then use the Lift-Off process to remove the excess metal layer to form The second silver
利用光刻工艺在上述步骤的基础上形成图形,然后利用电子束蒸镀工艺蒸镀AlCu层,然后利用Lift-Off工艺去除掉多余的金属层,形成金属保护层18;Using a photolithography process to form a pattern on the basis of the above steps, then using an electron beam evaporation process to evaporate an AlCu layer, and then using a Lift-Off process to remove the excess metal layer to form a
利用等立体化学气象沉积工艺在上述步骤的基础上沉积SiN层,形成第一绝缘保护层19,然后利用光刻和化学干法刻蚀工艺去除掉部分SiN层,形成N型第一绝缘保护层通孔191和P型第一绝缘保护层通孔192;Deposit a SiN layer on the basis of the above steps by using an isostereochemical vapor deposition process to form a first insulating
利用光刻工艺在上述步骤的基础上形成图形,然后利用电子束蒸镀工艺蒸镀Cr层,然后利用Lift-Off工艺去除掉多余的金属层,形成串联金属层20,包括N型串联金属层201,P型串联金属层202;Utilize the photolithography process to form patterns on the basis of the above steps, then use the electron beam evaporation process to evaporate the Cr layer, and then use the Lift-Off process to remove the redundant metal layer to form the
利用等立体化学气象沉积工艺在上述步骤的基础上沉积SiN层,形成第二绝缘保护层21,然后利用光刻和化学干法刻蚀工艺去除掉部分SiN层,形成N型第二绝缘保护层通孔211和P型第二绝缘保护层通孔212;Deposit a SiN layer on the basis of the above steps by using an isostereochemical vapor deposition process to form a second insulating
利用光刻工艺在上述步骤的基础上形成图形,然后利用电子束蒸镀工蒸镀Al层,然后利用Lift-Off工艺去除掉多余的金属层,形成焊盘层22,包括N型焊盘层221和P型焊盘层222;Use a photolithography process to form a pattern on the basis of the above steps, then use an electron beam evaporation worker to evaporate an Al layer, and then use a Lift-Off process to remove the excess metal layer to form a
利用丝网印刷工艺,印刷Sn金属,然后高温回流制备锡球23。Sn metal is printed by screen printing process, and then reflowed at high temperature to prepare
本实施例制备方法制备的倒装银镜发光二极管芯片与对照例制备的芯片尺寸规格相同,经测试仪器测试光效为236lm/W,较对照例提升了1.29%,具体结果如表1所示。The flip-chip silver mirror light-emitting diode chip prepared by the preparation method of this example has the same size specification as the chip prepared by the comparative example, and the light efficiency tested by the testing instrument is 236lm/W, which is 1.29% higher than that of the comparative example. The specific results are shown in Table 1. .
实施例二Embodiment two
本实施例与实施例1的不同之处在于:本实施例的布拉格反射层厚度为1μm,布拉格反射层通孔直径为20μm。The difference between this embodiment and
本实施例制备方法制备的倒装银镜发光二极管芯片与对照例制备的芯片尺寸规格相同,经测试仪器测试光效为234lm/W,较对照例提升了0.43%,具体结果如表1所示。The flip-chip silver mirror light-emitting diode chip prepared by the preparation method of this example has the same size and specification as the chip prepared by the comparative example, and the light efficiency tested by the testing instrument is 234lm/W, which is 0.43% higher than that of the comparative example. The specific results are shown in Table 1. .
实施例三Embodiment three
本实施例与实施例1的不同之处在于:本实施例的布拉格反射层厚度为4μm,布拉格反射层通孔直径为15μm。The difference between this embodiment and
本实施例制备方法制备的倒装银镜发光二极管芯片与对照例制备的芯片尺寸规格相同,经测试仪器测试光效为236.5lm/W,较对照例提升了1.5%,具体结果如表1所示。The flip-chip silver mirror light-emitting diode chip prepared by the preparation method of this example has the same size specification as the chip prepared by the comparative example, and the light efficiency tested by the testing instrument is 236.5lm/W, which is 1.5% higher than that of the comparative example. The specific results are shown in Table 1. Show.
实施例四Embodiment four
本实施例与实施例1的不同之处在于,本实施例的布拉格反射层厚度为5μm,布拉格反射层通孔直径为5μm。The difference between this embodiment and
本实施例制备方法制备的倒装银镜发光二极管芯片与对照例制备的芯片尺寸规格相同,经测试仪器测试光效为238lm/W,较对照例提升了2.15%,具体结果如表1所示。The flip-chip silver mirror light-emitting diode chip prepared by the preparation method of this example has the same size and specification as the chip prepared by the comparative example, and the light efficiency tested by the testing instrument is 238lm/W, which is 2.15% higher than that of the comparative example. The specific results are shown in Table 1. .
对照例Comparative example
本对照例采用现有技术制备的倒装发光二极管芯片,其包括衬底及设在衬底上的外延层,依次在外延层上沉积的电流阻挡层、电流扩展层、防护层、布拉格反射层、金属反射层、金属保护层、串联金属层、绝缘保护层、焊盘层、锡球。其中,防护层为SiO2层或SiN层,金属反射层为Al层。通过测试仪器测试本芯片的光效为233lm/W。This comparative example adopts the flip-chip light-emitting diode chip prepared by the prior art, which includes a substrate and an epitaxial layer arranged on the substrate, and a current blocking layer, a current spreading layer, a protective layer, and a Bragg reflective layer deposited on the epitaxial layer in sequence. , metal reflective layer, metal protective layer, series metal layer, insulating protective layer, pad layer, solder ball. Wherein, the protective layer is a SiO2 layer or a SiN layer, and the metal reflective layer is an Al layer. The luminous efficiency of this chip is 233lm/W tested by the testing instrument.
表1:各实施例及对照例的部分参数比对以及对应光效结果的对比表Table 1: Comparison of some parameters of each embodiment and comparative example and a comparison table of the corresponding light effect results
从表1可知,本发明通过设置第一银反射层15加布拉格反射层16加第二银反射层17的结构来替代对照例的SiN防护层加布拉格反射层加金属Al反射层,再由各实施例调整布拉格反射层16厚度及布拉格反射层通孔161的直径,使得本发明各实施例的光效均优于对照例。As can be seen from Table 1, the present invention replaces the SiN protective layer of the comparative example plus the Bragg reflective layer plus the metal Al reflective layer by setting the first silver
综上,通过上述实施制作的倒装银镜发光二极管芯片,通过设置第一银反射层15加布拉格反射层16加第二银反射层17的结构,可以实现100%发光区面积的全反射,反射面积增加,相应的蓝光发光二极管发光亮度也随之增加;而且因为金属银反射率在可见光波段随波长增加而增加,在可见光波段金属Ag的反射率大于金属Al的反射率,所以采用金属银的发光二极管芯片封装成白光后,发光效率可大幅提升;并且第一银反射层15的正向投影面积大于布拉格反射层通孔161的面积,使得布拉格反射层16底部不需要制备用于湿法腐蚀的SiO2层SiN层,即可防止干法刻蚀布拉格反射层16时对电流扩展层14造成损伤,从而提升了布拉格反射层16的反射率,增加了蓝光发光二极管芯片的发光亮度。To sum up, the flip-chip silver mirror light-emitting diode chip produced by the above implementation can achieve total reflection of 100% of the light-emitting area by setting the structure of the first silver
在不出现冲突的前提下,本领域技术人员可以将上述附加技术特征自由组合以及叠加使用。On the premise of no conflict, those skilled in the art can freely combine and superimpose the above additional technical features.
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115863514A (en) * | 2023-03-03 | 2023-03-28 | 江西兆驰半导体有限公司 | Vertical LED chip and preparation method thereof |
CN116581225A (en) * | 2023-07-13 | 2023-08-11 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
CN116613259A (en) * | 2023-07-20 | 2023-08-18 | 江西兆驰半导体有限公司 | Flip LED chip and preparation method |
CN116646435A (en) * | 2023-07-26 | 2023-08-25 | 江西兆驰半导体有限公司 | A flip-chip light-emitting diode chip and its preparation method |
CN117393680A (en) * | 2023-12-12 | 2024-01-12 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160329461A1 (en) * | 2015-02-17 | 2016-11-10 | Genesis Photonics Inc. | Light emitting diode |
US20170025571A1 (en) * | 2015-05-22 | 2017-01-26 | Seoul Viosys Co., Ltd. | Light emitting diode with high efficiency |
US20170047484A1 (en) * | 2015-08-13 | 2017-02-16 | Lextar Electronics Corporation | Semiconductor light emitting structure |
CN109713103A (en) * | 2018-12-28 | 2019-05-03 | 映瑞光电科技(上海)有限公司 | A kind of LED chip |
US20200127167A1 (en) * | 2018-10-23 | 2020-04-23 | Seoul Viosys Co., Ltd. | Flip chip type light emitting diode chip |
US20210359188A1 (en) * | 2019-01-31 | 2021-11-18 | Seoul Viosys Co., Ltd. | Light emitting diode |
CN114709307A (en) * | 2022-03-16 | 2022-07-05 | 江西兆驰半导体有限公司 | A flip-chip light-emitting diode chip and preparation method thereof |
CN114709304A (en) * | 2022-03-04 | 2022-07-05 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
CN114709311A (en) * | 2022-03-21 | 2022-07-05 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
-
2022
- 2022-12-09 CN CN202211576008.3A patent/CN115579438A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160329461A1 (en) * | 2015-02-17 | 2016-11-10 | Genesis Photonics Inc. | Light emitting diode |
US20170025571A1 (en) * | 2015-05-22 | 2017-01-26 | Seoul Viosys Co., Ltd. | Light emitting diode with high efficiency |
US20170047484A1 (en) * | 2015-08-13 | 2017-02-16 | Lextar Electronics Corporation | Semiconductor light emitting structure |
US20200127167A1 (en) * | 2018-10-23 | 2020-04-23 | Seoul Viosys Co., Ltd. | Flip chip type light emitting diode chip |
CN109713103A (en) * | 2018-12-28 | 2019-05-03 | 映瑞光电科技(上海)有限公司 | A kind of LED chip |
US20210359188A1 (en) * | 2019-01-31 | 2021-11-18 | Seoul Viosys Co., Ltd. | Light emitting diode |
CN114709304A (en) * | 2022-03-04 | 2022-07-05 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
CN114709307A (en) * | 2022-03-16 | 2022-07-05 | 江西兆驰半导体有限公司 | A flip-chip light-emitting diode chip and preparation method thereof |
CN114709311A (en) * | 2022-03-21 | 2022-07-05 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115863514A (en) * | 2023-03-03 | 2023-03-28 | 江西兆驰半导体有限公司 | Vertical LED chip and preparation method thereof |
CN116581225A (en) * | 2023-07-13 | 2023-08-11 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
CN116581225B (en) * | 2023-07-13 | 2023-10-17 | 江西兆驰半导体有限公司 | Flip-chip light-emitting diode chip and preparation method thereof |
CN116613259A (en) * | 2023-07-20 | 2023-08-18 | 江西兆驰半导体有限公司 | Flip LED chip and preparation method |
CN116646435A (en) * | 2023-07-26 | 2023-08-25 | 江西兆驰半导体有限公司 | A flip-chip light-emitting diode chip and its preparation method |
CN116646435B (en) * | 2023-07-26 | 2023-09-19 | 江西兆驰半导体有限公司 | Flip-chip light-emitting diode chip and preparation method thereof |
CN117393680A (en) * | 2023-12-12 | 2024-01-12 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip and preparation method thereof |
CN117393680B (en) * | 2023-12-12 | 2024-04-12 | 江西兆驰半导体有限公司 | A flip-chip light-emitting diode chip and its preparation method |
CN117712245A (en) * | 2024-02-05 | 2024-03-15 | 江西兆驰半导体有限公司 | A flip-chip LED chip and its preparation method |
CN118763162A (en) * | 2024-09-06 | 2024-10-11 | 江西兆驰半导体有限公司 | A flip-chip LED chip and its preparation method |
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