CN116646435B - Flip-chip light-emitting diode chip and preparation method thereof - Google Patents

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a flip-chip light-emitting diode chip and a preparation method thereof, wherein the flip-chip light-emitting diode chip comprises a substrate, an epitaxial layer, a current blocking layer, a current expansion layer, an electrode layer, a Bragg reflection layer, a connection layer, a first insulating protection layer, a metal protection layer, a second insulating protection layer and a bonding pad layer which are sequentially laminated on the substrate; the connecting layer comprises a plurality of P-type connecting layers and a plurality of N-type connecting layers which are identical in structure, wherein the P-type connecting layers are formed by sequentially stacking a high-reflection metal layer, a protective metal layer and a current transmission layer, and the high-reflection metal layer is an Al layer or an Ag layer; the current transmission layer comprises at least two transmission sublayers which are sequentially laminated, the transmission sublayers are composed of a plurality of groups of periodically laminated TiW layers and Au layers, and the ratio of the thickness of the TiW layers to the thickness of the Au layers in different transmission sublayers along the growth direction of the chip is linearly increased. The LED chip of the invention has uniformly diffused current and can increase the maximum current which can be used by the LED chip.

Description

Flip-chip light-emitting diode chip and preparation method thereof

Technical field

The present invention relates to the technical field of semiconductor devices, and in particular to a flip-chip light-emitting diode chip and a preparation method thereof.

Background technique

Flip-chip LED chips are widely used for their advantages of emitting light from the back, strong heat dissipation, good weldability, large thrust, and strong reliability. At first, people used the Bragg reflective layer as a reflector to enable flip-chip LEDs to emit light from the back. Recently, In recent years, people have begun to add high-reflectivity metals to the Bragg reflective layer to cooperate with the Bragg reflective layer to form a total reflection mirror, thereby improving the reflectivity of the Bragg reflective layer and ultimately improving the external quantum efficiency of the flip-chip light-emitting diode chip.

The metal placed on the Bragg reflective layer not only cooperates with the Bragg reflective layer to form a total reflection mirror, but also needs to transmit current to several electrodes under the Bragg reflective layer so that the current can spread to the entire LED chip. However, existing LED chips , when current is injected into the metal above the Bragg reflective layer, most of the current will flow vertically through the reflective metal into the electrode layer below the current injection port, instead of being transmitted laterally to the electrode layer of the entire LED chip. This will cause uneven current diffusion, resulting in a high operating voltage of the LED chip. When the LED chip is used under high current, the heat is mainly concentrated in the LED chip area below the current injection port, putting the LED chip at risk of burning; causing the LED chip to fail. Used under high current for a long time.

Contents of the invention

In order to solve the above technical problems, the present invention provides a flip-chip light-emitting diode chip and a preparation method thereof.

The present invention adopts the following technical solution: a flip-chip light-emitting diode chip, including a substrate and an epitaxial layer, a current blocking layer, a current spreading layer, an electrode layer, a Bragg reflective layer, a connection layer and a third layer that are sequentially stacked on the substrate. an insulating protective layer, a metal protective layer, a second insulating protective layer, and a pad layer;

The connection layer includes a plurality of P-type connection layers and a plurality of N-type connection layers with the same structure. The P-type connection layer includes a highly reflective metal layer, a protective metal layer and a current transmission layer stacked in sequence. The highly reflective metal layer The layer is an Al layer or an Ag layer, and the protective metal layer is composed of one or more stacks of a Ti layer, a Pt layer, a Ni layer, a Cr layer, and a Pb layer;

The current transmission layer includes at least two transmission sub-layers stacked in sequence. The transmission sub-layer is composed of 3-5 groups of periodically stacked TiW layers and Au layers. The thickness of the TiW layer in the different transmission sub-layers accounts for the Au layer. The thickness ratio is between 10% and 40%, and the ratio of the TiW layer thickness to the Au layer thickness in the transmission sublayer increases linearly along the chip growth direction;

The distance from the edge of the P-type connection layer to the edge of the N-type connection layer is between 20 μm and 40 μm.

In the flip-chip light-emitting diode chip according to an embodiment of the present invention, the highly reflective metal layer can cooperate with the Bragg reflective layer to form total reflection to ensure reflectivity. The protective metal layer can protect the highly reflective metal layer from migration and oxidation; the current transmission layer There are multiple transmission sublayers composed of periodically stacked TiW layers and Au layers, and the ratio of the thickness of the TiW layer to the thickness of the Au layer in different transmission sublayers along the chip growth direction increases linearly, so that when current is injected into the connection layer Transmit laterally first, then vertically, so that the LED chip current spreads evenly, and can increase the maximum current that the LED chip can use; and if the distance from the edge of the P-type connection layer to the edge of the N-type connection layer is less than 20μm, when the LED chip is powered on Under such circumstances, electromigration can easily occur between the edge of the P-type connection layer and the edge of the N-type connection layer, causing a short circuit in the LED chip. If the distance is too large, the overall area of the P-type connection layer and the N-type connection layer will be smaller, affecting the connection layer and The total reflection effect formed by the Bragg reflective layer, so the moderate distance from the edge of the P-type connection layer to the edge of the N-type connection layer can ensure that the LED chip works stably and has a good luminous effect.

Further, the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. Isolation grooves are provided around the N-type semiconductor layer, and the Bragg reflective layer, Both the first insulating protective layer and the second insulating protective layer extend to cover the isolation trench.

Further, the current blocking layer is a plurality of SiO ₂ disks or Al ₂ O ₃ disks with a diameter ranging from 20 μm to 50 μm, and they are all placed on the P-type semiconductor layer.

Further, the current spreading layer covers and extends the current blocking layer to the P-type semiconductor layer, and the distance from the edge of the current spreading layer to the edge of the P-type semiconductor layer is between 3 μm and 10 μm.

Further, the electrode layer includes a plurality of P-type electrode layers and a plurality of N-type electrode layers, and the P-type electrode layer and the N-type electrode layer are metal disks with a diameter between 10 μm and 30 μm, and the The P-type electrode layer is located on the current spreading layer and is concentric with the current blocking layer; the distance from the edge of the P-type electrode layer to the edge of the current blocking layer is between 5 μm and 15 μm; the N-type electrode layer It is located on the N-type semiconductor layer and forms an electrical connection with the N-type semiconductor layer. The distance from the edge of the N-type electrode layer to the edge of the P-type semiconductor layer is between 7 μm and 10 μm.

Further, the Bragg reflective layer is composed of 20-40 groups of periodically stacked TiO ₂ layers and SiO ₂ layers. The Bragg reflective layer is provided with a plurality of first through holes, and the connection layer penetrates the first through holes. The through hole is connected to the electrode layer, and the distance from the edge of the first through hole to the edge of the electrode layer is between 2 μm and 10 μm.

Further, the first insulating protective layer and the second insulating protective layer are both SiO ₂ layers, Al ₂ O ₃ layers or SiN layers, and both the first insulating protective layer and the second insulating protective layer are A second through hole is provided to penetrate it. The pad layer is electrically connected to the connection layer through the second through hole. The distance from the edge of the second through hole to the edge of the connection layer is between 10 μm. -15μm.

Further, the pad layer is placed on the second insulating protective layer, which includes a P-type pad layer and an N-type pad layer, and the edge of the P-type pad layer to the N-type pad layer The edge distance is between 200μm-300μm.

Further, the metal protective layer includes a P-type metal protective layer, an N-type metal protective layer and an anti-ejector layer, and the P-type metal protective layer is placed on the N-type connection layer on one side of the P-type pad layer. between the first insulating protective layer and the second insulating protective layer, and the width of the projection of the P-type metal protective layer on the substrate is greater than the width of the N-type connection layer on the substrate. The width of the projection on the substrate, the distance from the projected edge of the P-type metal protective layer on the substrate to the projected edge of the N-type connection layer on the substrate is between 5 μm and 15 μm;

The N-type metal protective layer is placed between the first insulating protective layer and the second insulating protective layer on the P-type connection layer on one side of the N-type pad layer, and the N-type metal protective layer The width of the projection of the N-type metal protective layer on the substrate is greater than the width of the projection of the P-type connection layer on the substrate, and the projection edge of the N-type metal protective layer on the substrate reaches the The projected edge distance of the P-type connection layer on the substrate is between 5 μm and 15 μm;

The anti-ejector layer is placed between the first insulating protective layer and the second insulating protective layer in the center of the flip-chip LED chip, and the anti-ejector layer is a disc with a diameter between 50 μm and 100 μm.

Correspondingly, the present invention also provides a method for preparing a flip-chip light-emitting diode chip, which is used to prepare the flip-chip light-emitting diode chip as described above. The method includes:

provide a substrate;

Deposit an epitaxial layer on the substrate, the epitaxial layer including an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer;

Prepare isolation trenches on the N-type semiconductor layer;

Deposit a current blocking layer on the P-type semiconductor layer, the current blocking layer extends to the N-type semiconductor layer and covers the isolation trench;

depositing a current spreading layer on the current blocking layer;

Deposit an electrode layer on the current spreading layer and the N-type semiconductor layer, the electrode layer including a P-type electrode layer located on the current spreading layer and an N-type electrode layer located on the N-type semiconductor layer;

depositing a Bragg reflective layer on the electrode layer;

Deposit a connection layer on the Bragg reflective layer, the connection layer including a P-type connection layer electrically connected to the P-type electrode layer and an N-type connection layer electrically connected to the N-type electrode layer;

depositing a first insulating protective layer on the connection layer;

depositing a metal protective layer on the first insulating protective layer;

depositing a second insulating protective layer on the metal protective layer;

A pad layer is deposited on the second insulating protective layer. The pad layer includes a P-type pad electrically connected to the P-type connection layer and an N-type pad electrically connected to the N-type connection layer. plate.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings in the following description are only illustrative of the present invention. For some embodiments, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic top view of the flip-chip light-emitting diode chip according to the first embodiment of the present invention;

Figure 2 is a schematic cross-sectional view of the flip-chip light-emitting diode chip along line AA in Figure 1 according to the first embodiment of the present invention;

Figure 3 is a schematic cross-sectional view of the flip-chip light-emitting diode chip along line BB in Figure 1 according to the first embodiment of the present invention;

FIG. 4 is a flow chart of a method for manufacturing a flip-chip light-emitting diode chip according to the second embodiment of the present invention.

Explanation of reference symbols:

10. Substrate; 11. Epitaxial layer; 111. N-type semiconductor layer; 112. Active light-emitting layer; 113. P-type semiconductor layer; 114. Isolation trench; 12. Current blocking layer; 13. Current expansion layer; 14. Electrode layer; 141. P-type electrode layer; 142. N-type electrode layer; 15. Bragg reflective layer; 151. First through hole; 152. P-type Bragg via hole; 153. N-type Bragg via hole; 16. Connection layer ; 161. P-type connection layer; 162. N-type connection layer; 163. High-reflective metal layer; 164. Protective metal layer; 165. Current transmission layer; 166. Transmission sub-layer; 1661. First sub-layer; 1662. Chapter Two sub-layers; 17. First insulating protective layer; 18. Metal protective layer; 181. P-type metal protective layer; 182. N-type metal protective layer; 183. Anti-ejector layer; 19. Second insulating protective layer; 191. Second through hole; 192, P-type insulating protective layer through hole, 193, N-type insulating protective layer through hole; 20, pad layer; 201, P-type pad layer; 202, N-type pad layer.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the drawings are exemplary and are intended to explain the embodiments of the present invention and are not to be construed as limitations of the present invention.

In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical" ", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience and simplicity in describing the embodiments of the present invention. The description does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore is not to be construed as a limitation of the invention.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

In the embodiments of the present invention, unless otherwise expressly stipulated and limited, the terms "installation", "connection", "connection", "fixing" and other terms should be understood in a broad sense. For example, it can be a fixed connection or a removable connection. Disassembly and connection, or integration; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

Example 1

Referring to Figures 1 to 3, a first embodiment of the present invention, a flip-chip light-emitting diode chip, includes a substrate 10 and an epitaxial layer 11, a current blocking layer 12, a current spreading layer 13, and electrodes sequentially stacked on the substrate 10 Layer 14, Bragg reflective layer 15, connection layer 16, first insulating protective layer 17, metal protective layer 18, second insulating protective layer 19, pad layer 20;

The connection layer 16 includes a plurality of P-type connection layers 161 and a plurality of N-type connection layers 162 with the same structure. The P-type connection layer 161 is composed of a highly reflective metal layer 163, a protective metal layer 164 and a current transmission layer 165 stacked in sequence. The reflective metal layer 163 is an Al layer or an Ag layer, and the protective metal layer 164 is a stack of one or more of a Ti layer, a Pt layer, a Ni layer, a Cr layer, and a Pb layer;

The current transmission layer 165 includes at least two transmission sub-layers 166 stacked in sequence. The transmission sub-layer 166 is composed of 3-5 groups of periodically stacked TiW layers and Au layers. The thickness of the TiW layer in different transmission sub-layers 166 accounts for 50% of the thickness of the Au layer. The ratio is between 10% and 40%, and the ratio of the thickness of the TiW layer to the thickness of the Au layer in different transmission sublayers 166 along the chip growth direction increases linearly;

The distance e from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is between 20 μm and 40 μm.

In this embodiment, the highly reflective metal layer 163 is an Ag layer, and the protective metal layer 164 is a Ti layer; the current transmission layer 165 includes two transmission sub-layers 166 stacked in sequence, divided into a first sub-layer 1661 and a second sub-layer 1662 , both transmission sublayers 166 are composed of three groups of periodically stacked TiW layers and Au layers. The thickness of each TiW layer in the first sublayer 1661 is 10% of the thickness of each Au layer, and each layer in the second sublayer 1662 is The thickness of the TiW layer is 20% of the thickness of each Au layer; during specific implementation, the current transmission layer 165 may include four transmission sub-layers 166 stacked in sequence, wherein the thickness of each TiW layer in the third transmission sub-layer 166 is 30% of the thickness of each Au layer, and the thickness of each TiW layer in the fourth transmission sublayer 166 is 40% of the thickness of each Au layer, not limited to this; the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 The distance e is 30 μm.

In the flip-chip LED chip according to an embodiment of the present invention, the highly reflective metal layer 163 can cooperate with the Bragg reflective layer 15 to form total reflection to ensure reflectivity. The protective metal layer 164 can protect the highly reflective metal layer 163 from migration and oxidation. ; The current transmission layer 165 has a plurality of transmission sub-layers 166 composed of periodically stacked TiW layers and Au layers, and the ratio of the thickness of the TiW layer to the thickness of the Au layer in different transmission sub-layers 166 along the chip growth direction increases linearly, When the current is injected into the connection layer 16, it is first transmitted horizontally and then vertically, so that the LED chip current spreads evenly, and the maximum current that can be used by the LED chip can be increased; and if the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 The distance is less than 20 μm. When the LED chip is powered on, electromigration easily occurs between the edge of the P-type connection layer 161 and the edge of the N-type connection layer 162, causing the LED chip to short circuit. If the distance is too large, the P-type connection layer 161 and the The overall area of the N-type connection layer 162 is small, which affects the total reflection effect formed by the connection layer 16 and the Bragg reflection layer 15. Therefore, a moderate distance from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 can ensure that the LED chip operates stably and has Good luminous effect.

The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 that are sequentially stacked on the substrate 10. The N-type semiconductor layer 111 is surrounded by an isolation trench 114, a Bragg reflective layer 15, and a first insulating layer. The protective layer 17 and the second insulating protective layer 19 both extend and cover the isolation trench 114, which can effectively prevent external water vapor from oxidizing the epitaxial layer 11.

The current blocking layer 12 is a plurality of SiO ₂ disks or Al ₂ O ₃ disks with a diameter between 20 μm and 50 μm, and they are all placed on the P-type semiconductor layer 113; if the diameter of the current blocking layer 12 is less than 20 μm, the LED The anti-ESD ability of the chip becomes worse. The larger the diameter, the better the ESD ability. However, if it is larger than 50 μm, it will cause the operating voltage of the LED chip to rise sharply. In this embodiment, the current blocking layer 12 is a plurality of SiO ₂ disks with a diameter of 35 μm. Quantity depends on chip size.

The current spreading layer 13 covers and extends the current blocking layer 12 to the P-type semiconductor layer 113, and the distance a from the edge of the current spreading layer 13 to the edge of the P-type semiconductor layer 113 is between 3 μm and 10 μm; the distance a from the edge of the current spreading layer 13 to the P-type semiconductor layer 113 is If the edge distance of the semiconductor layer 113 is less than 3 μm, it will easily cause the current expansion layer 13 to contact the side walls of the P-type semiconductor layer 113, causing the LED chip to conduct under reverse current, causing the LED chip to fail. If the distance is too large, a current will occur. If the area of the expansion layer 13 is too small, it is difficult to expand the current, resulting in a high operating voltage of the LED chip. In this embodiment, the distance a from the edge of the current expansion layer 13 to the edge of the P-type semiconductor layer 113 is 6 μm, and the area of the current expansion layer 13 is P 50%-98% of the area of the P-type semiconductor layer 113. In specific implementation, the area of the current spreading layer 13 is 70% of the area of the P-type semiconductor layer 113.

The electrode layer 14 includes a plurality of P-type electrode layers 141 and a plurality of N-type electrode layers 142. The P-type electrode layers 141 and the N-type electrode layers 142 are both metal disks with a diameter between 10 μm and 30 μm. The P-type electrode layer 141 is located on on the current spreading layer 13 and concentric with the current blocking layer 12; the distance b from the edge of the P-type electrode layer 141 to the edge of the current blocking layer 12 is between 5 μm and 15 μm; the N-type electrode layer 142 is located on the N-type semiconductor layer 111, and It is electrically connected to the N-type semiconductor layer 111, and the distance c from the edge of the N-type electrode layer 142 to the edge of the P-type semiconductor layer 113 is between 7 μm and 10 μm; the diameters of the P-type electrode layer 141 and the N-type electrode layer 142 are too small. It causes the working voltage of the LED chip to increase. If it is too large, it will cause the brightness to decrease. It is between 10μm-30μm, which can balance the working voltage and brightness; the distance from the edge of the P-type electrode layer 141 to the edge of the current blocking layer 12 is set to enhance the resistance of the LED chip to electrostatic shock. Penetration ability, the larger the distance, the better the effect, but the distance greater than 15 μm will cause the operating voltage of the LED chip to rise sharply; the distance from the edge of the N-type electrode layer 142 to the edge of the P-type semiconductor layer 113 is set to prevent the LED chip from The metal of the N-type electrode migrates to the P-type semiconductor, causing short-circuit failure of the LED chip. In this embodiment, the number of P-type electrode layers 141 is the same as the number of current blocking layers 12, and the area of P-type electrode layer 141 is smaller than the area of current blocking layer 12. , the metal disk of the electrode layer 14 can be formed from one or more combinations of Cr layer, Ni layer, Al layer, AlCu layer, Ti layer, Pt layer, Au layer, Ag layer, and Cu layer. In specific embodiments, , the metal disk of the electrode layer 14 is a Cr layer; the P-type electrode layer 141 is a metal disk with a diameter of 20 μm, and the N-type electrode layer 142 is a metal disk with a diameter of 25 μm. The edge of the P-type electrode layer 141 is from the edge of the current blocking layer 12 The distance b is 10 μm, and the distance c from the edge of the N-type electrode layer 142 to the edge of the P-type semiconductor layer 113 is 9 μm.

The Bragg reflective layer 15 is composed of 20-40 groups of periodically stacked TiO ₂ layers and SiO ₂ layers. The Bragg reflective layer 15 is provided with a plurality of first through holes 151 , and the connection layer 16 passes through the first through holes 151 and the electrode layer 14 For connection, the distance d between the edge of the first through hole 151 and the edge of the electrode layer 14 is between 2 μm and 10 μm; the diameter of the first through hole 151 should be smaller than the diameter of the electrode layer 14 to avoid that the connection layer 16 cannot completely cover the electrode layer in the first through hole 151 14. Effectively improve the chip reliability of the LED chip; in this embodiment, the Bragg reflective layer 15 is composed of 28 groups of periodically stacked TiO ₂ layers and SiO ₂ layers, and the first through hole 151 is projected into a circle of 4 μm-20 μm. And projected as a concentric circle with the electrode layer 14, the first through hole 151 placed on the P-type electrode layer 141 is a P-type Bragg via 152, and the first through hole 151 placed on the N-type electrode layer 142 is an N-type Bragg via 153. , during specific implementation, the first through hole 151 is projected into a circle of 15 μm; the distance d from the edge of the first through hole 151 to the edge of the electrode layer 14 is 5 μm.

The first insulating protective layer 17 and the second insulating protective layer 19 are both SiO ₂ layers, Al ₂ O ₃ layers or SiN layers. The first insulating protective layer 17 and the second insulating protective layer 19 are both provided with a third insulating protective layer penetrating them. Two through holes 191, the pad layer 20 is electrically connected to the connection layer 16 through the second through hole 191, the distance f from the edge of the second through hole 191 to the edge of the connection layer 16 is between 10 μm and 15 μm; the pad layer 20 is placed on the third through hole 191. On the second insulating protective layer 19, it includes a P-type pad layer 201 and an N-type pad layer 202. The distance h from the edge of the P-type pad layer 201 to the edge of the N-type pad layer 202 is between 200 μm and 300 μm.

The setting of the distance from the edge of the second through hole 191 to the edge of the connection layer 16 can prevent the pad layer 20 from forming a void at the edge of the connection layer 16 when the pad layer 20 is connected to the edge of the connection layer 16 through the second through hole 191 , eventually causing the LED chip Reliability is reduced; the second through hole 191 placed on the P-type connection layer 161 is a P-type insulating protective layer through hole 192, and the second through hole 191 placed on the N-type connecting layer 162 is an N-type insulating protective layer. Through hole 193; the distance from the edge of the P-type pad layer 201 to the edge of the N-type pad layer 202 is to avoid the pads placed on the P-type pad layer 201 and the pads placed on the N-type pad layer 202 during the subsequent packaging process. The pads are connected together during the reflow process, causing short circuit failure of the LED chip. This distance must be greater than 200 μm. The larger the better the effect, but if it is too large, it will cause the P-type pad layer 201 and the N-type pad layer 202 If the area is too large, it will also cause the problem of reduced bonding force between the P-type pad layer 201 and the N-type pad layer 202. Therefore, the present invention sets the maximum distance to 300 μm; in this embodiment, the first insulating protective layer 17 and The second insulating protective layer 19 is both a SiO ₂ layer. The P-type pad layer 201 is electrically connected to the P-type connecting layer 161 through the P-type insulating protective layer through hole 192. The N-type pad layer 202 passes through the N-type insulating protective layer. The through hole 193 forms an electrical connection with the N-type connection layer 162; the distance f from the edge of the second through hole 191 to the edge of the connection layer 16 is 10 μm, and the distance h from the edge of the P-type pad layer 201 to the edge of the N-type pad layer 202 is 200 μm; The pad layer 20 may be composed of one or more of an Al layer, a Ti layer, a Pt layer, a Ni layer, an Au layer, a Sn layer, and an AuSn layer. In specific implementation, the pad layer 20 is an Au layer.

The metal protective layer 18 includes a P-type metal protective layer 181, an N-type metal protective layer 182 and an anti-ejector layer 183. The P-type metal protective layer 181 is placed on the N-type connection layer 162 on one side of the P-type pad layer 201. Between an insulating protective layer 17 and the second insulating protective layer 19, and the width of the projection of the P-type metal protective layer 181 on the substrate 10 is greater than the width of the projection of the N-type connection layer 162 on the substrate 10, the P-type metal The distance g1 from the projected edge of the protective layer 181 on the substrate 10 to the projected edge of the N-type connection layer 162 on the substrate 10 is between 5 μm and 15 μm; the N-type metal protective layer 182 is placed on one side of the N-type pad layer 202 between the first insulating protective layer 17 and the second insulating protective layer 19 above the P-type connection layer 161 , and the projected width of the N-type metal protective layer 182 on the substrate 10 is larger than that of the P-type connection layer 161 on the substrate 10 The width of the projection on the substrate 10, the distance g2 from the projected edge of the N-type metal protective layer 182 on the substrate 10 to the projected edge of the P-type connection layer 161 on the substrate 10 is between 5 μm and 15 μm; the anti-ejector layer 183 is placed on the flip chip Between the first insulating protective layer 17 and the second insulating protective layer 19 in the center of the LED chip, the anti-ejector layer 183 is a disk with a diameter between 50 μm and 100 μm.

The distance from the projected edge of the P-type metal protective layer 181 on the substrate 10 to the projected edge of the N-type connection layer 162 on the substrate 10 is set to ensure that the projection of the P-type metal protective layer 181 on the substrate 10 completely covers this area. Part of the N-type connection layer 162; the distance from the projected edge of the N-type metal protective layer 182 on the substrate 10 to the projected edge of the P-type connection layer 161 on the substrate 10 is to ensure that the N-type metal protective layer 182 is on the substrate. The projection on the bottom 10 completely covers this part of the P-type connection layer 161; the anti-ejector layer 183 can prevent the sorting ejector pin from damaging the LED chip during the LED chip sorting process. The diameter of 50 μm-100 μm is set as the search accuracy of the ejector pin. To prevent the ejector pin from deflecting and not touching the disc of the anti-ejector pin layer 183; in this embodiment, the metal protective layer 18 can be one of inert metals such as Al layer, Cr layer, Ni layer, Sb layer, Be layer, etc. Or multiple combinations. During specific implementation, the metal protective layer 18 is a Ni layer; the distance g1 from the projected edge of the P-type metal protective layer 181 to the projected edge of the N-type connection layer 162 is 12 μm, and the projected edge of the N-type metal protective layer 182 to the P-type connection The projected edge distance g2 of layer 161 is 12 μm, and the anti-ejector layer 183 is a disk with a diameter of 75 μm.

Example 2

Referring to Figure 4, correspondingly, the present invention also provides a method for preparing a flip-chip light-emitting diode chip, which is used to prepare the flip-chip light-emitting diode chip as described above. The method includes:

S1: Provide a substrate 10; the substrate 10 is a light-transmitting material, which can be a GaN layer, an AlN layer, or an Al ₂ O ₃ layer; in this embodiment, the substrate 10 is a GaN layer.

S2: Deposit an epitaxial layer 11 on the substrate 10. The epitaxial layer 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113. In this embodiment, the MOCVD (Metal Organic Chemical Vapor Deposition) process is used in sequence. The N-type semiconductor layer 111, the active light-emitting layer 112, and the P-type semiconductor layer 113 are grown.

S3: Prepare the isolation trench 114 on the N-type semiconductor layer 111; specifically, apply photoresist on the P-type semiconductor layer 113, and then expose and develop to remove part of the photoresist, exposing the surrounding and internal parts of the LED chip. P-type semiconductor layer 113, and then use an inductively coupled plasma etching process to remove the exposed P-type semiconductor layer 113 and the active light-emitting layer 112 under this part of P-type semiconductor layer 113, exposing the N-type semiconductor layer 111, and then Remove the remaining photoresist to obtain the P-type semiconductor layer 113, active light-emitting layer 112, and N-type semiconductor layer 111 of the LED chip; then apply photoresist on the surfaces of the N-type semiconductor layer 111 and the P-type semiconductor layer 113, and then expose . Develop to remove part of the photoresist, exposing part of the N-type semiconductor layer 111 around the LED chip. Then use inductively coupled plasma etching to remove the exposed N-type semiconductor layer 111, expose the substrate 10, and form an isolation trench. 114, and then remove the remaining photoresist.

S4: Deposit the current blocking layer 12 on the P-type semiconductor layer 113. The current blocking layer 12 extends to the N-type semiconductor layer 111 and covers the isolation trench 114; specifically, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is used to deposit the current blocking layer 12 on the N-type semiconductor layer 111. SiO _{2 is deposited on the surface of the P-type semiconductor layer 113, the N-type semiconductor layer 111, and the isolation trench 114, and then photoresist is coated on the SiO 2 surface} , and then exposed and developed to remove part of the photoresist, exposing part of SiO ₂ , and then The exposed SiO ₂ is etched away using BOE etching solution, and then the photoresist is removed to form a current blocking layer 12 with a disc structure having a diameter of 35 μm.

S5: Deposit the current expansion layer 13 on the current blocking layer 12; specifically, use the Sputter (magnetron sputtering) process to deposit on the surface of the P-type semiconductor layer 113, the N-type semiconductor layer 111, the isolation trench 114, and the current blocking layer 12. ITO (indium tin oxide), then apply photoresist on the surface of ITO, then expose and develop to remove part of the photoresist, exposing part of the ITO, and then use a mixture of FeCl ₃ and HCl to corrode the exposed ITO, and then The photoresist is removed to form the current spreading layer 13; the distance between the edge of the current spreading layer 13 and the edge of the P-type semiconductor layer 113 is equal to 6 μm.

S6: Deposit an electrode layer 14 on the current spreading layer 13 and the N-type semiconductor layer 111. The electrode layer 14 includes a P-type electrode layer 141 located on the current spreading layer 13 and an N-type electrode layer located on the N-type semiconductor layer 111. 142; Specifically, a negative photoresist is coated on the surface of the isolation trench 114, the N-type semiconductor layer 111 and the current expansion layer 13, and then exposed and developed to remove part of the photoresist, exposing part of the N-type semiconductor layer 111 and part of the current. Expansion layer 13, and then use electron beam evaporation process to evaporate Cr/Al/Ti/Pt/Ni/Au metal, then use blue film stripping technology to remove the metal on the remaining photoresist, and then remove the remaining photoresist to obtain P Type electrode layer 141 and N-type electrode layer 142; P-type electrode layer 141 has a diameter of 20 μm, N-type electrode layer 142 has a diameter of 25 μm, the distance between the edge of P-type electrode layer 141 and the edge of current blocking layer 12 is equal to 10 μm, and N-type electrode layer 142 The edge distance from the P-type semiconductor layer 113 is equal to 9 μm.

S7: Deposit the Bragg reflective layer 15 on the electrode layer 14; specifically, use electron beam evaporation technology to periodically stack 28 groups of SiO ₂ on the surface of the isolation trench 114, the N-type semiconductor layer 111, the current spreading layer 13 and the electrode layer 14. and TiO ₂ layer to form a Bragg reflective layer 15, then apply photoresist on the surface of the Bragg reflective layer 15, then expose and develop to remove part of the photoresist, and then use an inductively coupled plasma etching process to remove the exposed Bragg reflection layer 15, and then remove the remaining photoresist to form a P-type Bragg via 152 and an N-type Bragg via 153; the distance between the edge of the P-type Bragg via 152 or the N-type Bragg via 153 and the edge of the electrode layer 14 is equal to 5 μm.

S8: Deposit the connection layer 16 on the Bragg reflective layer 15. The connection layer 16 includes a P-type connection layer 161 electrically connected to the P-type electrode layer 141 and an N-type connection layer 162 electrically connected to the N-type electrode layer 142; specifically , apply negative photoresist on the surface of the Bragg reflective layer 15, then expose and develop to remove part of the photoresist, and then use electron beam evaporation technology to sequentially evaporate the highly reflective metal layer 163 and the protective metal layer of the connection layer 16 164. Current transmission layer 165. The current transmission layer 165 includes a first sub-layer 1661 and a second sub-layer 1662; the highly reflective metal layer 163 is a metal Ag layer, the protective metal layer 164 is a Ti layer, and the first sub-layer 1661 is composed of three groups. A periodic stack of TiW layers and Au layers, where the thickness of the TiW layer is 10% of the Au layer; the second sub-layer 1662 is a stack of three groups of TiW layers and Au layers, where the thickness of the TiW layer is 20% of the Au layer %; the distance from the edge of the P-type connection layer 161 to the edge of the N-type connection layer 162 is equal to 30 μm.

S9: Deposit the first insulating protective layer 17 on the connecting layer 16; specifically, use the PECVD process to deposit SiO2 on the surface of the connecting layer 16 and the Bragg reflective layer ₁₅ not covered by the connecting layer 16 to form the first insulating protective layer 17.

S10: Deposit the metal protective layer 18 on the first insulating protective layer 17; specifically, apply negative photoresist on the surface of the first insulating protective layer 17, then expose and develop to remove part of the photoresist, and then use electron beams The evaporation process evaporates the Ni layer, and then uses the blue film stripping process to remove the metal on the remaining photoresist, and then removes the remaining photoresist to obtain a metal protective layer 18, including a P-type metal protective layer 181 and an N-type metal protective layer. 182 and the anti-ejector layer 183, the distance from the edge of the P-type metal protective layer 181 to the N-type connection layer 162 is equal to 12 μm, and the distance from the edge of the N-type metal protective layer 182 to the P-type connection layer 161 is equal to 12 μm.

S11: Deposit the second insulating protective layer 19 on the metal protective layer 18; specifically, use the PECVD process to deposit _SiO2 on the surface of the metal protective layer 18 and the first insulating protective layer 17 not covered by the metal protective layer 18 to obtain the second The insulating protective layer 19 is then coated with photoresist on the surface of the second insulating protective layer 19, and then part of the photoresist is removed to expose part of the second insulating protective layer 19, and then an inductively coupled plasma etching process is used to remove the exposed parts. The second insulating protective layer 19 and the first insulating protective layer 17 below form P-type insulating protective layer through holes 192 and N-type insulating protective layer through holes 193, P-type insulating protective layer through holes 192 or N-type insulating protective layer The distance from the edge of the through hole 193 to the edge of the connection layer 16 is equal to 10 μm.

S12: Deposit the pad layer 20 on the second insulating protective layer 19. The pad layer 20 includes a P-type pad electrically connected to the P-type connection layer 161 and an N-type pad electrically connected to the N-type connection layer 162. ; Specifically, a negative photoresist is coated on the surface of the second insulating protective layer 19 and the P-type insulating protective layer through hole 192 and the N-type insulating protective layer through hole 193, and then exposed and developed to remove part of the photoresist, and then The Au layer is evaporated, and then the metal on the remaining photoresist is removed using a blue film stripping process, and then the photoresist is removed to obtain the P-type pad layer 201 and the N-type pad layer 202. The edge of the P-type pad layer 201 is The edge distance of the N-type pad layer 202 is equal to 200 μm.

In the preparation method of a flip-chip light-emitting diode chip according to an embodiment of the present invention, the highly reflective metal layer 163 can cooperate with the Bragg reflective layer 15 to form total reflection to ensure reflectivity. The protective metal layer 164 can protect the highly reflective metal layer 163 from migration. Not oxidized; the current transmission layer 165 has a plurality of transmission sub-layers 166 composed of periodically stacked TiW layers and Au layers, and the ratio of the thickness of the TiW layer to the thickness of the Au layer in different transmission sub-layers 166 along the chip growth direction is Linearly increases, so that when the current is injected into the connection layer 16, it is first transmitted horizontally and then vertically, so that the LED chip current spreads evenly, and the maximum current that can be used by the LED chip can be increased; and if the edge of the P-type connection layer 161 is connected to the N-type The distance between the edges of the layer 162 is less than 20 μm. When the LED chip is powered on, electromigration easily occurs between the edge of the P-type connection layer 161 and the edge of the N-type connection layer 162, causing a short circuit in the LED chip. If the distance is too large, the P-type connection will The overall area of layer 161 and N-type connection layer 162 is small, which affects the total reflection effect formed by connection layer 16 and Bragg reflection layer 15. Therefore, a moderate distance from the edge of P-type connection layer 161 to the edge of N-type connection layer 162 can ensure the stability of the LED chip. Works and has a good glow effect.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

On the premise that no conflict occurs, those skilled in the art can freely combine and superimpose the above additional technical features.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (10)

1. A flip-chip light-emitting diode chip, characterized in that it includes a substrate and an epitaxial layer, a current blocking layer, a current spreading layer, an electrode layer, a Bragg reflective layer, a connecting layer, and a first layer laminated sequentially on the substrate. Insulating protective layer, metal protective layer, second insulating protective layer, pad layer; The connection layer includes a plurality of P-type connection layers and a plurality of N-type connection layers with the same structure. The P-type connection layer includes a highly reflective metal layer, a protective metal layer and a current transmission layer stacked in sequence. The highly reflective metal layer The layer is an Al layer or an Ag layer, and the protective metal layer is composed of one or more stacks of a Ti layer, a Pt layer, a Ni layer, a Cr layer, and a Pb layer; The current transmission layer includes at least two transmission sub-layers stacked in sequence. The transmission sub-layer is composed of 3-5 groups of periodically stacked TiW layers and Au layers. The thickness of the TiW layer in the different transmission sub-layers accounts for the Au layer. The thickness ratio is between 10% and 40%, and the ratio of the TiW layer thickness to the Au layer thickness in the transmission sublayer increases linearly along the chip growth direction; The distance from the edge of the P-type connection layer to the edge of the N-type connection layer is between 20 μm and 40 μm. 2. The flip-chip light-emitting diode chip according to claim 1, wherein the epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially stacked on the substrate. An isolation trench is provided around the N-type semiconductor layer, and the Bragg reflective layer, the first insulating protective layer and the second insulating protective layer all extend to cover the isolation trench. 3. The flip-chip light-emitting diode chip according to claim 2, wherein the current blocking layer is a plurality of SiO ₂ disks or Al ₂ O ₃ disks with a diameter between 20 μm and 50 μm, and are placed on on the P-type semiconductor layer. 4. The flip-chip light-emitting diode chip according to claim 2, wherein the current spreading layer covers the current blocking layer and extends to the P-type semiconductor layer, and the edge of the current spreading layer reaches The distance between the edges of the P-type semiconductor layer is between 3 μm and 10 μm. 5. The flip-chip light-emitting diode chip according to claim 3, wherein the electrode layer includes a plurality of P-type electrode layers and a plurality of N-type electrode layers, and the P-type electrode layer and the N-type electrode The layers are all metal disks with a diameter between 10 μm and 30 μm. The P-type electrode layer is located on the current expansion layer and is concentric with the current blocking layer; the edge of the P-type electrode layer reaches the current blocking layer. The distance between the layer edges is between 5 μm and 15 μm; the N-type electrode layer is located on the N-type semiconductor layer and forms an electrical connection with the N-type semiconductor layer, and the edge of the N-type electrode layer is to the P The distance between the edges of the semiconductor layer is between 7 μm and 10 μm. 6. The flip-chip light-emitting diode chip according to claim 1, characterized in that the Bragg reflective layer is composed of 20-40 groups of periodically stacked _TiO2 layers and _SiO2 layers, and the Bragg reflective layer is provided with multiple layers. A first through hole, the connection layer is connected to the electrode layer through the first through hole, and the distance from the edge of the first through hole to the edge of the electrode layer is between 2 μm and 10 μm. 7. The flip-chip light-emitting _diode chip according to claim 1, wherein the first insulating protective layer and the second insulating protective layer are _SiO2 layers, _Al2O3 layers or SiN layers, so The first insulating protective layer and the second insulating protective layer are both provided with second through holes penetrating them, and the pad layer is electrically connected to the connection layer through the second through holes, so The distance from the edge of the second through hole to the edge of the connection layer is between 10 μm and 15 μm. 8. The flip-chip light-emitting diode chip according to claim 1, wherein the pad layer is placed on the second insulating protective layer and includes a P-type pad layer and an N-type pad layer, The distance from the edge of the P-type pad layer to the edge of the N-type pad layer is between 200 μm and 300 μm. 9. The flip-chip light-emitting diode chip according to claim 8, wherein the metal protective layer includes a P-type metal protective layer, an N-type metal protective layer and an anti-ejector layer, and the P-type metal protective layer is placed on between the first insulating protective layer and the second insulating protective layer on the N-type connection layer on one side of the P-type pad layer, and the P-type metal protective layer is on the substrate The width of the projection of the N-type connection layer on the substrate is greater than the width of the projection of the N-type connection layer on the substrate. The projection edge of the P-type metal protective layer on the substrate is to the edge of the N-type connection layer on the substrate. The projected edge distance on the bottom is between 5μm-15μm; The N-type metal protective layer is placed between the first insulating protective layer and the second insulating protective layer on the P-type connection layer on one side of the N-type pad layer, and the N-type metal protective layer The width of the projection of the N-type metal protective layer on the substrate is greater than the width of the projection of the P-type connection layer on the substrate, and the projection edge of the N-type metal protective layer on the substrate reaches the The projected edge distance of the P-type connection layer on the substrate is between 5 μm and 15 μm; The anti-ejector layer is placed between the first insulating protective layer and the second insulating protective layer in the center of the flip-chip LED chip, and the anti-ejector layer is a disc with a diameter between 50 μm and 100 μm. 10. A method for preparing a flip-chip light-emitting diode chip, used to prepare the flip-chip light-emitting diode chip according to any one of claims 1 to 9, characterized in that the method includes: provide a substrate; Deposit an epitaxial layer on the substrate, the epitaxial layer including an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer; Prepare isolation trenches on the N-type semiconductor layer; Deposit a current blocking layer on the P-type semiconductor layer, the current blocking layer extends to the N-type semiconductor layer and covers the isolation trench; depositing a current spreading layer on the current blocking layer; Deposit an electrode layer on the current spreading layer and the N-type semiconductor layer, the electrode layer including a P-type electrode layer located on the current spreading layer and an N-type electrode layer located on the N-type semiconductor layer; depositing a Bragg reflective layer on the electrode layer; Deposit a connection layer on the Bragg reflective layer, the connection layer including a P-type connection layer electrically connected to the P-type electrode layer and an N-type connection layer electrically connected to the N-type electrode layer; depositing a first insulating protective layer on the connection layer; depositing a metal protective layer on the first insulating protective layer; depositing a second insulating protective layer on the metal protective layer; A pad layer is deposited on the second insulating protective layer. The pad layer includes a P-type pad electrically connected to the P-type connection layer and an N-type pad electrically connected to the N-type connection layer. plate.