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CN106848006A - Flip LED chips and preparation method thereof - Google Patents

Flip LED chips and preparation method thereof Download PDF

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Publication number
CN106848006A
CN106848006A CN201510881846.5A CN201510881846A CN106848006A CN 106848006 A CN106848006 A CN 106848006A CN 201510881846 A CN201510881846 A CN 201510881846A CN 106848006 A CN106848006 A CN 106848006A
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layer
type gan
deep groove
opening
aluminum oxide
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朱秀山
王倩静
徐慧文
李起鸣
张宇
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Enraytek Optoelectronics Co Ltd
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Enraytek Optoelectronics Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/011Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/814Bodies having reflecting means, e.g. semiconductor Bragg reflectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/816Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H10H20/8162Current-blocking structures

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Abstract

本发明提供一种倒装LED芯片及其制备方法,包括以下步骤:1)提供生长衬底,在生长衬底上依次生长n型GaN层、发光层多量子阱及p型GaN层;2)形成贯穿p型GaN层及发光层多量子阱的第一深槽;3)在p型GaN层表面形成欧姆接触及电流扩展层;4)在欧姆接触及电流扩展层表面形成反射层;5)在反射层表面、内侧及第一深槽底部形成反射层保护层;6)采用原子层沉积法在步骤5)得到的结构表面形成氧化铝层;7)在氧化铝层内形成第一开口及第二开口;8)在第二开口内形成N电极,在第一开口内及氧化铝层表面形成P电极。采用原子层沉积制备的氧化铝层具有更好的绝缘性能和金属阻挡性能,从而保证倒装芯片在大电流使用下的可靠性能。

The invention provides a flip-chip LED chip and a preparation method thereof, comprising the following steps: 1) providing a growth substrate, and sequentially growing an n-type GaN layer, a light-emitting layer multi-quantum well and a p-type GaN layer on the growth substrate; 2) Form the first deep groove that runs through the p-type GaN layer and the multi-quantum well of the light-emitting layer; 3) Form an ohmic contact and a current spreading layer on the surface of the p-type GaN layer; 4) Form a reflective layer on the surface of the ohmic contact and current spreading layer; 5) Forming a reflective layer protection layer on the reflective layer surface, inner side and bottom of the first deep groove; 6) forming an aluminum oxide layer on the surface of the structure obtained in step 5) by atomic layer deposition; 7) forming a first opening and an aluminum oxide layer in the aluminum oxide layer The second opening; 8) forming an N electrode in the second opening, and forming a P electrode in the first opening and on the surface of the aluminum oxide layer. The aluminum oxide layer prepared by atomic layer deposition has better insulation performance and metal barrier performance, thus ensuring the reliable performance of the flip chip under high current use.

Description

倒装LED芯片及其制备方法Flip-chip LED chip and preparation method thereof

技术领域technical field

本发明属于半导体技术领域,特别是涉及一种倒装LED芯片及其制备方法。The invention belongs to the technical field of semiconductors, in particular to a flip-chip LED chip and a preparation method thereof.

背景技术Background technique

发光二极管(Light Emitting Diode,简称LED)是一种半导体固态发光器件,利用半导体P-N结电致发光原理制成。LED器件具有开启电压低、体积小、响应快、稳定性好、寿命长、无污染等良好光电性能,因此在室外室内照明、背光、显示、交通指示等领域具有越来越广泛的应用。A light emitting diode (Light Emitting Diode, referred to as LED) is a semiconductor solid-state light-emitting device, which is made by using the principle of semiconductor P-N junction electroluminescence. LED devices have good photoelectric properties such as low turn-on voltage, small size, fast response, good stability, long life, and no pollution. Therefore, they are widely used in outdoor and indoor lighting, backlighting, display, traffic indication and other fields.

LED芯片结构有三种类型,分别为水平结构(正装芯片)、垂直结构(垂直结构芯片)和倒装结构(倒装芯片);倒装结构即芯片P、N电极在GaN的同侧,量子阱发出的光主要通过透明蓝宝石面逸出,没有正装芯片和垂直芯片电极和封装打金线遮光的问题,电流通过反射层金属直接注入,电流分布均匀,电压低亮度高,适用于大功率和大电流密度的芯片使用,倒装芯片产品具有免打线、低电压、高光效、低热阻、高可靠性、高饱和电流密度等优点,逐渐成为市场重点开发方向。There are three types of LED chip structures, namely horizontal structure (front mounted chip), vertical structure (vertical structure chip) and flip chip structure (flip chip); the flip chip structure means that the P and N electrodes of the chip are on the same side of GaN, and the quantum well The emitted light mainly escapes through the transparent sapphire surface. There is no problem of shading the front-mounted chip and vertical chip electrodes and gold wires on the package. The current is directly injected through the metal of the reflective layer. The current distribution is uniform, and the voltage is low and the brightness is high. It is suitable for high power and large The use of chips with current density, flip chip products have the advantages of no wire bonding, low voltage, high light efficiency, low thermal resistance, high reliability, high saturation current density, etc., and have gradually become the key development direction of the market.

但是在倒装芯片制程中会用到在受热会扩散的Ag和Al材料,并且使用SiO2作为正、负电极的绝缘材料和金属的阻挡层材料,在大电流使用情况下可靠性能得不到保障。However, in the flip-chip process, Ag and Al materials that will diffuse when heated are used, and SiO2 is used as the insulating material of the positive and negative electrodes and the barrier layer material of the metal, so the reliability cannot be guaranteed under the condition of high current use. .

倒装芯片制程过程中,需要绝缘材料对正负电极进行绝缘,同时这层绝缘材料又需要起到阻挡金属扩散的作用,目前通常情况下绝缘材料是使用PECVD(等离子体增强化学气相沉积法)沉积的SiO2,而SiO2介电常数约为3.9,且膜层内大都有空洞,且膜层应力比较大,受基底材料的形貌比较大,容易出现断裂异常,从而对芯片的可靠性能没有办法保证;During the flip-chip manufacturing process, an insulating material is required to insulate the positive and negative electrodes, and at the same time, this layer of insulating material needs to play a role in blocking metal diffusion. Currently, the insulating material is usually PECVD (Plasma Enhanced Chemical Vapor Deposition) Deposited SiO 2 , and the dielectric constant of SiO 2 is about 3.9, and most of the film has cavities, and the stress of the film is relatively large, and the shape of the substrate material is relatively large, which is prone to abnormal fracture, which affects the reliability of the chip. There is no guarantee;

SiO2作为绝缘层存在如下:1、SiO2对金属的阻挡能力不足,导致Barrier(阻挡层)和N孔金属在受热情况下会想刻蚀边框处扩散,导致漏电;2、SiO2膜层受到基底形貌的影响在Barrier边界处容易出现断裂,导致Pad内的金属会沿着SiO2的裂缝渗透到N孔金属,导致漏电。The existence of SiO 2 as an insulating layer is as follows: 1. The barrier ability of SiO 2 to metal is insufficient, causing the Barrier (barrier layer) and N-hole metal to diffuse at the etched frame when heated, resulting in leakage; 2. SiO 2 film layer Affected by the substrate morphology, fractures are prone to occur at the boundary of the Barrier, causing the metal in the Pad to penetrate into the N-hole metal along the SiO 2 cracks, resulting in leakage.

发明内容Contents of the invention

鉴于以上所述现有技术的缺点,本发明的目的在于提供一种倒装LED芯片及其制备方法,用于解决现有技术中使用SiO2作为绝缘层而存在的对金属的阻挡能力不足,导致Barrier和N孔金属在受热情况下会想刻蚀边框处扩散,导致漏电的问题及受到基底形貌的影响在Barrier边界处容易出现断裂,导致Pad内的金属会沿着SiO2的裂缝渗透到N孔金属,导致漏电的问题。In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a flip-chip LED chip and its preparation method, which is used to solve the problem of insufficient barrier ability to metals in the prior art using SiO2 as an insulating layer. As a result, barrier and N-hole metals will want to diffuse at the etched border when heated, resulting in leakage problems and being affected by the substrate morphology. Fractures are prone to occur at the border of the barrier, causing the metal in the pad to penetrate along the cracks of SiO 2 To the N-hole metal, causing leakage problems.

为实现上述目的及其他相关目的,本发明提供一种倒装LED芯片的制备方法,所述制备方法包括以下步骤:In order to achieve the above purpose and other related purposes, the present invention provides a method for preparing a flip-chip LED chip, the preparation method comprising the following steps:

1)提供生长衬底,在所述生长衬底上依次生长n型GaN层、发光层多量子阱及p型GaN层;1) A growth substrate is provided, and an n-type GaN layer, a light-emitting layer multiple quantum well, and a p-type GaN layer are sequentially grown on the growth substrate;

2)形成贯穿所述p型GaN层及所述发光层多量子阱的第一深槽,所述第一深槽的底部位于所述n型GaN层内;2) forming a first deep groove penetrating through the p-type GaN layer and the multi-quantum well of the light-emitting layer, the bottom of the first deep groove is located in the n-type GaN layer;

3)在所述p型GaN层表面形成欧姆接触及电流扩展层,所述欧姆接触及电流扩展层的面积小于所述p型GaN层的面积;3) forming an ohmic contact and a current spreading layer on the surface of the p-type GaN layer, the area of the ohmic contact and the current spreading layer being smaller than the area of the p-type GaN layer;

4)在所述欧姆接触及电流扩展层表面形成反射层;4) forming a reflective layer on the surface of the ohmic contact and the current spreading layer;

5)在所述反射层表面、内侧及所述第一深槽底部形成反射层保护层,位于所述第一深槽底部的所述反射层保护层与所述第一深槽的侧壁相隔一定的间距;5) forming a reflective layer protective layer on the reflective layer surface, inner side and bottom of the first deep groove, the reflective protective layer at the bottom of the first deep groove is separated from the sidewall of the first deep groove a certain distance;

6)采用原子层沉积法在步骤5)得到的结构表面形成氧化铝层;6) forming an aluminum oxide layer on the surface of the structure obtained in step 5) by atomic layer deposition;

7)在所述氧化铝层内形成第一开口及第二开口,所述第一开口暴露出位于所述反射层表面的所述反射层保护层,所述第二开口暴露出位于所述第一深槽底部的所述反射层保护层;7) Forming a first opening and a second opening in the aluminum oxide layer, the first opening exposes the protective layer of the reflective layer on the surface of the reflective layer, and the second opening exposes the protective layer on the surface of the second reflective layer. said reflective layer protective layer at the bottom of a deep groove;

8)在所述第二开口内形成N电极,在所述第一开口内及所述氧化铝层表面形成P电极。8) forming an N electrode in the second opening, and forming a P electrode in the first opening and on the surface of the aluminum oxide layer.

作为本发明的倒装LED芯片的制备方法的一种优选方案,所述生长衬底为蓝宝石衬底、GaN衬底、硅衬底或碳化硅衬底。As a preferred solution of the method for preparing a flip-chip LED chip of the present invention, the growth substrate is a sapphire substrate, a GaN substrate, a silicon substrate or a silicon carbide substrate.

作为本发明的倒装LED芯片的制备方法的一种优选方案,步骤1)与步骤2)之间还包括在步骤1)得到的结构内形成第二深槽,以将步骤1)得到的结构分割为若干个独立的芯片单元的步骤,所述第二深槽贯穿所述p型GaN层、所述发光层多量子阱及所述n型GaN层,且所述第二深槽的底部位于所述生长衬底内。As a preferred solution of the preparation method of the flip-chip LED chip of the present invention, step 1) and step 2) also include forming a second deep groove in the structure obtained in step 1), so that the structure obtained in step 1) The step of dividing into several independent chip units, the second deep groove runs through the p-type GaN layer, the light-emitting layer multi-quantum well and the n-type GaN layer, and the bottom of the second deep groove is located within the growth substrate.

作为本发明的倒装LED芯片的制备方法的一种优选方案,采用BCl3、Cl2及Ar等离子体选择性刻蚀所述p型GaN层、所述发光层多量子阱、所述n型GaN层及所述生长衬底以形成所述第二深槽。As a preferred solution of the preparation method of the flip-chip LED chip of the present invention, BCl 3 , Cl 2 and Ar plasma are used to selectively etch the p-type GaN layer, the multi-quantum well of the light-emitting layer, the n-type GaN layer and the growth substrate to form the second deep groove.

作为本发明的倒装LED芯片的制备方法的一种优选方案,采用BCl3、Cl2及Ar等离子体选择性刻蚀所述p型GaN层、所述发光层多量子阱及所述n型GaN层以形成所述第一深槽。As a preferred solution of the preparation method of the flip-chip LED chip of the present invention, BCl 3 , Cl 2 and Ar plasma are used to selectively etch the p-type GaN layer, the multi-quantum well of the light-emitting layer and the n-type GaN layer to form the first deep groove.

作为本发明的倒装LED芯片的制备方法的一种优选方案,利用磁控溅射工艺或反应等离子沉积工艺在所述p型GaN层表面沉积ITO薄膜作为所述欧姆接触及电流扩展层。As a preferred solution of the method for preparing the flip-chip LED chip of the present invention, a magnetron sputtering process or a reactive plasma deposition process is used to deposit an ITO thin film on the surface of the p-type GaN layer as the ohmic contact and current spreading layer.

作为本发明的倒装LED芯片的制备方法的一种优选方案,利用磁控溅射工艺或MOCVD工艺在所述p型GaN层表面沉积ZnO薄膜作为所述欧姆接触及电流扩展层。As a preferred solution of the method for preparing the flip-chip LED chip of the present invention, a ZnO thin film is deposited on the surface of the p-type GaN layer as the ohmic contact and current spreading layer by magnetron sputtering process or MOCVD process.

作为本发明的倒装LED芯片的制备方法的一种优选方案,利用磁控溅射工艺在所述欧姆接触及电流扩展层表面形成所述反射层,所述反射层的材料为Ag-TiW或Ag-TiW-Pt。As a preferred solution of the preparation method of the flip-chip LED chip of the present invention, the reflective layer is formed on the surface of the ohmic contact and the current spreading layer by using a magnetron sputtering process, and the material of the reflective layer is Ag-TiW or Ag-TiW-Pt.

作为本发明的倒装LED芯片的制备方法的一种优选方案,采用磁控溅射工艺或电子束气相蒸发工艺在所述反射层表面、内侧及所述第一深槽底部形成所述反射层保护层,所述反射层保护层的材料为Cr、Al、TiW、Pt、Ti、Au、Ni中的一种或几种的组合。As a preferred solution of the method for preparing the flip-chip LED chip of the present invention, the reflective layer is formed on the surface, inner side, and bottom of the first deep groove by using a magnetron sputtering process or an electron beam vapor phase evaporation process. The protective layer, the material of the reflective layer protective layer is one or a combination of Cr, Al, TiW, Pt, Ti, Au, Ni.

作为本发明的倒装LED芯片的制备方法的一种优选方案,所述氧化铝层包覆所述反射层保护层及裸露的所述反射层、所述欧姆接触及电流扩展层、所述p型GaN层、所述发光层多量子阱、所述n型GaN层,所述氧化铝层的厚度为200埃~5000埃。As a preferred solution of the preparation method of the flip-chip LED chip of the present invention, the aluminum oxide layer covers the reflective layer protection layer and the exposed reflective layer, the ohmic contact and current spreading layer, the p -type GaN layer, the light-emitting layer multiple quantum wells, the n-type GaN layer, and the thickness of the aluminum oxide layer is 200-5000 angstroms.

本发明还提供一种倒装LED芯片,所述倒装LED芯片包括:生长衬底、n型GaN层、发光层多量子阱、p型GaN层、欧姆接触及电流扩展层、反射层、反射层保护层、氧化铝层、N电极及P电极;其中,The present invention also provides a flip-chip LED chip, which includes: a growth substrate, an n-type GaN layer, a light-emitting layer with multiple quantum wells, a p-type GaN layer, an ohmic contact and a current spreading layer, a reflective layer, a reflective Layer protection layer, aluminum oxide layer, N electrode and P electrode; Wherein,

所述n型GaN层、所述发光层多量子阱、所述p型GaN层、所述欧姆接触及电流扩展层及所述反射层由下至上依次叠置于所述生长衬底的上表面;所述n型GaN层、所述发光层多量子阱及所述p型GaN层内形成有第一深槽,所述第一深槽贯穿所述p型GaN层及所述发光层多量子阱,且所述第一深槽的底部位于所述n型GaN层内;所述欧姆接触及电流扩展层及所述反射层内形成有贯通孔,所述贯通孔与所述第一深槽上下对应,且所述贯通孔的横向尺寸大于所述第一深槽的横向尺寸;The n-type GaN layer, the light-emitting layer multi-quantum well, the p-type GaN layer, the ohmic contact and current spreading layer, and the reflective layer are sequentially stacked on the upper surface of the growth substrate from bottom to top ; A first deep groove is formed in the n-type GaN layer, the multi-quantum well of the light-emitting layer and the p-type GaN layer, and the first deep groove runs through the p-type GaN layer and the multi-quantum well of the light-emitting layer well, and the bottom of the first deep groove is located in the n-type GaN layer; a through hole is formed in the ohmic contact and current spreading layer and the reflective layer, and the through hole and the first deep groove Corresponding up and down, and the lateral dimension of the through hole is larger than the lateral dimension of the first deep groove;

所述反射层保护层位于所述反射层表面、内侧及所述第一深槽底部,位于所述第一深槽底部的所述反射层保护层与所述第一深槽的侧壁相隔一定的间距;The protective layer of the reflective layer is located on the surface of the reflective layer, the inner side and the bottom of the first deep groove, and the protective layer of the reflective layer at the bottom of the first deep groove is separated from the sidewall of the first deep groove by a certain distance. Pitch;

所述氧化铝层覆盖所述反射层保护层并填满所述贯通孔及所述第一深槽;所述氧化铝层内形成有第一开口及第二开口,所述第一开口暴露出位于所述反射层表面的所述反射层保护层,所述第二开口暴露出位于所述第一深槽底部的所述反射层保护层;The aluminum oxide layer covers the reflective layer protection layer and fills the through hole and the first deep groove; a first opening and a second opening are formed in the aluminum oxide layer, and the first opening exposes The reflective layer protective layer located on the surface of the reflective layer, the second opening exposes the reflective layer protective layer located at the bottom of the first deep groove;

所述N电极位于所述第二开口内,所述P电极位于所述第一开口内及所述氧化铝层表面。The N electrode is located in the second opening, and the P electrode is located in the first opening and on the surface of the aluminum oxide layer.

作为本发明的倒装LED芯片的一种优选方案,所述氧化铝层采用原子层沉积法制备而得,所述氧化铝层的厚度为200埃~5000埃。As a preferred solution of the flip-chip LED chip of the present invention, the aluminum oxide layer is prepared by an atomic layer deposition method, and the thickness of the aluminum oxide layer is 200 angstroms to 5000 angstroms.

如上所述,本发明的倒装LED芯片及其制备方法,具有以下有益效果:采用ALD(原子层沉积)制备的Al2O3材料是单个原子层逐层沉积,膜层密度高,更加致密,并且不容易受基底形貌的影响,对深宽比大的台阶区域覆盖性好,采用原子层沉积法制备的Al2O3层作为绝缘层和金属阻挡层相对于PECVD沉积的SiO2具有更好的绝缘性能和金属阻挡性能,从而保证倒装芯片在大电流使用下的可靠性能。As mentioned above, the flip-chip LED chip and its preparation method of the present invention have the following beneficial effects: the Al 2 O 3 material prepared by ALD (atomic layer deposition) is deposited layer by layer with a single atomic layer, and the film layer density is high and denser. , and it is not easily affected by the substrate morphology, and has good coverage for the step area with a large aspect ratio. The Al 2 O 3 layer prepared by atomic layer deposition is used as an insulating layer and a metal barrier layer. Compared with SiO 2 deposited by PECVD, it has Better insulation performance and metal barrier performance, so as to ensure the reliable performance of flip chip under high current use.

附图说明Description of drawings

图1显示为本发明倒装LED芯片的制备方法的流程图。Fig. 1 is a flow chart showing a method for preparing a flip-chip LED chip of the present invention.

图2至图3显示为本发明倒装LED芯片的制备方法中S1步骤呈现的结构示意图。FIG. 2 to FIG. 3 are schematic structural diagrams of step S1 in the manufacturing method of the flip-chip LED chip of the present invention.

图4显示为本发明倒装LED芯片的制备方法中S2步骤呈现的结构示意图。FIG. 4 is a schematic structural view of step S2 in the method for preparing a flip-chip LED chip of the present invention.

图5显示为本发明倒装LED芯片的制备方法中S3步骤呈现的结构示意图。FIG. 5 is a schematic structural view of step S3 in the method for preparing a flip-chip LED chip according to the present invention.

图6显示为本发明倒装LED芯片的制备方法中S4步骤呈现的结构示意图。FIG. 6 is a schematic structural view of step S4 in the method for preparing a flip-chip LED chip according to the present invention.

图7显示为本发明倒装LED芯片的制备方法中S5步骤呈现的结构示意图。FIG. 7 is a schematic structural view of step S5 in the method for preparing a flip-chip LED chip according to the present invention.

图8显示为本发明倒装LED芯片的制备方法中S6及S7步骤呈现的结构示意图。FIG. 8 is a schematic structural view of steps S6 and S7 in the method for preparing a flip-chip LED chip according to the present invention.

图9显示为本发明倒装LED芯片的制备方法中S8步骤呈现的结构示意图。FIG. 9 is a schematic structural view of step S8 in the method for preparing a flip-chip LED chip according to the present invention.

元件标号说明Component designation description

100 生长衬底100 growth substrates

101 n型GaN层101 n-type GaN layer

102 发光层多量子阱102 Light-emitting layer multiple quantum wells

103 p型GaN层103 p-type GaN layer

104 第一深槽104 First Deep Groove

105 欧姆接触及电流扩展层105 ohm contact and current spreading layer

106 反射层106 reflective layer

107 反射层保护层107 reflective protective layer

108 氧化铝层108 aluminum oxide layer

109 第一开口109 first opening

110 第二开口110 second opening

111 N电极111 N electrode

112 P电极112 P electrode

113 第二深槽113 Second deep groove

具体实施方式detailed description

以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

请参阅图1至图9需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。Please refer to FIG. 1 to FIG. 9. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, although the diagrams only show components related to the present invention rather than actual implementation. The number, shape, and size of the components are drawn, and the type, quantity, and proportion of each component can be changed at will during actual implementation, and the layout of the components may also be more complicated.

请参阅图1,本发明提供一种倒装LED芯片的制备方法,所述制备方法包括以下步骤:Please refer to Fig. 1, the present invention provides a kind of preparation method of flip-chip LED chip, and described preparation method comprises the following steps:

1)提供生长衬底,在所述生长衬底上依次生长n型GaN层、发光层多量子阱及p型GaN层;1) A growth substrate is provided, and an n-type GaN layer, a light-emitting layer multiple quantum well, and a p-type GaN layer are sequentially grown on the growth substrate;

2)形成贯穿所述p型GaN层及所述发光层多量子阱的第一深槽,所述第一深槽的底部位于所述n型GaN层内;2) forming a first deep groove penetrating through the p-type GaN layer and the multi-quantum well of the light-emitting layer, the bottom of the first deep groove is located in the n-type GaN layer;

3)在所述p型GaN层表面形成欧姆接触及电流扩展层,所述欧姆接触及电流扩展层的面积小于所述p型GaN层的面积;3) forming an ohmic contact and a current spreading layer on the surface of the p-type GaN layer, the area of the ohmic contact and the current spreading layer being smaller than the area of the p-type GaN layer;

4)在所述欧姆接触及电流扩展层表面形成反射层;4) forming a reflective layer on the surface of the ohmic contact and the current spreading layer;

5)在所述反射层表面、内侧及所述第一深槽底部形成反射层保护层,位于所述第一深槽底部的所述反射层保护层与所述第一深槽的侧壁相隔一定的间距;5) forming a reflective layer protective layer on the reflective layer surface, inner side and bottom of the first deep groove, the reflective protective layer at the bottom of the first deep groove is separated from the sidewall of the first deep groove a certain distance;

6)采用原子层沉积法在步骤5)得到的结构表面形成氧化铝层;6) forming an aluminum oxide layer on the surface of the structure obtained in step 5) by atomic layer deposition;

7)在所述氧化铝层内形成第一开口及第二开口,所述第一开口暴露出位于所述反射层表面的所述反射层保护层,所述第二开口暴露出位于所述第一深槽底部的所述反射层保护层;7) Forming a first opening and a second opening in the aluminum oxide layer, the first opening exposes the protective layer of the reflective layer on the surface of the reflective layer, and the second opening exposes the protective layer on the surface of the second reflective layer. said reflective layer protective layer at the bottom of a deep groove;

8)在所述第二开口内形成N电极,在所述第一开口内及所述氧化铝层表面形成P电极。8) forming an N electrode in the second opening, and forming a P electrode in the first opening and on the surface of the aluminum oxide layer.

在步骤1)中,请参阅图1中的S1步骤及图2,提供生长衬底100,在所述生长衬底100上依次生长n型GaN层101、发光层多量子阱102及p型GaN层103。In step 1), referring to step S1 in FIG. 1 and FIG. 2, a growth substrate 100 is provided, on which an n-type GaN layer 101, a light-emitting layer multiple quantum well 102, and a p-type GaN are sequentially grown. Layer 103.

作为示例,所述生长衬底100可以为但不仅限于适合GaN及其半导体外延材料生长的蓝宝石衬底、GaN衬底、硅衬底或碳化硅衬底。As an example, the growth substrate 100 may be, but not limited to, a sapphire substrate, a GaN substrate, a silicon substrate or a silicon carbide substrate suitable for the growth of GaN and its semiconductor epitaxial materials.

作为示例,在所述生长衬底100上依次外延生长所述n型GaN层101、所述发光层多量子阱102及所述p型GaN层103。As an example, the n-type GaN layer 101 , the light-emitting layer multiple quantum well 102 and the p-type GaN layer 103 are epitaxially grown in sequence on the growth substrate 100 .

作为示例,请参阅图3,步骤1)之后还包括在步骤1)得到的结构内形成第二深槽113,以将步骤1)得到的结构分割为若干个独立的芯片单元的步骤,所述第二深槽113贯穿所述p型GaN层103、所述发光层多量子阱102及所述n型GaN层101,且所述第二深槽113的底部位于所述生长衬底100内。As an example, please refer to FIG. 3 , after step 1), it also includes forming a second deep groove 113 in the structure obtained in step 1), so as to divide the structure obtained in step 1) into several independent chip units. The second deep groove 113 runs through the p-type GaN layer 103 , the light-emitting layer multiple quantum well 102 and the n-type GaN layer 101 , and the bottom of the second deep groove 113 is located in the growth substrate 100 .

作为示例,采用光刻、刻蚀工艺在步骤1)得到的结构内形成所述第二深槽113,具体方法为:首先,在所述步骤1)得到的结构表面涂覆光刻胶层(未示出),采用光刻工艺图形化所述光刻胶层,以在所述光刻胶层内形成所述第二深槽113的图形;其次,依据图形化的所述光刻胶层采用BCl3、Cl2及Ar等离子体选择性刻蚀所述p型GaN层103、所述发光层多量子阱102、所述n型GaN层101及所述生长衬底100以形成所述第二深槽113;最后,去除所述光刻胶层。As an example, the second deep groove 113 is formed in the structure obtained in step 1) using photolithography and etching processes. The specific method is: first, coat a photoresist layer on the surface of the structure obtained in step 1) ( not shown), using a photolithography process to pattern the photoresist layer to form the pattern of the second deep groove 113 in the photoresist layer; secondly, according to the patterned photoresist layer BCl 3 , Cl 2 and Ar plasma are used to selectively etch the p-type GaN layer 103, the light-emitting layer multiple quantum well 102, the n-type GaN layer 101 and the growth substrate 100 to form the first Two deep grooves 113; finally, remove the photoresist layer.

在步骤2)中,请参阅图1中的S2步骤及图4,形成贯穿所述p型GaN层103及所述发光层多量子阱102的第一深槽104,所述第一深槽104的底部位于所述n型GaN层101内。In step 2), referring to step S2 in FIG. 1 and FIG. 4, a first deep groove 104 penetrating through the p-type GaN layer 103 and the light-emitting layer multiple quantum well 102 is formed, and the first deep groove 104 The bottom of the n-type GaN layer is located in the n-type GaN layer 101.

作为示例,采用光刻、刻蚀工艺在所述芯片单元内形成贯穿所述p型GaN层103及所述发光层多量子阱102的所述第一深槽104,具体方法为:首先,在所述芯片单元表面涂覆光刻胶层(未示出),采用光刻工艺图形化所述光刻胶层,以在所述光刻胶层内形成所述第一深槽104的图形;其次,依据图形化的所述光刻胶层采用BCl3、Cl2及Ar等离子体选择性刻蚀所述p型GaN层103、所述发光层多量子阱102及所述n型GaN层101以形成所述第一深槽104;最后,去除所述光刻胶层。As an example, the first deep groove 104 penetrating through the p-type GaN layer 103 and the light-emitting layer multiple quantum well 102 is formed in the chip unit by using photolithography and etching processes. The specific method is as follows: first, in The surface of the chip unit is coated with a photoresist layer (not shown), and the photoresist layer is patterned by a photolithography process to form the pattern of the first deep groove 104 in the photoresist layer; Secondly, according to the patterned photoresist layer, BCl 3 , Cl 2 and Ar plasma are used to selectively etch the p-type GaN layer 103, the light-emitting layer multi-quantum well 102 and the n-type GaN layer 101 to form the first deep groove 104; finally, remove the photoresist layer.

在步骤3)中,请参阅图1中的S3步骤及图5,在所述p型GaN层103表面形成欧姆接触及电流扩展层105,所述欧姆接触及电流扩展层105的面积小于所述p型GaN层103的面积。In step 3), referring to step S3 in FIG. 1 and FIG. 5, an ohmic contact and current spreading layer 105 is formed on the surface of the p-type GaN layer 103, and the area of the ohmic contact and current spreading layer 105 is smaller than that of the The area of the p-type GaN layer 103.

作为示例,在所述p型GaN层103表面形成所述欧姆接触及电流扩展层105的具体方法为:首先,利用磁控溅射工艺或反应等离子沉积工艺在所述p型GaN层103表面沉积ITO(氧化铟锡)薄膜;其次,在所述ITO薄膜表面涂覆光刻胶层(未示出),采用光刻工艺图形化所述光刻胶层,以在所述光刻胶层内定义出所述欧姆接触及电流扩展层105的图形;然后,依据图形化的所述光刻胶层刻蚀所述ITO薄膜以形成所述欧姆接触及电流扩展层105,最后,去除所述光刻胶层。As an example, the specific method for forming the ohmic contact and current spreading layer 105 on the surface of the p-type GaN layer 103 is as follows: firstly, depositing ITO (Indium Tin Oxide) film; secondly, a photoresist layer (not shown) is coated on the surface of the ITO film, and the photoresist layer is patterned by a photolithography process, so that in the photoresist layer Define the pattern of the ohmic contact and the current spreading layer 105; then, etch the ITO thin film according to the patterned photoresist layer to form the ohmic contact and the current spreading layer 105, and finally, remove the light Resist layer.

作为示例,利用磁控溅射工艺或反应等离子沉积工艺在所述p型GaN层103表面沉积的所述ITO(氧化铟锡)薄膜的厚度可以为但不仅限于50埃~3000埃。As an example, the thickness of the ITO (Indium Tin Oxide) thin film deposited on the surface of the p-type GaN layer 103 by magnetron sputtering process or reactive plasma deposition process may be, but not limited to, 50 angstroms to 3000 angstroms.

作为示例,在所述p型GaN层103表面形成所述欧姆接触及电流扩展层105的具体方法为:首先,利用磁控溅射工艺或MOCVD工艺在所述p型GaN层103表面沉积ZnO薄膜;其次,在所述ZnO薄膜表面涂覆光刻胶层(未示出),采用光刻工艺图形化所述光刻胶层,以在所述光刻胶层内定义出所述欧姆接触及电流扩展层105的图形;然后,依据图形化的所述光刻胶层刻蚀所述ZnO薄膜以形成所述欧姆接触及电流扩展层105,最后,去除所述光刻胶层。As an example, the specific method for forming the ohmic contact and current spreading layer 105 on the surface of the p-type GaN layer 103 is as follows: first, deposit a ZnO thin film on the surface of the p-type GaN layer 103 by using a magnetron sputtering process or an MOCVD process ; Secondly, a photoresist layer (not shown) is coated on the surface of the ZnO film, and the photoresist layer is patterned using a photolithography process to define the ohmic contact and The pattern of the current spreading layer 105; then, etching the ZnO thin film according to the patterned photoresist layer to form the ohmic contact and the current spreading layer 105, and finally, removing the photoresist layer.

作为示例,利用磁控溅射工艺或反应等离子沉积工艺在所述p型GaN层103表面沉积的所述ZnO薄膜的厚度可以为但不仅限于50埃~3000埃。As an example, the thickness of the ZnO thin film deposited on the surface of the p-type GaN layer 103 by magnetron sputtering process or reactive plasma deposition process may be, but not limited to, 50 angstroms to 3000 angstroms.

在步骤4)中,请参阅图1中的S4步骤及图6,在所述欧姆接触及电流扩展层105表面形成反射层106。In step 4), referring to step S4 in FIG. 1 and FIG. 6 , a reflective layer 106 is formed on the surface of the ohmic contact and current spreading layer 105 .

作为示例,利用磁控溅射工艺在所述欧姆接触及电流扩展层105表面形成所述反射层106,所述反射层106的材料可以为但不仅限于为Ag-TiW(Ag及TiW)或Ag-TiW-Pt(Ag、TiW及Pt),其中,Ag的厚度可以为但不仅限于750埃~3000埃,TiW的厚度可以为但不仅限于100埃~1000埃,Pt的厚度可以为但不仅限于100埃~1000埃。As an example, the reflective layer 106 is formed on the surface of the ohmic contact and current spreading layer 105 using a magnetron sputtering process, and the material of the reflective layer 106 can be but not limited to Ag-TiW (Ag and TiW) or Ag -TiW-Pt (Ag, TiW and Pt), wherein, the thickness of Ag can be but not limited to 750 angstroms to 3000 angstroms, the thickness of TiW can be but not limited to 100 angstroms to 1000 angstroms, and the thickness of Pt can be but not limited to 100 angstroms to 1000 angstroms.

作为示例,所述反射层106的面积稍大于所述欧姆接触及电流扩展层105的面积。As an example, the area of the reflective layer 106 is slightly larger than the area of the ohmic contact and current spreading layer 105 .

在步骤5)中,请参阅图1中的S5步骤及图7,在所述反射层106表面、内侧及所述第一深槽104底部形成反射层保护层107,位于所述第一深槽104底部的所述反射层保护层107与所述第一深槽104的侧壁相隔一定的间距。In step 5), please refer to the S5 step and FIG. 7 in FIG. 1, a reflective layer protection layer 107 is formed on the surface, inner side and bottom of the first deep groove 104 of the reflective layer 106, and is located in the first deep groove. The reflective protection layer 107 at the bottom of 104 is spaced from the sidewall of the first deep groove 104 by a certain distance.

作为示例,采用磁控溅射工艺或电子束气相蒸发工艺在所述反射层106表面、内侧及所述第一深槽104底部形成所述反射层保护层107,所述反射层保护层107的材料可以为但不仅限于Cr、Al、TiW、Pt、Ti、Au、Ni中的一种或几种的组合。As an example, a magnetron sputtering process or an electron beam vapor phase evaporation process is used to form the reflective layer protection layer 107 on the surface, inner side, and bottom of the first deep groove 104 of the reflective layer 106, and the reflective layer protection layer 107 The material can be but not limited to one or a combination of Cr, Al, TiW, Pt, Ti, Au, Ni.

作为示例,所述反射层保护层107的厚度可以为但不仅限于20埃~20000埃,其中,TiW的厚度为200埃~5000埃,Cr的厚度为20埃~500埃,Pt的厚度为200埃~1000埃,Ti的厚度范围为200埃~1000埃,Au的厚度为2000埃~5000埃,Ni的厚度为200埃~2000埃。As an example, the thickness of the reflective protective layer 107 may be, but not limited to, 20 angstroms to 20000 angstroms, wherein the thickness of TiW is 200 angstroms to 5000 angstroms, the thickness of Cr is 20 angstroms to 500 angstroms, and the thickness of Pt is 200 angstroms. Å to 1000 Å, the thickness of Ti is in the range of 200 Å to 1000 Å, the thickness of Au is in the range of 2000 Å to 5000 Å, and the thickness of Ni is in the range of 200 Å to 2000 Å.

作为示例,位于所述第一深槽104底部的所述反射层保护层107作为后续形成的N电极的接触性材料。As an example, the reflective layer protection layer 107 located at the bottom of the first deep groove 104 serves as a contact material for the subsequently formed N electrode.

作为示例,所述反射层保护层107为多层结构时,位于顶层的为Ni层。As an example, when the reflective protection layer 107 has a multi-layer structure, the top layer is a Ni layer.

在步骤6)中,请参阅图1中的S6步骤,采用原子层沉积法在步骤5)得到的结构表面形成氧化铝层108。In step 6), referring to step S6 in FIG. 1 , an aluminum oxide layer 108 is formed on the surface of the structure obtained in step 5) by atomic layer deposition.

作为示例,所述氧化铝层108包覆所述反射层保护层107及裸露的所述反射层106、所述欧姆接触及电流扩展层105、所述p型GaN层103、所述发光层多量子阱102、所述n型GaN层101,所述氧化铝层108的厚度可以为但不仅限于200埃~5000埃。As an example, the aluminum oxide layer 108 covers the reflective layer protection layer 107 and the exposed reflective layer 106, the ohmic contact and current spreading layer 105, the p-type GaN layer 103, the light emitting layer The thicknesses of the quantum well 102, the n-type GaN layer 101, and the aluminum oxide layer 108 may be, but not limited to, 200 angstroms to 5000 angstroms.

采用ALD(原子层沉积)制备的所述氧化铝层108是单个原子层逐层沉积,膜层密度高,更加致密,并且不容易受基底形貌的影响,对深宽比大的台阶区域覆盖性好,采用原子层沉积法制备的所述氧化铝层108作为绝缘层和金属阻挡层相对于PECVD沉积的SiO2具有更好的绝缘性能和金属阻挡性能,从而保证倒装芯片在大电流使用下的可靠性能。The aluminum oxide layer 108 prepared by ALD (atomic layer deposition) is a single atomic layer deposited layer by layer, the film layer density is high, denser, and is not easily affected by the shape of the substrate, covering the step area with a large aspect ratio Good performance, the aluminum oxide layer 108 prepared by atomic layer deposition method has better insulation performance and metal barrier performance than SiO2 deposited by PECVD as an insulating layer and metal barrier layer, thereby ensuring that the flip chip is used in high current Under the reliable performance.

在步骤7)中,请参阅图1中的S7步骤及图8,在所述氧化铝层108内形成第一开口109及第二开口110,所述第一开口109暴露出位于所述反射层106表面的所述反射层保护层107,所述第二开口110暴露出位于所述第一深槽104底部的所述反射层保护层107。In step 7), please refer to step S7 in FIG. 1 and FIG. 8, a first opening 109 and a second opening 110 are formed in the aluminum oxide layer 108, and the first opening 109 exposes the 106 on the reflective protective layer 107 , the second opening 110 exposes the reflective protective layer 107 at the bottom of the first deep groove 104 .

作为示例,所在所述氧化铝层108内形成第一开口109及第二开口110的具体方法为:首先,在所述氧化铝层108表面涂覆光刻胶层(未示出),采用光刻工艺图形化所述光刻胶层,以在所述光刻胶层内定义出所述第一开口109及所述第二开口110的图形;然后,依据图形化的所述光刻胶层刻蚀所述氧化铝层108以在所述氧化铝层108内形成所述第一开口109及所述第二开口110。As an example, the specific method for forming the first opening 109 and the second opening 110 in the aluminum oxide layer 108 is as follows: first, coat a photoresist layer (not shown) on the surface of the aluminum oxide layer 108, The photoresist layer is patterned by etching process, so as to define the patterns of the first opening 109 and the second opening 110 in the photoresist layer; then, according to the patterned photoresist layer The aluminum oxide layer 108 is etched to form the first opening 109 and the second opening 110 in the aluminum oxide layer 108 .

在步骤8)中,请参阅图1中的S8步骤及图9,在所述第二开口110内形成N电极111,在所述第一开口109内及所述氧化铝层108表面形成P电极112。In step 8), referring to step S8 in FIG. 1 and FIG. 9, an N electrode 111 is formed in the second opening 110, and a P electrode is formed in the first opening 109 and on the surface of the aluminum oxide layer 108. 112.

作为示例,采用蒸镀工艺在所述第二开口110内形成N电极111,在第一开口109内及所述氧化铝层108表面形成P电极112。As an example, an N electrode 111 is formed in the second opening 110 by an evaporation process, and a P electrode 112 is formed in the first opening 109 and on the surface of the aluminum oxide layer 108 .

作为示例,所述N电极111及所述P电极112的材料可以为Cr、Pt、Ti、Au、Sn中的一种或几种的组合。Cr的厚度为50埃~1000埃,Pt的厚度为200埃~1000埃,Ti的厚度为200埃~1000埃,Au的厚度为2000埃~5000埃,Sn的厚度为200埃~2000埃。As an example, the material of the N electrode 111 and the P electrode 112 may be one or a combination of Cr, Pt, Ti, Au, Sn. The thickness of Cr is 50-1000 angstroms, the thickness of Pt is 200-1000 angstroms, the thickness of Ti is 200-1000 angstroms, the thickness of Au is 2000-5000 angstroms, and the thickness of Sn is 200-2000 angstroms.

本发明还提供一种倒装LED芯片,请参阅图2至图9,所述倒装LED芯片采用上述方案中所述的制备方法制备而得到,所述倒装LED芯片的最终结构如图9所示,所述倒装LED芯片包括:生长衬底100、n型GaN层101、发光层多量子阱102、p型GaN层103、欧姆接触及电流扩展层105、反射层106、反射层保护层107、氧化铝层108、N电极111及P电极112;其中,所述n型GaN层101、所述发光层多量子阱102、所述p型GaN层103、所述欧姆接触及电流扩展层105及所述反射层106由下至上依次叠置于所述生长衬底100的上表面;所述n型GaN层101、所述发光层多量子阱102及所述p型GaN层103内形成有第一深槽104,所述第一深槽104贯穿所述p型GaN层103及所述发光层多量子阱102,且所述第一深槽104的底部位于所述n型GaN层101内;所述欧姆接触及电流扩展层105及所述反射层106内形成有贯通孔,所述贯通孔贯穿所述欧姆接触及电流扩展层105及所述反射层106,且与所述第一深槽104上下对应,且所述贯通孔的横向尺寸大于所述第一深槽104的横向尺寸;所述反射层保护层107位于所述反射层106表面、内侧及所述第一深槽104底部,位于所述第一深槽104底部的所述反射层保护层107与所述第一深槽104的侧壁相隔一定的间距;所述氧化铝层108覆盖所述反射层保护层107并填满所述贯通孔及所述第一深槽104;所述氧化铝层108内形成有第一开口109及第二开口110,所述第一开口109暴露出位于所述反射层106表面的所述反射层保护层107,所述第二开口110暴露出位于所述第一深槽104底部的所述反射层保护层107;所述N电极111位于所述第二开口110内,所述P电极112位于所述第一开口109内及所述氧化铝层108表面。The present invention also provides a flip-chip LED chip, please refer to Figure 2 to Figure 9, the flip-chip LED chip is prepared by the preparation method described in the above scheme, the final structure of the flip-chip LED chip is shown in Figure 9 As shown, the flip-chip LED chip includes: growth substrate 100, n-type GaN layer 101, light-emitting layer multiple quantum wells 102, p-type GaN layer 103, ohmic contact and current spreading layer 105, reflective layer 106, reflective layer protection layer 107, aluminum oxide layer 108, N electrode 111, and P electrode 112; wherein, the n-type GaN layer 101, the light-emitting layer multiple quantum well 102, the p-type GaN layer 103, the ohmic contact and the current spreading layer 105 and the reflective layer 106 are sequentially stacked on the upper surface of the growth substrate 100 from bottom to top; A first deep groove 104 is formed, the first deep groove 104 runs through the p-type GaN layer 103 and the light-emitting layer multiple quantum well 102, and the bottom of the first deep groove 104 is located in the n-type GaN layer 101; a through hole is formed in the ohmic contact and current spreading layer 105 and the reflective layer 106, the through hole runs through the ohmic contact and current spreading layer 105 and the reflective layer 106, and is connected to the first A deep groove 104 corresponds up and down, and the lateral dimension of the through hole is larger than the lateral dimension of the first deep groove 104; the reflective layer protection layer 107 is located on the surface of the reflective layer 106, inside and the first deep groove 104 bottom, the reflective layer protection layer 107 at the bottom of the first deep groove 104 is spaced from the sidewall of the first deep groove 104 by a certain distance; the aluminum oxide layer 108 covers the reflective layer protection layer 107 and fill the through hole and the first deep groove 104; a first opening 109 and a second opening 110 are formed in the aluminum oxide layer 108, and the first opening 109 exposes the The reflective layer protection layer 107, the second opening 110 exposes the reflective layer protection layer 107 at the bottom of the first deep groove 104; the N electrode 111 is located in the second opening 110, the The P-electrode 112 is located in the first opening 109 and on the surface of the aluminum oxide layer 108 .

作为示例,所述氧化铝层108采用原子层沉积法制备而得,所述氧化铝层108的厚度为200埃~5000埃。As an example, the aluminum oxide layer 108 is prepared by an atomic layer deposition method, and the thickness of the aluminum oxide layer 108 is 200 angstroms to 5000 angstroms.

需要说明的是,由于所述氧化铝层108覆盖所述反射层保护层107并填满所述贯通孔及所述第一深槽104,故图9中并未标示出所述贯通孔及所述第一深槽104;同理,由于所述N电极111位于所述第二开口110内,所述P电极112位于所述第一开口109内,图9中并未标示出所述第一开口109及所述第二开口110。It should be noted that, since the aluminum oxide layer 108 covers the reflective layer protection layer 107 and fills the through hole and the first deep groove 104, the through hole and the first deep groove 104 are not marked in FIG. the first deep groove 104; similarly, since the N electrode 111 is located in the second opening 110, and the P electrode 112 is located in the first opening 109, the first opening 109 is not marked in FIG. The opening 109 and the second opening 110 .

综上所述,本发明提供一种倒装LED芯片及其制备方法,所述倒装LED芯片的制备方法包括以下步骤:1)提供生长衬底,在所述生长衬底上依次生长n型GaN层、发光层多量子阱及p型GaN层;2)形成贯穿所述p型GaN层及所述发光层多量子阱的第一深槽,所述第一深槽的底部位于所述n型GaN层内;3)在所述p型GaN层表面形成欧姆接触及电流扩展层,所述欧姆接触及电流扩展层的面积小于所述p型GaN层的面积;4)在所述欧姆接触及电流扩展层表面形成反射层;5)在所述反射层表面、内侧及所述第一深槽底部形成反射层保护层,位于所述第一深槽底部的所述反射层保护层与所述第一深槽的侧壁相隔一定的间距;6)采用原子层沉积法在步骤5)得到的结构表面形成氧化铝层;7)在所述氧化铝层内形成第一开口及第二开口,所述第一开口暴露出位于所述反射层表面的所述反射层保护层,所述第二开口暴露出位于所述第一深槽底部的所述反射层保护层;8)在所述第二开口内形成N电极,在所述第一开口内及所述氧化铝层表面形成P电极。采用ALD(原子层沉积)制备的Al2O3材料是单个原子层逐层沉积,膜层密度高,更加致密,并且不容易受基底形貌的影响,对深宽比大的台阶区域覆盖性好,采用原子层沉积法制备的Al2O3层作为绝缘层和金属阻挡层相对于PECVD沉积的SiO2具有更好的绝缘性能和金属阻挡性能,从而保证倒装芯片在大电流使用下的可靠性能。In summary, the present invention provides a flip-chip LED chip and a preparation method thereof. The preparation method of the flip-chip LED chip includes the following steps: 1) providing a growth substrate, and sequentially growing n-type LED chips on the growth substrate GaN layer, light-emitting layer multiple quantum wells, and p-type GaN layer; 2) forming a first deep groove that runs through the p-type GaN layer and the light-emitting layer multiple quantum wells, and the bottom of the first deep groove is located at the n 3) form an ohmic contact and a current spreading layer on the surface of the p-type GaN layer, the area of the ohmic contact and the current spreading layer is smaller than the area of the p-type GaN layer; 4) in the ohmic contact and the surface of the current spreading layer to form a reflective layer; 5) form a reflective layer protection layer on the surface, inside, and bottom of the first deep groove of the reflective layer, and the reflective layer protective layer at the bottom of the first deep groove and the The sidewalls of the first deep groove are separated by a certain distance; 6) an aluminum oxide layer is formed on the surface of the structure obtained in step 5) by atomic layer deposition; 7) a first opening and a second opening are formed in the aluminum oxide layer , the first opening exposes the reflective layer protection layer on the surface of the reflective layer, and the second opening exposes the reflective layer protection layer at the bottom of the first deep groove; 8) in the An N electrode is formed in the second opening, and a P electrode is formed in the first opening and on the surface of the aluminum oxide layer. The Al 2 O 3 material prepared by ALD (atomic layer deposition) is a single atomic layer deposited layer by layer, the film layer density is high, denser, and not easily affected by the substrate morphology, and the coverage of the step area with a large aspect ratio Well, the Al2O3 layer prepared by atomic layer deposition as the insulating layer and metal barrier layer has better insulating properties and metal barrier properties than SiO2 deposited by PECVD, so as to ensure the flip chip under high current use Reliable performance.

上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (12)

1. A preparation method of a flip LED chip is characterized by comprising the following steps:
1) providing a growth substrate, and sequentially growing an n-type GaN layer, a light-emitting layer multi-quantum well and a p-type GaN layer on the growth substrate;
2) forming a first deep groove penetrating through the p-type GaN layer and the light-emitting layer multi-quantum well, wherein the bottom of the first deep groove is positioned in the n-type GaN layer;
3) forming an ohmic contact and a current spreading layer on the surface of the p-type GaN layer, wherein the area of the ohmic contact and the current spreading layer is smaller than that of the p-type GaN layer;
4) forming a reflecting layer on the surface of the ohmic contact and the current expansion layer;
5) forming a reflective layer protection layer on the surface and the inner side of the reflective layer and at the bottom of the first deep groove, wherein the reflective layer protection layer at the bottom of the first deep groove is separated from the side wall of the first deep groove by a certain distance;
6) forming an aluminum oxide layer on the surface of the structure obtained in the step 5) by adopting an atomic layer deposition method;
7) forming a first opening and a second opening in the aluminum oxide layer, wherein the reflective layer protection layer on the surface of the reflective layer is exposed out of the first opening, and the reflective layer protection layer at the bottom of the first deep groove is exposed out of the second opening;
8) and forming an N electrode in the second opening, and forming a P electrode in the first opening and on the surface of the aluminum oxide layer.
2. The method of manufacturing a flip LED chip of claim 1, wherein: the growth substrate is a sapphire substrate, a GaN substrate, a silicon substrate or a silicon carbide substrate.
3. The method of manufacturing a flip LED chip of claim 1, wherein: the method comprises the following steps that a second deep groove is formed in the structure obtained in the step 1) between the step 1) and the step 2) so as to divide the structure obtained in the step 1) into a plurality of independent chip units, the second deep groove penetrates through the p-type GaN layer, the light-emitting layer multi-quantum well and the n-type GaN layer, and the bottom of the second deep groove is located in the growth substrate.
4. The method of manufacturing a flip LED chip of claim 3, wherein: by BCl3、Cl2And Ar plasma selectively etches the p-type GaN layer, the light-emitting layer multi-quantum well, the n-type GaN layer and the growth substrate to form the second deep groove.
5. The method of manufacturing a flip LED chip of claim 1, wherein: by BCl3、Cl2And selectively etching the p-type GaN layer, the light-emitting layer multi-quantum well and the n-type GaN layer by Ar plasma to form the first deep groove.
6. The method of manufacturing a flip LED chip of claim 1, wherein: and depositing an ITO film on the surface of the p-type GaN layer by utilizing a magnetron sputtering process or a reactive plasma deposition process to serve as the ohmic contact and current expansion layer.
7. The method of manufacturing a flip LED chip of claim 1, wherein: and depositing a ZnO film on the surface of the p-type GaN layer by utilizing a magnetron sputtering process or an MOCVD process to serve as the ohmic contact and current expansion layer.
8. The method of manufacturing a flip LED chip of claim 1, wherein: and forming the reflecting layer on the surfaces of the ohmic contact layer and the current expansion layer by utilizing a magnetron sputtering process, wherein the reflecting layer is made of Ag-TiW or Ag-TiW-Pt.
9. The method of manufacturing a flip LED chip of claim 1, wherein: and forming the reflecting layer protective layer on the surface and the inner side of the reflecting layer and at the bottom of the first deep groove by adopting a magnetron sputtering process or an electron beam vapor evaporation process, wherein the material of the reflecting layer protective layer is one or a combination of more of Cr, Al, TiW, Pt, Ti, Au and Ni.
10. The method of manufacturing a flip LED chip of claim 1, wherein: the aluminum oxide layer coats the reflecting layer protection layer and the exposed reflecting layer, the ohmic contact and current expansion layer, the p-type GaN layer, the light-emitting layer multi-quantum well and the n-type GaN layer, and the thickness of the aluminum oxide layer is 200-5000 angstroms.
11. A flip LED chip, comprising: the LED comprises a growth substrate, an N-type GaN layer, a light-emitting layer multi-quantum well, a P-type GaN layer, an ohmic contact and current expansion layer, a reflecting layer protective layer, an aluminum oxide layer, an N electrode and a P electrode; wherein,
the n-type GaN layer, the light-emitting layer multi-quantum well, the p-type GaN layer, the ohmic contact and current expansion layer and the reflecting layer are sequentially stacked on the upper surface of the growth substrate from bottom to top; a first deep groove is formed in the n-type GaN layer, the light-emitting layer multi-quantum well and the p-type GaN layer, the first deep groove penetrates through the p-type GaN layer and the light-emitting layer multi-quantum well, and the bottom of the first deep groove is located in the n-type GaN layer; through holes are formed in the ohmic contact and current expansion layer and the reflecting layer, the through holes vertically correspond to the first deep grooves, and the transverse dimension of each through hole is larger than that of each first deep groove;
the reflecting layer protection layer is positioned on the surface and the inner side of the reflecting layer and at the bottom of the first deep groove, and the reflecting layer protection layer positioned at the bottom of the first deep groove is separated from the side wall of the first deep groove by a certain distance;
the aluminum oxide layer covers the reflecting layer protection layer and fills the through hole and the first deep groove; a first opening and a second opening are formed in the aluminum oxide layer, the reflective layer protection layer positioned on the surface of the reflective layer is exposed out of the first opening, and the reflective layer protection layer positioned at the bottom of the first deep groove is exposed out of the second opening;
the N electrode is positioned in the second opening, and the P electrode is positioned in the first opening and on the surface of the aluminum oxide layer.
12. The flip LED chip of claim 11, wherein: the aluminum oxide layer is prepared by adopting an atomic layer deposition method, and the thickness of the aluminum oxide layer is 200-5000 angstroms.
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CN113328015A (en) * 2021-06-04 2021-08-31 湘能华磊光电股份有限公司 Method for manufacturing light emitting diode chip with improved brightness
CN113328015B (en) * 2021-06-04 2022-06-03 湘能华磊光电股份有限公司 Method for manufacturing light emitting diode chip with improved brightness
CN114497328A (en) * 2022-01-28 2022-05-13 普瑞(无锡)研发有限公司 High-reliability light-emitting diode structure and packaging body

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