CN115496031A - Design method, device, equipment and medium of chip test carrier plate - Google Patents
Design method, device, equipment and medium of chip test carrier plate Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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Abstract
The invention relates to the field of carrier plate design, in particular to a method, a device, equipment and a medium for designing a chip test carrier plate. The method comprises the following steps: determining a change rule for multiplying the number of the tested chips based on the connection point of the testing machine; calculating the attributes of the welding points respectively corresponding to the different types of connection points of the test machine on the chip test carrier plate according to the change rule, and calculating the corresponding ranges of the probes and the parts on the chip test carrier plate according to the data information of the probes and the parts; and establishing a connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate according to the property of the welding point and the corresponding range of the probe and the part, and generating a line relation file for wiring based on the connection relation. The method of the invention can realize the multiplication of the number of the test chips of the chip test carrier plate, reduce the test time and the cost and obtain greater economic benefit.
Description
Technical Field
The invention relates to the field of carrier plate design, in particular to a method, a device, equipment and a medium for designing a chip test carrier plate.
Background
With the development of the semiconductor industry and the trend of moore's law, the number of Die units on each silicon Wafer (Wafer) is increasing during the semiconductor testing, and compared with the chip testing carrier board of the testing machine, if the number of the testing is not increased, the cost consumed in the testing will also increase by multiple times, so the design of the Wafer-level high-frequency high-speed multi-chip testing carrier board is becoming more and more important. In the prior art, because the number of available lines of a test machine (Tester) is limited, a chip test carrier can only reach 4X8DUT or 2X16DUT. How to realize the number multiplication of the test chips of the chip test carrier plate on the premise of limiting the parameter specification of the test machine and not changing the thickness of the carrier plate so as to reduce the production cost and obtain greater economic benefit is a problem in the prior art.
Disclosure of Invention
In view of this, the invention provides a method, an apparatus, a device and a medium for designing a chip test carrier. The design method of the chip test carrier plate provided by the invention is characterized in that within the range of not increasing the number of the carrier plate stack layers and the process capability of the carrier plate, the number of the test chips of the chip test carrier plate is multiplied by applying the limited parameter specification of the test machine, not changing the thickness of the carrier plate, increasing the limited stack layers and matching with impedance control.
In view of the above, an aspect of the embodiments of the present invention provides a method for designing a chip test carrier, where the method includes the following steps: determining a change rule for multiplying the number of the tested chips based on the connection point of the testing machine; calculating the attributes of the welding points respectively corresponding to the different types of connection points of the test machine on the chip test carrier plate according to the change rule, and calculating the corresponding ranges of the probe and the part on the chip test carrier plate according to the data information of the probe and the part; and establishing a connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate according to the attributes of the welding point and the corresponding range of the probe and the part, and generating a line relation file for wiring based on the connection relation.
In some embodiments, the determining a variation rule for multiplying the number of chips under test based on the connection point of the test bench includes: and setting an addressing connection point shared by adjacent tested chips and setting an input/output connection point as two blocks based on the connection point of the test machine.
In some embodiments, the determining the variation rule for multiplying the number of the tested chips based on the connection points of the testing machine further includes: the unused addressing connection point and the unused input-output connection point are set as connection points for testing the results.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding welding points on the chip test carrier of different types of connection points of the test machine, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier include: and respectively calculating the sizes of the corresponding welding points of the addressing connection point and the input and output connection point of the test machine on the chip test carrier plate.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding solder joints of different types of connection points of the test machine on the chip test carrier, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier include: the method comprises the steps of obtaining the pin position quantity and the attributes of parts including connection points of capacitors and connection points of relays, and setting the size of welding points corresponding to the connection points of the capacitors and the size of the welding points corresponding to the connection points of the relays.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding solder joints of different types of connection points of the test machine on the chip test carrier, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier further include: and acquiring the length and the number of layers of the probes, and arranging the probes in a range corresponding to the needle tips of the probes according to the length and the number of layers of the probes to obtain the corresponding positions of the probes on the chip test carrier plate.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding solder joints of different types of connection points of the test machine on the chip test carrier, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier further include: setting the range corresponding to the part on the chip test carrier plate to be not more than the range corresponding to the preset radius of the chip test carrier plate by taking the center as the reference; and setting the range corresponding to the needle point of the probe on the chip test carrier plate to be not more than the range corresponding to the part.
In some embodiments, the calculating the sizes of the corresponding bonding pads of the addressing connection point and the input/output connection point of the test machine on the chip test carrier respectively includes: by providing resistors at the addressing connection points as barriers to distinguish adjacent chips under test, and by not providing resistors at the input-output connection points, and calculating the sizes of the welding points respectively corresponding to the addressing connection point and the input/output connection point on the chip test carrier plate.
In some embodiments, the calculating the sizes of the corresponding bonding pads of the addressing connection point and the input/output connection point of the test machine on the chip test carrier respectively further includes: and setting the size of a copper pad of the welding point based on the attribute of the addressing connection point, the attribute of the input/output connection point, the thickness of the chip test carrier plate, the proportion of the through hole and the diameter of the probe.
In some embodiments, the establishing a connection relationship between a connection point of the test machine and a solder point of the chip test carrier according to the property of the solder point and a range corresponding to the probe and the component, and generating a line relationship file for routing based on the connection relationship includes: arranging the parts and the probes in the ranges corresponding to the parts and the probes respectively to obtain the positions of the parts and the probes on the chip test carrier plate; and establishing a connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate, and generating a line relation grade for wiring based on the connection relation.
In some embodiments, the establishing a connection relationship between a connection point of the test machine and a solder joint of the chip test carrier, and generating a line relationship file for routing based on the connection relationship includes: and calculating the pitch of the welding points and the routing rule in the pitch, and routing according to the pitch of the welding points and the routing rule.
In some embodiments, the calculating the pitch of the solder joints and the routable rule in the pitch, the routing according to the pitch of the solder joints and the routable rule comprising: and calculating the space of the welding points and the wire width and the wire distance which can be wired in the space according to the connection relation, the positions and the sizes of the welding points and the positions and the ranges corresponding to the probes and the parts, and wiring according to the space of the welding points and the wire width and the wire distance which can be wired in the space.
In another aspect of the embodiments of the present invention, a device for designing a chip test carrier is further provided, where the device includes: the first module is configured to determine a change rule for multiplying the number of the chips to be tested based on the connection point of the test machine; the second module is configured to calculate the attributes of the welding points respectively corresponding to the different types of connection points of the test machine on the chip test carrier plate according to the change rule, and calculate the ranges respectively corresponding to the probes and the parts on the chip test carrier plate according to the data information of the probes and the parts; and the third module is configured to establish a connection relation between the connection point of the test machine and the welding point of the chip test carrier plate according to the property of the welding point and the range corresponding to the probe and the part, and generate a line relation file for wiring based on the connection relation.
In some embodiments, the first module is further configured to set the adjacent chips under test to share one addressing connection point and set the input/output connection points as two blocks based on the connection point of the testing machine.
In some embodiments, the first module is further configured to set the unused addressing connection point and the unused input-output connection point as the connection points for testing the result.
In some embodiments, the second module is further configured to calculate sizes of corresponding solder joints of the addressing connection point and the input/output connection point of the test machine on the chip test carrier respectively.
In some embodiments, the second module is further configured to obtain the pin position number and attributes of the part including the connection point of the capacitor and the connection point of the relay, so as to set the size of the welding point corresponding to the connection point of the capacitor and the size of the welding point corresponding to the connection point of the relay.
In some embodiments, the second module is further configured to obtain the length and the number of layers of the probes, and arrange the probes in a range corresponding to the tips of the probes according to the length and the number of layers of the probes to obtain corresponding positions of the probes on the chip test carrier plate.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any of the methods described above.
In another aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing any one of the above method steps is stored when the computer program is executed by a processor.
The invention has at least the following beneficial effects: the invention provides a design method, a device, equipment and a medium of a chip test carrier plate. According to the design method of the chip test carrier plate, the number of welding points is multiplied in the process of multiplying the number of test chips of the chip test carrier plate through the limited parameter specification of the test machine and on the premise of not multiplying the thickness of the carrier plate, the number of the test chips of the chip test carrier plate is multiplied through setting the corresponding wiring rule and impedance control, the test time and the cost are reduced, and the greater economic benefit is obtained.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram illustrating an embodiment of a method for designing a chip test carrier according to the present invention;
FIG. 2 is a schematic diagram illustrating an appearance of a chip test carrier according to the present invention;
FIG. 3 is a design flowchart of a circuit diagram of a chip test carrier according to the present invention;
FIG. 4 is a schematic diagram of a range of parts and a range of probes on a chip test carrier according to the present invention;
fig. 5 is a schematic diagram illustrating an embodiment of a device for designing a chip test carrier according to the present invention;
FIG. 6 is a schematic diagram of one embodiment of a computer device;
fig. 7 is a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention.
Detailed Description
Embodiments of the present invention are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms.
In addition, it should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are only used for convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and they are not described in any further embodiments. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
One or more embodiments of the present application will be described below with reference to the accompanying drawings.
In view of the above, a first aspect of the embodiments of the present invention provides an embodiment of a method for designing a chip test carrier. Fig. 1 is a schematic diagram illustrating an embodiment of a method for designing a chip test carrier according to the present invention. As shown in fig. 1, a method for designing a chip test carrier according to an embodiment of the present invention includes the following steps:
s1, determining a change rule for multiplying the number of tested chips based on a connection point of a test machine;
s2, calculating the attributes of the welding points respectively corresponding to the different types of connection points of the test machine on the chip test carrier plate according to the change rule, and calculating the corresponding ranges of the probes and the parts on the chip test carrier plate according to the data information of the probes and the parts;
and S3, establishing a connection relation between a connection point of the test machine platform and the welding point of the chip test carrier plate according to the attributes of the welding point and the corresponding range of the probe and the part, and generating a line relation file for wiring based on the connection relation.
In view of the above, in a first aspect of the embodiments of the present invention, another embodiment of a method for designing a chip test carrier is further provided. As shown in fig. 2, which is a schematic diagram illustrating an exterior of the chip test carrier according to the present embodiment, in this embodiment, a diameter of a size of the carrier is 12 inches (304.8 mm), a thickness of the carrier is 0.189 inches, and 64 ZIF connector contacts used in the carrier are divided into eight blocks. Each block consists of 8 ZIF connector contacts, the number of the test chips of the carrier plate is 32DUT, and the number of the test chips of the chip test carrier plate is designed to be doubled on the basis of the carrier plate, namely the chip test carrier plate is 64DUT. Wherein the connection points of the zones of the carrier plate comprise: power output connection points (Power), input/output connection points (I/O), addressing connection points (Address), control connection points (Control Pin), on-board machine function connection points (Enable Pin), and the like. The number, arrangement and size of DUTs of the carrier board depend on the size requirement of the tested chip. As the process capability of the wafer is gradually improved, the moore's law indicates that the size of the die is gradually reduced, so that the number of chips to be tested is gradually increased, and the number of arrays is also increased by a multiplication, so as to meet the testing efficiency of the testing machine.
The design principle of the 4X8DUT and the 2X16DUT is the same, and the difference is in the arrangement mode. And obtaining the lengths of the connection welding points on the chip test carrier plate and the test points of the tested chip according to the lengths of the cantilever type probes and the number of the probe layers, so as to design the chip test carrier plate. In this embodiment, the chip test carrier is designed in a standard mode of the test machine according to all available lines of the test machine, the input/output contacts and the addressing contacts are shared between two adjacent DUTs, the input/output contacts are divided into two blocks, and the unshared contacts are used as a judgment for the quality of the test result to achieve the best test effect.
As shown in fig. 3, a flow chart of a circuit diagram of a chip test carrier board according to the present embodiment is provided, specifically,
(1) Establishing parts: the shapes of the components and the pins of the connection points are defined, such as the number and the attributes of the pins of the connection Points (POGO) used by a tester, the number and the attributes of the pins of the connection points of a DUT, the number and the attributes of the pins of the connection points of a relay, the number and the attributes of the pins of the connection points of a capacitor, and the like.
(2) Establishing a line connection relation: according to the requirements of a user of the chip test carrier plate, the connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate is established.
(3) Generating a connection relation file: and generating a line relation File (Netlist File) by utilizing the established connection relation.
Fig. 4 is a schematic diagram of a part range and a probe range on a chip test carrier according to the present invention, wherein a circular area is the part range, and a rectangular area is the probe range. According to the originally designed mechanism condition of the tester, when the chip test carrier is designed, the component placement area is limited within a range of a preset radius based on the center, and if the range is exceeded, the chip test carrier interferes with the mechanism of the tester. Similarly, the user calculates the range of the probe tip of the chip test carrier according to the size of the tested chip, the arrangement of the tested chips (4 × 16 DUT) and the size of the probe holder, and designs the range according to the range of the probe tip, and the range of the probe tip may not exceed the range of the component placement area.
For the arrangement of the welding points, the input and output connection points are independently used by each tested chip, the addressing connection points are shared by the adjacent tested chips, so that the input and output part and the addressing part need to be distinguished, and each addressing connection point is provided with a resistor to be used as a barrier for distinguishing the connected tested chips. In each block of the tested chip, the sizes of the welding points corresponding to the input/output connection points and the addressing connection points are set by sharing or not sharing. A resistor needs to be bridged at a welding point corresponding to the addressing connection point, so the processing needs to consider the proportional relation between the thickness of the chip test carrier plate and the through hole, and also needs to consider the diameter of the probe. And for the consistency of the arrangement size of the welding points of the input and output connection points, setting the width of the welding points to be the same as that of the welding points corresponding to the addressing connection points. For the spot-welded joints corresponding to the capacitor connections, as with the probe-welded joints, it is also considered that the number of capacitors increases as the number of DUTs increases, and therefore the size of the capacitors must be relatively reduced. For the welding points corresponding to the relay connecting points, the specifications of the relays are unique, so that the sizes of the original specifications cannot be reduced.
And arranging and setting the relevant position of each DUT welding point according to the requirement of the DUT line connecting point, and sequentially setting the relevant position of each DUT on the chip test carrier plate. The purpose of this setting is to use the specific position as the origin, and lock the placement position of each DUT after it is placed at the fixed point, so as to avoid the error of displacement of DUT or other parts caused by carelessly moving the relevant position of each DUT. And the addressing connection point resistor, capacitor and relay are organized into parts in sequence. The organized parts are stored in a part database in sequence, and then a connection relation file generated according to a drawn line diagram is loaded into P-CAD software and is arranged in sequence according to the relevant positions of all the parts.
Since the line width of the signal line affects the impedance control and board thickness of the chip test carrier board, the line width of the signal line, i.e. the line width of the input/output and addressing connection line, is set before the wiring is started. To be set respectively include: the distance between the copper pad (including the copper pad with the drilled hole) and the signal line, the distance between the signal line and the through hole copper pad, the distance between the adjacent signal lines, and the wiring rules of the power supply source end, the induction end and the relay connection point.
The chip test carrier plate needs to consider impedance control, and aims to be matched with impedance control of a test machine table to achieve better signal transmission efficiency. Therefore, when considering the impedance control, the necessary conditions are the line width and the plate material, and the material of the plate material used also affects the magnitude of the impedance control value. The board used in the chip test carrier was FR-4, and the copper foil coated on the FR-4 board had a thickness of 1 ounce. The method is used as the basis of impedance control of each layer, the line width of the wiring circuit and the corresponding large-area copper foil distance are calculated by using software for calculating impedance, and the chip test carrier plate is marked according to the required specification of a test machine.
In a second aspect of the embodiments of the present invention, an apparatus for designing a chip test carrier is provided. Fig. 5 is a schematic diagram illustrating an embodiment of a device for designing a chip test carrier according to the present invention. As shown in fig. 5, the apparatus for designing a chip test carrier according to the present invention includes: a first module 011 configured to determine a variation rule for multiplying the number of chips under test based on a connection point of a test bench; the second module 012 is configured to calculate, according to the change rule, attributes of respective corresponding welding points on the chip test carrier of different types of connection points of the test machine, and calculate, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier; and a third module 013 configured to establish a connection relationship between the connection point of the test machine and the bonding point of the chip test carrier according to the property of the bonding point and the range corresponding to the probe and the part, and generate a line relationship file for wiring based on the connection relationship.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, and fig. 6 is a schematic diagram illustrating an embodiment of a computer device provided by the present invention. As shown in fig. 6, an embodiment of a computer device provided by the present invention includes the following modules: at least one processor 021; and a memory 022, the memory 022 storing computer instructions 023 executable on the processor 021, the computer instructions 023, when executed by the processor 021, implementing the steps of the method described above.
The invention also provides a computer readable storage medium. FIG. 7 is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 7, the computer readable storage medium 031 stores a computer program 032 which, when executed by a processor, performs the method as described above. The method that can be executed by computer program 032 includes: determining a change rule for multiplying the number of the tested chips based on the connection point of the testing machine; calculating the attributes of the welding points respectively corresponding to the different types of connection points of the test machine on the chip test carrier plate according to the change rule, and calculating the corresponding ranges of the probe and the part on the chip test carrier plate according to the data information of the probe and the part; and establishing a connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate according to the property of the welding point and the corresponding range of the probe and the part, and generating a line relation file for wiring based on the connection relation.
In some embodiments, the determining the variation rule for multiplying the number of the tested chips based on the connection points of the testing machine includes: and setting an addressing connection point shared by adjacent tested chips and setting an input/output connection point as two blocks based on the connection point of the test machine.
In some embodiments, the determining a variation rule for multiplying the number of chips under test based on the connection point of the test bench further includes: the unused addressing connection point and the unused input-output connection point are set as connection points for testing the results.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding solder joints of different types of connection points of the test machine on the chip test carrier, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier include: and respectively calculating the sizes of the corresponding welding points of the addressing connection point and the input/output connection point of the test machine on the chip test carrier plate.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding solder joints of different types of connection points of the test machine on the chip test carrier, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier include: the method comprises the steps of obtaining the pin position quantity and the attributes of parts including connection points of capacitors and connection points of relays, and setting the size of welding points corresponding to the connection points of the capacitors and the size of the welding points corresponding to the connection points of the relays.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding solder joints of different types of connection points of the test machine on the chip test carrier, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier further include: and acquiring the length and the number of layers of the probes, and arranging the probes in a range corresponding to the needle tips of the probes according to the length and the number of layers of the probes to obtain the corresponding positions of the probes on the chip test carrier plate.
In some embodiments, the calculating, according to the change rule, attributes of respective corresponding solder joints of different types of connection points of the test machine on the chip test carrier, and calculating, according to data information of the probe and the part, respective corresponding ranges of the probe and the part on the chip test carrier further include: setting the range corresponding to the part on the chip test carrier plate to be not more than the range corresponding to the preset radius of the chip test carrier plate by taking the center as the reference; and setting the range corresponding to the needle point of the probe on the chip test carrier plate to be not more than the range corresponding to the part.
In some embodiments, the calculating the sizes of the corresponding bonding pads of the addressing connection point and the input/output connection point of the test machine on the chip test carrier respectively includes: the resistors are arranged at the addressing connection points to be used as barriers for distinguishing adjacent tested chips, and the resistors are not arranged at the input and output connection points, so that the sizes of the welding points respectively corresponding to the addressing connection points and the input and output connection points on the chip test carrier plate are calculated.
In some embodiments, the calculating the sizes of the corresponding bonding pads of the addressing connection point and the input/output connection point of the test machine on the chip test carrier respectively further includes: and setting the size of a copper pad of the welding point based on the attribute of the addressing connection point, the attribute of the input/output connection point, the thickness of the chip test carrier plate, the proportion of the through hole and the diameter of the probe.
In some embodiments, the establishing a connection relationship between a connection point of the test machine and a solder point of the chip test carrier according to the property of the solder point and the corresponding range of the probe and the component, and generating a line relationship file for routing based on the connection relationship includes: arranging the parts and the probes in the ranges corresponding to the parts and the probes respectively to obtain the positions of the parts and the probes on the chip test carrier plate; and establishing a connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate, and generating a line relation grade for wiring based on the connection relation.
In some embodiments, the establishing a connection relationship between a connection point of the test machine and a solder joint of the chip test carrier, and generating a line relationship file for routing based on the connection relationship includes: and calculating the pitch of the welding points and the rules of routable in the pitch, and routing according to the pitch of the welding points and the rules of routable.
In some embodiments, the calculating the pitch of the solder joints and the routable rule in the pitch, the routing according to the pitch of the solder joints and the routable rule comprising: and calculating the space of the welding points and the wire width and the wire distance which can be wired in the space according to the connection relation, the positions and the sizes of the welding points and the positions and the ranges corresponding to the probes and the parts, and wiring according to the space of the welding points and the wire width and the wire distance which can be wired in the space.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for setting system parameters can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, D0L, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the above embodiments of the present invention are merely for description, and do not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also combinations between technical features in the above embodiments or in different embodiments are possible, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (20)
1. A method for designing a chip test carrier plate is characterized by comprising the following steps:
determining a change rule for multiplying the number of the tested chips based on the connection point of the testing machine;
calculating the attributes of the welding points respectively corresponding to the different types of connection points of the test machine on the chip test carrier plate according to the change rule, and calculating the corresponding ranges of the probe and the part on the chip test carrier plate according to the data information of the probe and the part;
and establishing a connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate according to the property of the welding point and the corresponding range of the probe and the part, and generating a line relation file for wiring based on the connection relation.
2. The method of claim 1, wherein determining a variation rule for multiplying the number of chips under test based on the connection point of the test bench comprises:
and setting an addressing connection point shared by adjacent tested chips and setting an input/output connection point as two blocks based on the connection point of the test machine.
3. The method of claim 2, wherein determining the variation rule for multiplying the number of chips under test based on the connection point of the test bench further comprises:
the unused addressing connection point and the unused input-output connection point are set as connection points for testing the results.
4. The method of claim 2, wherein the calculating, according to the variation rule, the attributes of the pads respectively corresponding to the different types of connection points of the test machine on the chip test carrier, and the calculating, according to the data information of the probe and the part, the ranges respectively corresponding to the probe and the part on the chip test carrier include:
and respectively calculating the sizes of the corresponding welding points of the addressing connection point and the input/output connection point of the test machine on the chip test carrier plate.
5. The method of claim 2, wherein the calculating, according to the variation rule, the attributes of the pads respectively corresponding to the different types of connection points of the test machine on the chip test carrier, and the calculating, according to the data information of the probe and the part, the ranges respectively corresponding to the probe and the part on the chip test carrier include:
the method comprises the steps of obtaining the pin position quantity and the attributes of parts including connection points of capacitors and connection points of relays, and setting the size of welding points corresponding to the connection points of the capacitors and the size of the welding points corresponding to the connection points of the relays.
6. The method of claim 2, wherein the calculating, according to the variation rule, the attributes of the pads respectively corresponding to the different types of connection points of the test machine on the chip test carrier, and the calculating, according to the data information of the probe and the part, the ranges respectively corresponding to the probe and the part on the chip test carrier further comprises:
and acquiring the length and the number of layers of the probes, and arranging the probes in a range corresponding to the needle tips of the probes according to the length and the number of layers of the probes to obtain the corresponding positions of the probes on the chip test carrier plate.
7. The method of claim 2, wherein the calculating, according to the variation rule, the attributes of the pads respectively corresponding to the different types of connection points of the test machine on the chip test carrier, and the calculating, according to the data information of the probe and the part, the ranges respectively corresponding to the probe and the part on the chip test carrier further comprises:
setting the range corresponding to the part on the chip test carrier plate to be not more than the range corresponding to the preset radius of the chip test carrier plate by taking the center as the reference;
and setting the range corresponding to the needle point of the probe on the chip test carrier plate to be not more than the range corresponding to the part.
8. The method of claim 4, wherein the calculating the sizes of the bonding pads of the addressing connection point and the I/O connection point of the testing machine on the chip testing carrier respectively comprises:
and setting resistors at the addressing connection points to be used as barriers for distinguishing adjacent tested chips, and not setting resistors at the input and output connection points to calculate the sizes of the welding points respectively corresponding to the addressing connection points and the input and output connection points on the chip test carrier plate.
9. The method of claim 4, wherein the calculating the sizes of the bonding pads of the addressing connection point and the I/O connection point of the testing machine on the chip testing carrier respectively further comprises:
and setting the size of a copper pad of the welding point based on the attribute of the addressing connection point, the attribute of the input/output connection point, the thickness of the chip test carrier plate, the proportion of the through hole and the diameter of the probe.
10. The method of claim 1, wherein the establishing a connection relationship between the connection point of the test machine and the bonding point of the chip test carrier according to the property of the bonding point and the corresponding range of the probe and the component, and generating a line relationship file for routing based on the connection relationship comprises:
arranging the parts and the probes in the ranges corresponding to the parts and the probes respectively to obtain the positions of the parts and the probes on the chip test carrier plate;
and establishing a connection relation between the connection point of the test machine platform and the welding point of the chip test carrier plate, and generating a line relation grade for wiring based on the connection relation.
11. The method of claim 10, wherein the establishing a connection relationship between the connection point of the test machine and the bonding pad of the chip test carrier, and generating a line relationship file for routing based on the connection relationship comprises:
and calculating the pitch of the welding points and the rules of routable in the pitch, and routing according to the pitch of the welding points and the rules of routable.
12. The method of claim 11, wherein the calculating the pitch of the solder joints and the routable rule in the pitch, and wherein routing according to the pitch of the solder joints and the routable rule comprises:
and calculating the space of the welding points and the wire width and the wire distance which can be wired in the space according to the connection relation, the positions and the sizes of the welding points and the positions and the ranges corresponding to the probes and the parts, and wiring according to the space of the welding points and the wire width and the wire distance which can be wired in the space.
13. A design device of a chip test carrier plate is characterized by comprising:
the first module is configured to determine a change rule for multiplying the number of the chips to be tested based on the connection point of the test machine;
the second module is configured to calculate the attributes of the welding points respectively corresponding to the different types of connection points of the test machine on the chip test carrier plate according to the change rule, and calculate the ranges respectively corresponding to the probes and the parts on the chip test carrier plate according to the data information of the probes and the parts; and
and the third module is configured to establish a connection relation between the connection point of the test machine and the welding point of the chip test carrier plate according to the property of the welding point and the range corresponding to the probe and the part, and generate a line relation file for wiring based on the connection relation.
14. The apparatus of claim 13, wherein the first module is further configured to:
and setting an addressing connection point shared by adjacent tested chips and setting an input/output connection point as two blocks based on the connection point of the test machine.
15. The apparatus of claim 14, wherein the first module is further configured for:
the unused addressing connection point and the unused input-output connection point are set as connection points for testing the results.
16. The apparatus of claim 14, wherein the second module is further configured for:
and respectively calculating the sizes of the corresponding welding points of the addressing connection point and the input and output connection point of the test machine on the chip test carrier plate.
17. The apparatus of claim 14, wherein the second module is further configured for:
the method comprises the steps of obtaining the pin position quantity and the attributes of parts including connection points of capacitors and connection points of relays, and setting the size of welding points corresponding to the connection points of the capacitors and the size of the welding points corresponding to the connection points of the relays.
18. The apparatus of claim 14, wherein the second module is further configured for:
and acquiring the length and the number of layers of the probes, and arranging the probes in a range corresponding to the needle tips of the probes according to the length and the number of layers of the probes to obtain the corresponding positions of the probes on the chip test carrier plate.
19. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 12.
20. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 12.
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| CN202211426658.XA CN115496031B (en) | 2022-11-15 | 2022-11-15 | Design method, device, equipment and medium of chip test carrier plate |
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| CN102831471A (en) * | 2011-06-16 | 2012-12-19 | 王海泉 | Novel packaging method for contact smart cards |
| CN113514475A (en) * | 2021-06-25 | 2021-10-19 | 深圳格芯集成电路装备有限公司 | Method for generating reference template for chip detection and related equipment |
| CN114075687A (en) * | 2020-08-21 | 2022-02-22 | 盛合晶微半导体(江阴)有限公司 | Electroplating carrier and electroplating method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1694601A (en) * | 2005-05-26 | 2005-11-09 | 倚天资讯股份有限公司 | Electronic component assembly device inside electronic equipment |
| CN102831471A (en) * | 2011-06-16 | 2012-12-19 | 王海泉 | Novel packaging method for contact smart cards |
| CN114075687A (en) * | 2020-08-21 | 2022-02-22 | 盛合晶微半导体(江阴)有限公司 | Electroplating carrier and electroplating method |
| CN113514475A (en) * | 2021-06-25 | 2021-10-19 | 深圳格芯集成电路装备有限公司 | Method for generating reference template for chip detection and related equipment |
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