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JP2020128881A - Short circuit inspection system, and short circuit inspection method - Google Patents

Short circuit inspection system, and short circuit inspection method Download PDF

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JP2020128881A
JP2020128881A JP2019020464A JP2019020464A JP2020128881A JP 2020128881 A JP2020128881 A JP 2020128881A JP 2019020464 A JP2019020464 A JP 2019020464A JP 2019020464 A JP2019020464 A JP 2019020464A JP 2020128881 A JP2020128881 A JP 2020128881A
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wirings
pair
wiring
short circuit
voltage
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山下 宗寛
Munehiro Yamashita
宗寛 山下
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Nidec Advance Technology Corp
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Nidec Read Corp
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Priority to TW109100251A priority patent/TW202040155A/en
Priority to KR1020200010306A priority patent/KR20200097202A/en
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52Testing for short-circuits, leakage current or ground faults
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/55Testing for incorrect line connections

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

To provide a short circuit inspection system and a short circuit inspection method, which are capable of easily inspecting an inspection object including a plurality of wirings and a conductive portion which electrically connects one ends of the respective wirings.SOLUTION: A short circuit inspection device 1 is the short circuit inspection device 1 for inspecting an inspection object A including four or more wirings L and a conductive layer 102 for electrically connecting one end of each wiring L to each other. The short circuit inspection device includes: a current supply unit 3 that causes current I to flow between pads P1 and P2 of a pair of first wirings G1 among the four or more wirings L; a voltage detection unit 4 for detecting the voltage V between pads P3 and P4 of a pair of second wirings G2 including a wiring L different from the pair of first wirings and adjacent to at least one of the pair of first wirings G1; and an inspection processing unit 52 that determines a defect if the voltage V detected by the voltage detection unit 4 is not substantially zero.SELECTED DRAWING: Figure 1

Description

本発明は、配線間の短絡を検査するための短絡検査システム、及び短絡検査方法に関する。 The present invention relates to a short circuit inspection system and a short circuit inspection method for inspecting a short circuit between wirings.

従来より、幹配線から枝状に引き出された複数の配線相互間の短絡不良の有無を検査する検査方法が知られている(例えば、特許文献1参照。)。 2. Description of the Related Art Conventionally, there is known an inspection method for inspecting the presence or absence of a short circuit defect between a plurality of wirings that are led out from a trunk wiring in a branch shape (see, for example, Patent Document 1).

特許文献1に記載の検査方法は、幹配線と同幹配線から枝状に引き出されている複数の枝配線とを含み、上記枝配線の各々に2つのランドが設けられている回路配線を検査対象とし、上記各枝配線の上記2つのランド間の断線の有無および隣接する2つの上記枝配線のうちの一方の枝配線側の2つのランド間と他方の枝配線側の2つのランド間との間の短絡の有無をそれぞれ検査する回路配線検査方法において、信号出力検出部を含む検査信号発生手段と検査信号検出手段とを備え、上記検査信号発生手段を上記一方の枝配線側の2つのランド間に接続して信号発生状態にするとともに、上記検査信号検出手段を上記他方の枝配線側の2つのランド間に接続し、上記信号出力検出部にて上記検査信号発生手段から上記一方の枝配線側の2つのランド間に供給される検査信号が検出されないときには上記一方の枝配線側の2つのランド間に断線有りと判定し、上記検査信号検出手段により上記他方の枝配線側の2つのランド間で上記検査信号が検出された場合には上記他方の枝配線側の2つのランド間と上記一方の枝配線側の2つのランド間との間に短絡有りと判定する。 The inspection method described in Patent Document 1 inspects a circuit wiring including a trunk wiring and a plurality of branch wirings branched from the trunk wiring, and two lands are provided in each of the branch wirings. The presence or absence of a disconnection between the two lands of each of the branch wirings, between two lands on one branch wiring side of two adjacent branch wirings, and between two lands on the other branch wiring side. In a circuit wiring inspection method for inspecting each for the presence or absence of a short circuit between them, an inspection signal generation means including a signal output detection portion and an inspection signal detection means are provided, and the inspection signal generation means is provided on the one branch wiring side. The test signal detecting means is connected between the two lands on the side of the other branch wiring, and the signal output detecting section connects the test signal generating means to the one of the one side. When the inspection signal supplied between the two lands on the side of the branch wiring is not detected, it is determined that there is a disconnection between the two lands on the side of the one branch wiring, and the inspection signal detecting means detects the 2 on the side of the other branch wiring. When the inspection signal is detected between two lands, it is determined that there is a short circuit between the two lands on the other branch wiring side and the two lands on the one branch wiring side.

特開2005−300240Japanese Patent Laid-Open No. 2005-300240

従来より、ICダイからのファンアウト配線を行う手法として、フリップチップCSP(Chip Size Package)が用いられ、近年、ファンアウトウェハレベルパッケージ(FOWLP:Fan-Out Wafer Level Package)が主流となっている。ファンアウトウェハレベルパッケージの製造方法には、チップファースト(Chip Fast)とチップラスト(Chip Last)の工法があり、当初はチップファーストの工法が用いられていた。 Conventionally, a flip-chip CSP (Chip Size Package) has been used as a method for performing fan-out wiring from an IC die, and in recent years, a fan-out wafer level package (FOWLP) has become mainstream. .. The fan-out wafer level package manufacturing method includes a chip first method and a chip last method, and the chip first method was initially used.

チップファーストの工法では、良品のICダイに再配置配線層(RDL:Re Distribution Layer)を積み上げるため、再配置配線層に不良が発生すると、良品のICダイを含めて不良となってしまう。そのため、不良発生時の損害額が大きくなり、生産性を上げることが難しい。 In the chip-first method, a redistribution wiring layer (RDL: Redistribution Layer) is stacked on a non-defective IC die. Therefore, when a defect occurs in the redistribution wiring layer, the non-defective IC die is defective. Therefore, the amount of damage when a defect occurs becomes large, and it is difficult to improve productivity.

そのため、再配置配線層が良品であることを確認した後にICダイを実装するチップラスト工法が注目されている。チップラスト工法では、まず、ガラス基板等の絶縁基板101の表面に、銅等の導電層102が形成され、キャリア100が作成される(図8(a))。 Therefore, the chip last method of mounting the IC die after confirming that the rearrangement wiring layer is a good product is drawing attention. In the chip last method, first, a conductive layer 102 made of copper or the like is formed on the surface of an insulating substrate 101 such as a glass substrate to make a carrier 100 (FIG. 8A).

次に、キャリア100の導電層102の上に、メッキプロセス等によって再配置配線層103が形成される(図8(b))。再配置配線層103には、再配置配線層103を貫通する複数の配線L1〜L8が形成される(配線L1〜L4は図示省略)。配線L1〜L8は、その一端が導電層102とつながっている。配線L1〜L8の一端は、後の工程、例えば基板実装工程等においてキャリア100が剥離されることによって露出し、半導体デバイスの外部端子となる。配線L1〜L8の他端は、再配置配線層103の上面に露出してパッドP1〜P8となる。 Next, the rearrangement wiring layer 103 is formed on the conductive layer 102 of the carrier 100 by a plating process or the like (FIG. 8B). In the rearrangement wiring layer 103, a plurality of wirings L1 to L8 penetrating the rearrangement wiring layer 103 are formed (the wirings L1 to L4 are not shown). One end of each of the wirings L1 to L8 is connected to the conductive layer 102. One end of each of the wirings L1 to L8 is exposed by peeling the carrier 100 in a later step, for example, a board mounting step, and becomes an external terminal of the semiconductor device. The other ends of the wirings L1 to L8 are exposed on the upper surface of the rearrangement wiring layer 103 and serve as pads P1 to P8.

図8(b)、図8(c)では、パッドP5〜P8の位置で切断した断面を示している。以下、配線L1〜L8を総称して配線Lと称し、パッドP1〜P8を総称してパッドPと称する。 8B and 8C show cross sections taken at the positions of the pads P5 to P8. Hereinafter, the wirings L1 to L8 are collectively referred to as the wiring L, and the pads P1 to P8 are collectively referred to as the pad P.

次に、再配置配線層103の上面に、ICダイ106が実装される(図8(c))。パッドPは、ICダイ106下面の端子と接続される。 Next, the IC die 106 is mounted on the upper surface of the rearrangement wiring layer 103 (FIG. 8C). The pad P is connected to the terminal on the lower surface of the IC die 106.

上述したように、チップラスト工法では、再配置配線層103が良品であることを確認した後にICダイ106を実装する。従って、ICダイ106が実装される前の図8(b)の段階で、検査を行う必要がある。ここで、図8(b)の段階における、キャリア100に再配置配線層103が形成された検査対象物Aは、複数の配線Lと、配線Lの一端を互いに導通させる導電層102とを備えており、導電層102から複数の配線Lが枝状に引き出されている。 As described above, in the chip last method, the IC die 106 is mounted after confirming that the rearrangement wiring layer 103 is a good product. Therefore, it is necessary to perform the inspection at the stage of FIG. 8B before the IC die 106 is mounted. Here, in the stage of FIG. 8B, the inspection object A in which the rearranged wiring layer 103 is formed on the carrier 100 includes a plurality of wirings L and a conductive layer 102 that electrically connects one ends of the wirings L to each other. Thus, the plurality of wirings L are drawn out from the conductive layer 102 in a branch shape.

この複数の配線L相互間で短絡が生じていないかどうかの短絡検査を行う必要がある。しかしながら、上述の特許文献1に記載の検査方法は、枝配線の各々に2つのランドが設けられている回路配線でなければ検査できないのに対し、検査対象物Aは、一つの配線Lに対して露出している部分がパッドPしか存在しない。そのため、上述の特許文献1に記載の検査方法では、検査対象物Aの検査を行うことができない。 It is necessary to perform a short-circuit inspection whether or not a short circuit has occurred between the plurality of wiring lines L. However, the inspection method described in the above-mentioned Patent Document 1 can be inspected only by circuit wiring in which two lands are provided in each branch wiring, whereas the inspection object A The exposed portion is only the pad P. Therefore, the inspection method described in Patent Document 1 described above cannot inspect the inspection target A.

本発明の目的は、複数の配線と、各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査することが容易な短絡検査システム、及び短絡検査方法を提供することである。 An object of the present invention is to provide a short-circuit inspection system and a short-circuit inspection method, which are capable of easily inspecting an inspection object including a plurality of wirings and a conductive portion that electrically connects one ends of the wirings to each other.

本発明の一例に係る短絡検査システムは、四本以上の配線と、前記各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査するための短絡検査システムであって、前記四本以上の配線のうち一対の第一配線における一方の他端と他方の他端との間に電流を流す電流供給部と、前記一対の第一配線とは異なる配線であって、前記一対の第一配線のうち少なくとも一本に対して隣接する配線を含む一対の第二配線における一方の他端と他方の他端との間の電圧を検出する電圧検出部と、前記電圧検出部によって検出された電圧が実質的にゼロでない場合に、不良と判定する検査処理部とを備える。 A short-circuit inspection system according to an example of the present invention is a short-circuit inspection system for inspecting an inspection object including four or more wirings and a conductive portion that electrically connects one ends of the wirings to each other. A current supply unit that causes a current to flow between the other end and the other end of the pair of first wirings among the plurality of wirings, and a wiring different from the pair of first wirings. A voltage detection unit that detects a voltage between one end and the other end of the pair of second wirings including a wiring adjacent to at least one of the first wirings, and the voltage detection unit detects the voltage. An inspection processing unit that determines a defect when the applied voltage is not substantially zero.

また、本発明の一例に係る短絡検査方法は、四本以上の配線と、前記各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査するための短絡検査方法であって、前記四本以上の配線のうち一対の第一配線における一方の他端と他方の他端との間に電流を流す電流供給工程と、前記一対の配線とは異なる配線であって、前記一対の第一配線のうち少なくとも一本に対して隣接する配線を含む一対の第二配線における一方の他端と他方の他端との間の電圧を検出する電圧検出工程と、前記電圧検出工程によって検出された電圧が実質的にゼロでない場合に、不良と判定する検査工程とを含む。 A short-circuit inspection method according to an example of the present invention is a short-circuit inspection method for inspecting an inspection object including four or more wirings and a conductive portion that electrically connects one end of each wiring to each other, Of the four or more wirings, a current supply step of flowing a current between the other end and the other end of the pair of first wirings is a wiring different from the pair of wirings. A voltage detection step of detecting a voltage between one end and the other end of the pair of second wirings including a wiring adjacent to at least one of the first wirings, and detected by the voltage detection step. And an inspection step of determining that the voltage is defective when the applied voltage is not substantially zero.

このような構成の短絡検査システム、及び短絡検査方法は、複数の配線と、各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査することが容易である。 With the short-circuit inspection system and the short-circuit inspection method having such a configuration, it is easy to inspect an inspection object including a plurality of wirings and a conductive portion that electrically connects one ends of the wirings to each other.

本発明の一実施形態に係る短絡検査方法を用いる短絡検査装置の構成の一例を示すブロック図である。It is a block diagram which shows an example of a structure of the short circuit inspection device which uses the short circuit inspection method which concerns on one Embodiment of this invention. 本発明の一実施形態に係る短絡検査方法及び短絡検査装置の動作の一例を示すフローチャートである。It is a flow chart which shows an example of operation of a short circuit inspection method and a short circuit inspection device concerning one embodiment of the present invention. パッドの配置の一例を示す説明図である。It is explanatory drawing which shows an example of arrangement|positioning of a pad. パッドの配置の他の一例を示す説明図である。It is explanatory drawing which shows another example of arrangement|positioning of a pad. 正常なときの電流経路を示す説明図である。It is explanatory drawing which shows the electric current path at the time of normal. 短絡不良が生じているときの電流経路を示す説明図である。It is explanatory drawing which shows the electric current path at the time of the short circuit defect being produced. 図6の等価回路図である。FIG. 7 is an equivalent circuit diagram of FIG. 6. ファンアウトウェハレベルパッケージのチップラスト工法を説明するための説明図である。It is explanatory drawing for demonstrating the chip last construction method of a fan-out wafer level package.

以下、本発明に係る実施形態を図面に基づいて説明する。なお、各図において同一の符号を付した構成は、同一の構成であることを示し、その説明を省略する。図1、図8を参照して、短絡検査システムの一例である短絡検査装置1は、複数のプローブPr、スキャナ部2、電流供給部3、電圧検出部4、及び制御部5を備えている。 Hereinafter, embodiments according to the present invention will be described with reference to the drawings. It should be noted that in each of the drawings, the components denoted by the same reference numerals indicate the same components, and the description thereof will be omitted. With reference to FIG. 1 and FIG. 8, a short circuit inspection apparatus 1 which is an example of a short circuit inspection system includes a plurality of probes Pr, a scanner unit 2, a current supply unit 3, a voltage detection unit 4, and a control unit 5. ..

図8(b)には、検査対象物Aが、八本の配線Lと八個のパッドPを備える例を示しているが、短絡検査装置1は、四本以上の配線Lと、四つ以上のパッドPとを備えた検査対象物Aを検査することができる。 FIG. 8B shows an example in which the inspection object A includes eight wirings L and eight pads P, but the short-circuit inspection apparatus 1 includes four or more wirings L and four wirings L. It is possible to inspect the inspection object A including the above-mentioned pad P.

なお、検査対象物は、ファンアウトウェハレベルパッケージにおけるチップラスト工程用の、キャリアに再配置配線層が形成されたものに限らない。例えば、基板の製造方法として、導電性の金属板を土台としてこの金属板の両面にプリント配線基板を積層形成し、形成された基板を土台の金属板から剥離することによって、二枚のプリント配線基板を形成する方法がある。このような基板の製造方法において、土台の金属板から基板を剥離する前の状態の基板(以下、中間基板と称する)は、金属板が二枚の基板に挟まれた態様を有している。このような中間基板は、キャリア基板とも称される。中間基板においても、複数の配線の一端が金属板(導電部)によって互いに導通される構成を有する場合がある。このような中間基板を検査対象物としてもよい。 The inspection target is not limited to the one in which the rearrangement wiring layer is formed on the carrier for the chip last process in the fan-out wafer level package. For example, as a method of manufacturing a board, a conductive metal plate is used as a base to form printed wiring boards on both sides of the metal plate, and the formed board is peeled from the base metal plate to form two printed wiring boards. There is a method of forming a substrate. In such a substrate manufacturing method, the substrate (hereinafter referred to as an intermediate substrate) in a state before the substrate is separated from the base metal plate has a mode in which the metal plate is sandwiched between two substrates. .. Such an intermediate substrate is also called a carrier substrate. The intermediate substrate may also have a configuration in which one ends of the plurality of wirings are electrically connected to each other by the metal plate (conductive portion). Such an intermediate substrate may be an inspection target.

また、基板内層に面状に拡がる導体パターンを備え、複数の配線の一端がこの導体パターン(導電部)によって互いに導通される構成を有する多層基板がある。このような多層基板を検査対象物としてもよい。 Further, there is a multilayer substrate having a conductor pattern that spreads in a planar shape in an inner layer of the substrate, and one end of a plurality of wirings is electrically connected to each other by the conductor pattern (conductive portion). Such a multilayer substrate may be an inspection target.

複数のプローブPrは、検査対象物Aに設けられた複数のパッドP(他端)に、それぞれ接触する。電流供給部3は、いわゆる定電流電源回路である。電流供給部3は、制御部5からの制御信号に応じて、スキャナ部2とプローブPrとを介して検査対象物Aへ電流Iを供給する。電圧検出部4は、プローブPrとスキャナ部2とを介して検査対象物Aの電圧を検出し、その電圧値を制御部5へ送信する電圧検出回路である。 The plurality of probes Pr come into contact with the plurality of pads P (other ends) provided on the inspection object A, respectively. The current supply unit 3 is a so-called constant current power supply circuit. The current supply unit 3 supplies a current I to the inspection object A via the scanner unit 2 and the probe Pr in response to a control signal from the control unit 5. The voltage detection unit 4 is a voltage detection circuit that detects the voltage of the inspection object A via the probe Pr and the scanner unit 2 and transmits the voltage value to the control unit 5.

スキャナ部2は、例えばトランジスタやリレースイッチ等のスイッチング素子を用いて構成された切り替え回路である。スキャナ部2は、検査対象物Aに電流Iを供給するための電流端子+F,−Fと、電流Iによって検査対象物Aの一対のパッドP間に生じた電圧を検出するための電圧検出端子+S,−Sとを備えている。また、スキャナ部2には、複数のプローブPrが電気的に接続されている。スキャナ部2は、制御部5からの制御信号に応じて電流端子+F,−F及び電圧検出端子+S,−Sと、複数のプローブPrとの間の接続関係を切り替える。 The scanner unit 2 is a switching circuit configured by using switching elements such as transistors and relay switches. The scanner unit 2 has current terminals +F and −F for supplying a current I to the inspection object A and a voltage detection terminal for detecting a voltage generated between the pair of pads P of the inspection object A by the current I. It has +S, -S. A plurality of probes Pr are electrically connected to the scanner unit 2. The scanner unit 2 switches the connection relationship between the current terminals +F and −F and the voltage detection terminals +S and −S and the plurality of probes Pr according to the control signal from the control unit 5.

電流供給部3は、その出力端子の、正極側が電流端子+Fに接続され、負極側が電流端子−Fに接続されている。電圧検出部4は、その一端が電圧検出端子+Sに接続され、他端が電圧検出端子−Sに接続されている。 The current supply unit 3 has its output terminal, the positive electrode side being connected to the current terminal +F, and the negative electrode side being connected to the current terminal -F. The voltage detection unit 4 has one end connected to the voltage detection terminal +S and the other end connected to the voltage detection terminal -S.

そして、スキャナ部2は、制御部5からの制御信号に応じて、電流端子+F,−F及び電圧検出端子+S,−Sを任意のプローブPrに導通接続可能にされている。これにより、電流供給部3は、制御部5からの制御信号に応じて選択された一対の第一配線である配線LのパッドPとパッドPとの間に電流を流す。また、電圧検出部4は、制御部5からの制御信号に応じて選択された、一対の第一配線とは異なる配線Lであって、一対の第一配線のうち少なくとも一本に対して隣接する配線Lを含む一対の第二配線のパッドPとパッドPとの間の電圧を検出する。 Then, the scanner unit 2 can connect the current terminals +F and −F and the voltage detection terminals +S and −S to the arbitrary probe Pr in accordance with the control signal from the control unit 5. As a result, the current supply unit 3 causes a current to flow between the pad P and the pad P of the wiring L that is the pair of first wirings selected according to the control signal from the control unit 5. In addition, the voltage detection unit 4 is a wiring L selected according to a control signal from the control unit 5 and different from the pair of first wirings, and is adjacent to at least one of the pair of first wirings. The voltage between the pad P and the pad P of the pair of second wirings including the wiring L is detected.

制御部5は、例えばマイクロコンピュータを用いて構成されている。制御部5は、所定の演算処理を実行するCPU(Central Processing Unit)、データを一時的に記憶するRAM(Random Access Memory)、不揮発性のハードディスクドライブ又はフラッシュメモリ等の記憶部53、及びこれらの周辺回路等を備える。そして、制御部5は、例えば記憶部53に予め記憶された制御プログラムを実行することによって、配線選択部51、及び検査処理部52として機能する。 The control unit 5 is configured using, for example, a microcomputer. The control unit 5 includes a CPU (Central Processing Unit) that executes predetermined arithmetic processing, a RAM (Random Access Memory) that temporarily stores data, a storage unit 53 such as a nonvolatile hard disk drive or a flash memory, and these. It is equipped with peripheral circuits. Then, the control unit 5 functions as the wiring selection unit 51 and the inspection processing unit 52, for example, by executing a control program stored in advance in the storage unit 53.

また、記憶部53には、再配置配線層103の配線構造を示す配線情報が、予め記憶されている。配線情報は、再配置配線層103における、複数の配線L及びパッドPの配置を示す情報である。配線情報としては、例えば再配置配線層103の製造に用いられるガーバーデータ等を用いることができる。 In addition, wiring information indicating the wiring structure of the rearrangement wiring layer 103 is stored in the storage unit 53 in advance. The wiring information is information indicating the arrangement of the plurality of wirings L and pads P in the rearrangement wiring layer 103. As the wiring information, for example, Gerber data used for manufacturing the rearranged wiring layer 103 can be used.

配線選択部51は、配線情報に基づいて、一対の配線Lを第一配線として選択し、第一配線とは異なる一対の配線Lを第二配線として選択する。配線選択部51は、第一配線及び第二配線として配線Lを選択する際に、一対の第一配線のうち少なくとも一本と、一対の第二配線のうち少なくとも一本とが隣接する組合せで配線Lを選択する。 The wiring selection unit 51 selects a pair of wirings L as a first wiring and a pair of wirings L different from the first wiring as a second wiring based on the wiring information. When selecting the wiring L as the first wiring and the second wiring, the wiring selection unit 51 uses a combination in which at least one of the pair of first wirings and at least one of the pair of second wirings are adjacent to each other. Select the wiring L.

なお、配線選択部51を、短絡検査装置1が備える例に限らない。例えば、短絡検査装置1とは別のコンピュータを配線選択部51として機能させることによって、短絡検査装置1とは別の装置として配線選択部51を構成してもよい。そして、配線選択部51として構成されたコンピュータが、配線情報に基づいて一対の第一配線と一対の第二配線とを選択し、このようにして得られた一対の第一配線と一対の第二配線とを示す情報を、記憶部53に記憶させてもよい。このように、配線選択部51として構成されたコンピュータと、配線選択部51を含まない短絡検査装置1とから、短絡検査システムを構成してもよい。 The wiring selection unit 51 is not limited to the example provided in the short circuit inspection device 1. For example, the wiring selection unit 51 may be configured as a device different from the short circuit inspection device 1 by causing a computer different from the short circuit inspection device 1 to function as the wiring selection unit 51. Then, the computer configured as the wiring selection unit 51 selects the pair of first wirings and the pair of second wirings based on the wiring information, and the pair of first wirings and the pair of first wirings thus obtained are selected. Information indicating the two wirings may be stored in the storage unit 53. As described above, the computer configured as the wiring selection unit 51 and the short-circuit inspection device 1 that does not include the wiring selection unit 51 may form a short-circuit inspection system.

第一配線及び第二配線を選択するために互いに隣接する配線Lを選択する方法としては、公知の方法を用いることができ、例えばダイナトロン社製 PC-Auto CAMを用いることができる。 A known method can be used as a method of selecting the wirings L adjacent to each other in order to select the first wiring and the second wiring, and for example, PC-Auto CAM manufactured by Dynatron can be used.

また、配線選択部51を備えない短絡検査装置1のみを短絡検査システムとしてもよい。一対の第一配線と一対の第二配線とを、必ずしも配線選択部51によって選択する必要はなく、例えば作業者が一対の第一配線と一対の第二配線とを選択し、短絡検査装置1の記憶部53に記憶させてもよい。 Further, only the short circuit inspection device 1 that does not include the wiring selection unit 51 may be the short circuit inspection system. The pair of first wirings and the pair of second wirings do not necessarily have to be selected by the wiring selection unit 51. For example, an operator selects the pair of first wirings and the pair of second wirings, and the short circuit inspection device 1 It may be stored in the storage unit 53.

検査処理部52は、配線選択部51によって選択され、又は記憶部53に記憶された第一及び第二配線に基づいてスキャナ部2を制御し、電流供給部3によって一対の第一配線に電流を供給させ、電圧検出部4によって一対の第二配線間の電圧を検出させる。 The inspection processing unit 52 controls the scanner unit 2 based on the first and second wirings selected by the wiring selection unit 51 or stored in the storage unit 53, and the current supply unit 3 supplies a current to the pair of first wirings. Is supplied, and the voltage detection unit 4 detects the voltage between the pair of second wirings.

そして、検査処理部52は、電圧検出部4によって検出された電圧が実質的にゼロでない場合に、不良と判定する。 Then, the inspection processing unit 52 determines that there is a defect when the voltage detected by the voltage detection unit 4 is not substantially zero.

次に、本発明の一実施形態に係る短絡検査方法及び短絡検査装置1の動作について説明する。図2〜図4を参照して、まず、配線選択部51は、配線情報を参照して、一対の第一配線のうち一本と一対の第二配線のうち一本とが隣接し、一対の第一配線のうち他の一本と一対の第二配線のうち他の一本とが隣接する配線Lの組合せを探索する(ステップS1)。 Next, the operation of the short circuit inspection method and the short circuit inspection apparatus 1 according to the embodiment of the present invention will be described. With reference to FIGS. 2 to 4, first, the wiring selection unit 51 refers to the wiring information, and one of the pair of first wirings and one of the pair of second wirings are adjacent to each other, and The combination of the wiring L in which another one of the first wirings and the other one of the pair of second wirings are adjacent to each other is searched (step S1).

ここで、二本の配線Lが隣接している場合、その二本の配線L間が、大きく離れている場合、その二本の配線Lが短絡するような不良は生じにくいと考えられる。そこで、短絡不良が生じやすい配線Lの距離を、予め設定距離として設定しておく。そして、配線選択部51は、ステップS1において、一対の第一配線のうち一本と一対の第二配線のうち一本とが設定距離の範囲内で隣接し、一対の第一配線のうち他の一本と一対の第二配線のうち他の一本とが、設定距離の範囲内で隣接する配線Lの組合せを探索することが、より好ましい。 Here, when the two wirings L are adjacent to each other and when the two wirings L are greatly separated, it is considered that a defect such as short-circuiting of the two wirings L is unlikely to occur. Therefore, the distance of the wiring L, which is likely to cause a short circuit failure, is set in advance as a set distance. Then, in step S1, the wiring selection unit 51 determines that one of the pair of first wirings and one of the pair of second wirings are adjacent to each other within the range of the set distance, and the other of the pair of first wirings. It is more preferable to search for a combination of the adjacent wirings L within the range of the set distance between the one wiring and the other one of the pair of second wirings.

図3、図4は、パッドP1〜P8の配置を図8(b)に示す再配置配線層103の上面側からみて示している。互いに隣接するパッドPに連なる配線L同士は隣接している。図3に示す例では、パッドP1,P2に連なる配線L1,L2を第一配線G1、パッドP5,P6に連なる配線L5,L6を第二配線G2とすることによって、一対の第一配線G1のうち配線L1と一対の第二配線G2のうち配線L5とが隣接し、一対の第一配線G1のうち配線L2と一対の第二配線G2のうち配線L6とが隣接する。 FIGS. 3 and 4 show the arrangement of the pads P1 to P8 as viewed from the upper surface side of the rearrangement wiring layer 103 shown in FIG. 8B. The wirings L connected to the pads P adjacent to each other are adjacent to each other. In the example shown in FIG. 3, the wirings L1 and L2 connected to the pads P1 and P2 are the first wiring G1, and the wirings L5 and L6 connected to the pads P5 and P6 are the second wiring G2. The wiring L1 is adjacent to the wiring L5 of the pair of second wirings G2, and the wiring L2 of the pair of first wirings G1 is adjacent to the wiring L6 of the pair of second wirings G2.

配線選択部51は、このような組合せが見つかった場合(ステップS2でYES)、見つかった組合せで一対の第一配線G1と一対の第二配線G2とを選択する(ステップS4)。図3で示すように配線Lが配置されている場合、配線選択部51は、配線L1,L2を第一配線G1、配線L5,L6を第二配線G2とする。 When such a combination is found (YES in step S2), the wiring selection unit 51 selects the pair of first wirings G1 and the pair of second wirings G2 in the found combination (step S4). When the wiring L is arranged as shown in FIG. 3, the wiring selection unit 51 sets the wirings L1 and L2 as the first wiring G1 and the wirings L5 and L6 as the second wiring G2.

一方、例えば図4で示すように配線L1〜L8が一列に配列されていた場合等では、ステップS1で探索する配線Lの組合せは存在しない。従って、ステップS1において探索された組合せが無かった場合(ステップS2でNO)、配線選択部51は、配線情報を参照して、一対の第一配線のうち一本と一対の第二配線のうち一本とが隣接する配線Lの組合せを探索する(ステップS3)。 On the other hand, for example, when the wirings L1 to L8 are arranged in a line as shown in FIG. 4, there is no combination of the wirings L searched in step S1. Therefore, when there is no combination searched in step S1 (NO in step S2), the wiring selection unit 51 refers to the wiring information and selects one of the pair of first wirings and the pair of second wirings. A combination of wirings L adjacent to each other is searched (step S3).

ステップS3においても、ステップS1の場合と同様、配線選択部51は、一対の第一配線のうち一本と一対の第二配線のうち一本とが、設定距離の範囲内で隣接する配線Lの組合せを探索することが、より好ましい。 In step S3 as well, as in the case of step S1, the wiring selection unit 51 causes the wiring L in which one of the pair of first wirings and one of the pair of second wirings are adjacent to each other within the set distance range. More preferred is to search for a combination of

図4に示す例では、パッドP1,P2に連なる配線L1,L2を第一配線G1、パッドP3,P4に連なる配線L3,L4を第二配線G2とすることによって、一対の第一配線G1のうち配線L2と一対の第二配線G2のうち配線L3とが隣接する。 In the example shown in FIG. 4, the wirings L1 and L2 connected to the pads P1 and P2 are the first wiring G1, and the wirings L3 and L4 connected to the pads P3 and P4 are the second wiring G2. The wiring L2 and the wiring L3 of the pair of second wirings G2 are adjacent to each other.

次に、検査処理部52は、配線選択部51によって選択された、一対の第一配線G1と一対の第二配線G2とに基づいて、スキャナ部2によって、電流供給部3を一対の第一配線のパッドPに接続させ、電圧検出部4を一対の第二配線のパッドPに接続させる(ステップS5)。 Next, the inspection processing unit 52 causes the scanner unit 2 to connect the current supply unit 3 to the pair of first wirings based on the pair of first wirings G1 and the pair of second wirings G2 selected by the wiring selection unit 51. The voltage detection unit 4 is connected to the pad P of the wiring, and the voltage detection unit 4 is connected to the pad P of the pair of second wirings (step S5).

次に、検査処理部52は、電流供給部3によって一対の第一配線に電流Iを流させつつ、電圧検出部4によって一対の第二配線のパッドP間の電圧Vを検出させる(ステップS6)。 Next, the inspection processing unit 52 causes the voltage supply unit 3 to cause the current I to flow through the pair of first wirings, and causes the voltage detection unit 4 to detect the voltage V between the pads P of the pair of second wirings (step S6). ).

ステップS3、図4に示すように、配線L1,L2を第一配線G1、配線L3,L4を第二配線G2とした場合、図5に示すように、パッドP2から配線L2、導電層102、及び配線L1を介してパッドP1に至る経路に電流Iが流れる。また、電圧検出部4によって電圧測定される、パッドP3,P4間の経路には電流が流れないから、電圧検出部4による測定対象のループ回路内を流れる電流はゼロである。従って、パッドP3,P4間の経路の抵抗値をRsとすると、電圧V=0×Rs=0となる。すなわち、第一配線G1と第二配線G2との間に短絡不良がなかった場合、電圧検出部4によって検出される電圧Vはゼロとなる。 Step S3, as shown in FIG. 4, when the wirings L1 and L2 are the first wirings G1 and the wirings L3 and L4 are the second wirings G2, as shown in FIG. 5, from the pad P2 to the wiring L2, the conductive layer 102, A current I flows through a path reaching the pad P1 via the wiring L1. In addition, since no current flows in the path between the pads P3 and P4 whose voltage is measured by the voltage detection unit 4, the current flowing through the loop circuit to be measured by the voltage detection unit 4 is zero. Therefore, if the resistance value of the path between the pads P3 and P4 is Rs, the voltage V=0×Rs=0. That is, when there is no short circuit defect between the first wiring G1 and the second wiring G2, the voltage V detected by the voltage detection unit 4 becomes zero.

そこで、検査処理部52は、電圧Vをゼロと比較し(ステップS7)、電圧Vが実質的にゼロであった場合(ステップS7でYES)、隣接する第一配線G1と第二配線G2との間に短絡なしと判定し(ステップS8)、処理を終了する。 Therefore, the inspection processing unit 52 compares the voltage V with zero (step S7), and when the voltage V is substantially zero (YES in step S7), the adjacent first wiring G1 and second wiring G2 are connected. During this period, it is determined that there is no short circuit (step S8), and the process ends.

なお、実質的にゼロ、とは、電圧検出部4の検出誤差、検査対象物A内における正常範囲内の漏れ電流等により生じた電圧はゼロとみなすことを意味する。 It should be noted that “substantially zero” means that the voltage generated by the detection error of the voltage detection unit 4, the leakage current within the normal range in the inspection object A, and the like is regarded as zero.

一方、第一配線G1と第二配線G2との間に短絡不良が生じている場合、以下のようになる。例えば、図6に示すように、配線L2と配線L3の間に短絡部Reが生じていた場合、配線L2を流れる電流Iは、短絡部Reとの分岐点で、そのまま配線L2を流れる電流I1と、短絡部Reを流れる電流I2とに分流する。電流I2は、配線L3及び導電層102を介して電流I1と合流する。 On the other hand, when a short circuit defect has occurred between the first wiring G1 and the second wiring G2, the following occurs. For example, as shown in FIG. 6, when a short-circuited portion Re occurs between the wiring L2 and the wiring L3, the current I flowing through the wiring L2 is a branch point with the short-circuited portion Re and the current I1 flowing through the wiring L2 as it is. And the current I2 flowing through the short circuit portion Re. The current I2 joins the current I1 via the wiring L3 and the conductive layer 102.

図7は、配線L1を抵抗R1、配線L2の短絡部ReよりパッドP2側を抵抗R21、配線L2の短絡部Reより導電層102側を抵抗R22、配線L3の短絡部ReよりパッドP3側を抵抗R31、配線L3の短絡部Reより導電層102側を抵抗R32、配線L4を抵抗R4、配線L1,L2間の導電層102を抵抗Rc1、配線L2,L3間の導電層102を抵抗Rc2、配線L3,L4間の導電層102を抵抗Rc3で表している。 In FIG. 7, the wiring L1 is the resistance R1, the pad P2 side is the resistance R21 from the short circuit portion Re of the wiring L2, the conductive layer 102 side is the resistance R22 from the short circuit portion Re of the wiring L2, and the pad P3 side is the short circuit portion Re from the wiring L3. A resistor R31, a resistor R32 on the conductive layer 102 side of the short circuit portion Re of the wiring L3, a resistor R4 on the wiring L4, a resistor Rc1 on the conductive layer 102 between the wirings L1 and L2, a resistor Rc2 on the conductive layer 102 between the wirings L2 and L3, The conductive layer 102 between the wirings L3 and L4 is represented by a resistor Rc3.

図7に示すように、電流I2は、短絡部Re、抵抗R32、及び抵抗Rc2を流れる。一方、電圧検出部4は、抵抗R31,R32,Rc3,R4の直列回路の両端電圧を電圧Vとして検出する。そうすると、電圧Vは実質的にゼロにはならず、電圧検出部4は、抵抗R32の抵抗値B×I2の電圧を、電圧Vとして検出することになる。 As shown in FIG. 7, the current I2 flows through the short circuit portion Re, the resistor R32, and the resistor Rc2. On the other hand, the voltage detector 4 detects the voltage across the series circuit of the resistors R31, R32, Rc3, R4 as the voltage V. Then, the voltage V does not become substantially zero, and the voltage detection unit 4 detects the voltage of the resistance value B×I2 of the resistor R32 as the voltage V.

そこで、検査処理部52は、電圧Vが実質的にゼロでなかった場合(ステップS7でNO)、隣接する第一配線G1と第二配線G2との間に短絡ありと判定し(ステップS9)、処理を終了する。 Therefore, when the voltage V is not substantially zero (NO in step S7), the inspection processing unit 52 determines that there is a short circuit between the adjacent first wiring G1 and second wiring G2 (step S9). , The process ends.

図7では、パッドP1〜P8が一列に並ぶ例(図4)において配線L1,L2を第一配線G1、配線L3,L4を第二配線G2とした場合(ステップS3)について説明したが、パッドP1〜P4の列とパッドP5〜P8の列とが並行に並ぶ例(図3)において配線L1,L2を第一配線G1、配線L5,L6を第二配線G2とした場合(ステップS1)であっても、第一配線G1と第二配線G2との間の短絡不良を検査することができる。この場合、図5に括弧書きで符号を記載しているように各配線Lが配置され、上述の配線L2と配線L3との間の短絡部Reと同様、配線L2と配線L6との間に短絡不良が生じた場合、ステップS7で電圧Vが実質的にゼロではなくなる結果、短絡不良を判定可能となる。 FIG. 7 illustrates the case where the wirings L1 and L2 are the first wiring G1 and the wirings L3 and L4 are the second wiring G2 in the example where the pads P1 to P8 are arranged in a line (FIG. 4) (step S3). In the example in which the columns of P1 to P4 and the columns of pads P5 to P8 are arranged in parallel (FIG. 3), the wirings L1 and L2 are the first wirings G1 and the wirings L5 and L6 are the second wirings G2 (step S1). Even if there is, a short circuit defect between the first wiring G1 and the second wiring G2 can be inspected. In this case, the respective wirings L are arranged as indicated by the reference numerals in parentheses in FIG. 5, and like the above-mentioned short circuit Re between the wirings L2 and L3, the wirings L2 and L6 are arranged between them. When a short circuit failure occurs, the voltage V becomes substantially non-zero in step S7, so that the short circuit failure can be determined.

この場合、さらに、配線L2,L6が隣接すると共に、配線L1,L5も隣接する。そのため、配線L1,L5間に短絡不良が生じた場合であっても、ステップS7で電圧Vが実質的にゼロではなくなる。その結果、配線L2,L6間の短絡不良と、配線L1,L5間の短絡不良とを、一度に検査することが可能となる。 In this case, the wirings L2 and L6 are adjacent to each other, and the wirings L1 and L5 are adjacent to each other. Therefore, even if a short circuit failure occurs between the wirings L1 and L5, the voltage V is not substantially zero in step S7. As a result, it becomes possible to inspect for a short circuit defect between the wirings L2 and L6 and a short circuit defect between the wirings L1 and L5 at one time.

従って、一対の第一配線のうち一本と一対の第二配線のうち一本とが隣接し、一対の第一配線のうち他の一本と一対の第二配線のうち他の一本とが隣接する配線Lの組合せ(ステップS1、図3)は、一対の第一配線のうち一本と一対の第二配線のうち一本とが隣接する配線Lの組合せ(ステップS3、図4)よりも、検査効率が高い。 Therefore, one of the pair of first wirings and one of the pair of second wirings are adjacent to each other, and one of the pair of first wirings and the other of the pair of second wirings are adjacent to each other. Is a combination of wirings L adjacent to each other (step S1, FIG. 3) is a combination of wirings L where one of the pair of first wirings and one of the pair of second wirings are adjacent (step S3, FIG. 4). Inspection efficiency is higher than.

すなわち、ステップS1〜S9の処理によれば、複数の配線Lと、各配線Lの一端を互いに導通させる導電層102とを備えた検査対象物Aを検査することが容易である。また、先にステップS1を実行して検査効率の高い配線Lの組合せを優先的に探索し、そのような組合せが見つからなかった場合にステップS3を実行するので、検査対象物Aの検査効率を向上することができる。 That is, according to the processes of steps S1 to S9, it is easy to inspect the inspection target A including the plurality of wirings L and the conductive layer 102 that electrically connects one ends of the wirings L to each other. Further, the step S1 is executed first to preferentially search for a combination of the wirings L having a high inspection efficiency, and if such a combination is not found, the step S3 is executed, so that the inspection efficiency of the inspection object A is improved. Can be improved.

なお、ステップS1,S2を実行しなくてもよい。 The steps S1 and S2 may not be executed.

ところで、図6に示すような短絡部Reによって、配線L2,L3間が短絡されると、パッドP2,P3の間の抵抗値が低下する。そこで、パッドP2,P3間の抵抗値を測定し、その抵抗値が正常値より小さくなった場合に短絡不良が有ると判定する検査方法が考えられる。 By the way, when the wirings L2 and L3 are short-circuited by the short circuit portion Re as shown in FIG. 6, the resistance value between the pads P2 and P3 is reduced. Therefore, an inspection method is conceivable in which the resistance value between the pads P2 and P3 is measured and it is determined that there is a short circuit failure when the resistance value becomes smaller than a normal value.

しかしながら、配線L2,L3及び導電層102は極めて低抵抗である。従って、短絡部Reによる抵抗低下は僅かである。その結果、このような検査を行うためには、極めて高精度の抵抗測定が必要となる。 However, the wirings L2 and L3 and the conductive layer 102 have extremely low resistance. Therefore, the resistance decrease due to the short circuit portion Re is slight. As a result, extremely high-precision resistance measurement is required to perform such inspection.

このような高精度の抵抗測定方法として、四端子抵抗測定法が知られている。四端子抵抗測定法では、一つのパッドPに二つのプローブを接触させる必要がある。しかしながら、ファンアウトウェハレベルパッケージ用の、キャリア100に再配置配線層103が積層された検査対象物Aでは、パッドPは、ICダイと直接接続されるため極めて微小であり、パッドPに二本のプローブを接触させることは困難である。 A four-terminal resistance measuring method is known as such a highly accurate resistance measuring method. In the four-terminal resistance measuring method, it is necessary to bring two probes into contact with one pad P. However, in the inspection object A for the fan-out wafer level package in which the rearrangement wiring layer 103 is laminated on the carrier 100, the pad P is extremely small because it is directly connected to the IC die, and two pads P are provided. It is difficult to bring the probe into contact.

一方、短絡検査装置1によれば、一つのパッドPに一本のプローブを接触させるだけでよいので、四端子抵抗測定法を用いるよりも、検査対象物Aを容易に検査することができる。 On the other hand, according to the short-circuit inspection device 1, since it is only necessary to bring one probe into contact with one pad P, it is possible to easily inspect the inspection object A as compared with the case of using the four-terminal resistance measuring method.

また、上述のように、短絡部Reによる微小な抵抗低下に基づき短絡不良を検査する場合、良品の抵抗値を基準値とし、その基準値からの微小な抵抗低下を判定する必要がある。しかしながら、上述したように、ファンアウトウェハレベルパッケージにおける再配置配線層103の配線Lは、メッキプロセス等によって形成される。 Further, as described above, in the case of inspecting for a short circuit failure based on a minute decrease in resistance due to the short circuit portion Re, it is necessary to use a resistance value of a non-defective product as a reference value and determine a minute decrease in resistance from the reference value. However, as described above, the wiring L of the rearrangement wiring layer 103 in the fan-out wafer level package is formed by the plating process or the like.

しかしながら、メッキプロセスはバラツキが大きいため、良品の配線Lの抵抗値バラツキが大きく、その良品の抵抗バラツキが短絡部Reによる抵抗低下を容易に超えてしまう。そのため、判定基準となる基準値を設定することができず、抵抗低下に基づく短絡不良の検査は困難である。 However, since the plating process has a large variation, the variation in the resistance value of the non-defective wiring L is large, and the variation in the resistance of the non-defective article easily exceeds the resistance reduction due to the short circuit portion Re. Therefore, it is not possible to set a reference value as a determination reference, and it is difficult to inspect for a short circuit failure due to resistance decrease.

一方、短絡検査装置1によれば、電圧Vが実質的にゼロか否か(ステップS7)を判定するだけで、基準値を設定する必要がないので、配線Lの抵抗バラツキが大きくても短絡不良を検査することが容易である。 On the other hand, according to the short-circuit inspection apparatus 1, it is not necessary to set the reference value only by determining whether or not the voltage V is substantially zero (step S7), so that a short circuit occurs even if the resistance variation of the wiring L is large. It is easy to inspect for defects.

すなわち、本発明の一例に係る短絡検査システムは、四本以上の配線と、前記各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査するための短絡検査システムであって、前記四本以上の配線のうち一対の第一配線における一方の他端と他方の他端との間に電流を流す電流供給部と、前記一対の第一配線とは異なる配線であって、前記一対の第一配線のうち少なくとも一本に対して隣接する配線を含む一対の第二配線における一方の他端と他方の他端との間の電圧を検出する電圧検出部と、前記電圧検出部によって検出された電圧が実質的にゼロでない場合に、不良と判定する検査処理部とを備える。 That is, the short-circuit inspection system according to an example of the present invention is a short-circuit inspection system for inspecting an inspection object including four or more wirings and a conductive portion that electrically connects one ends of the respective wirings to each other, Of the four or more wirings, a current supply unit that causes a current to flow between the other end and the other end of the pair of first wirings, and the pair of first wirings are different wirings, A voltage detection unit that detects a voltage between one end and the other end of a pair of second wirings including a wiring adjacent to at least one of the pair of first wirings, and the voltage detection unit. An inspection processing unit that determines that the voltage is defective when the voltage detected by is not substantially zero.

また、本発明の一例に係る短絡検査方法は、四本以上の配線と、前記各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査するための短絡検査方法であって、前記四本以上の配線のうち一対の第一配線における一方の他端と他方の他端との間に電流を流す電流供給工程と、前記一対の配線とは異なる配線であって、前記一対の第一配線のうち少なくとも一本に対して隣接する配線を含む一対の第二配線における一方の他端と他方の他端との間の電圧を検出する電圧検出工程と、前記電圧検出工程によって検出された電圧が実質的にゼロでない場合に、不良と判定する検査工程とを含む。 A short-circuit inspection method according to an example of the present invention is a short-circuit inspection method for inspecting an inspection object including four or more wirings and a conductive portion that electrically connects one end of each wiring to each other, Of the four or more wirings, a current supply step of flowing a current between the other end and the other end of the pair of first wirings is a wiring different from the pair of wirings. A voltage detection step of detecting a voltage between one end and the other end of the pair of second wirings including a wiring adjacent to at least one of the first wirings, and detected by the voltage detection step. And an inspection step of determining that the voltage is defective when the applied voltage is not substantially zero.

これらの構成によれば、一対の第一配線と一対の第二配線との間に短絡不良がない場合、一対の第一配線に対して供給された電流は、一対の第二配線には流れない。従って、一対の第二配線では電圧が生じないので、一対の第二配線における一方の他端と他方の他端との間で検出される電圧は実質的にゼロとなる。一方、一対の第一配線と一対の第二配線との間に短絡不良がある場合、一対の第一配線に対して供給された電流の一部は、短絡不良を介して隣接する第二配線に回り込む。回り込んだ電流が第二配線に流れることによって電圧が生じ、一対の第二配線における一方の他端と他方の他端との間で検出される電圧は実質的にゼロではなくなる。その結果、検出された電圧が実質的にゼロでない場合、不良と判定することができる。従って、複数の配線と、各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査することが容易である。 According to these configurations, when there is no short circuit defect between the pair of first wirings and the pair of second wirings, the current supplied to the pair of first wirings flows to the pair of second wirings. Absent. Therefore, since no voltage is generated in the pair of second wirings, the voltage detected between one end and the other end of the pair of second wirings is substantially zero. On the other hand, when there is a short circuit failure between the pair of first wirings and the pair of second wirings, a part of the current supplied to the pair of first wirings is the second wiring adjacent to the pair of first wirings via the short circuit failure. Wrap around. The sneak current flows into the second wiring to generate a voltage, and the voltage detected between the other end of one of the pair of second wires is not substantially zero. As a result, if the detected voltage is not substantially zero, it can be determined as defective. Therefore, it is easy to inspect an inspection object including a plurality of wirings and a conductive portion that electrically connects one end of each wiring.

また、前記一対の第一配線のうち一本と前記一対の第二配線のうち一本とが隣接し、前記一対の第一配線のうち他の一本と前記一対の第二配線のうち他の一本とが隣接していることが好ましい。 In addition, one of the pair of first wirings and one of the pair of second wirings are adjacent to each other, and another one of the pair of first wirings and another of the pair of second wirings are adjacent to each other. It is preferable that one of the two is adjacent.

この構成によれば、一回の検査で、隣接する第一配線の一本と第二配線の一本との間の短絡不良と、隣接する第一配線のうち他の一本と第二配線の他の一本との間の短絡不良とを検査することができる。従って、検査効率が向上する。 According to this configuration, a short-circuit defect between one of the adjacent first wirings and one of the second wirings and another one of the adjacent first wirings and the second wiring can be performed in one inspection. It can be inspected for a short circuit with another one. Therefore, the inspection efficiency is improved.

また、前記四本以上の配線の中から、前記一対の第一配線と前記一対の第二配線とを選択する配線選択部をさらに備えることが好ましい。 Further, it is preferable to further include a wiring selection unit that selects the pair of first wirings and the pair of second wirings from the four or more wirings.

この構成によれば、電流供給部による電流供給の対象となる一対の第一配線と、電圧検出部による電圧検出の対象となる一対の第二配線とが、配線選択部によって選択される。 According to this configuration, the wiring selection unit selects the pair of first wirings to which the current supply unit supplies the current and the pair of second wirings to which the voltage detection unit detects the voltage.

また、前記配線選択部は、前記一対の第一配線及び前記一対の第二配線として、前記一対の第一配線のうち一本と前記一対の第二配線のうち一本とが隣接し、前記一対の第一配線のうち他の一本と前記一対の第二配線のうち他の一本とが隣接する前記配線の組合せを優先的に選択することが好ましい。 Further, the wiring selection unit, as the pair of first wirings and the pair of second wirings, one of the pair of first wirings and one of the pair of second wirings are adjacent to each other, It is preferable to preferentially select a combination of the wirings in which another one of the pair of first wirings and another one of the pair of second wirings are adjacent to each other.

この構成によれば、一回の検査で、隣接する第一配線の一本と第二配線の一本との間の短絡不良と、隣接する第一配線のうち他の一本と第二配線の他の一本との間の短絡不良とを検査することが可能な検査効率のよい配線の組合せが優先的に選択されるので、検査効率を向上させることが可能となる。 According to this configuration, a short-circuit defect between one of the adjacent first wirings and one of the second wirings and another one of the adjacent first wirings and the second wiring can be performed in one inspection. Since a wiring combination having a high inspection efficiency capable of inspecting for a short circuit with another wiring is preferentially selected, it is possible to improve the inspection efficiency.

また、前記検査対象物は、ファンアウトウェハレベルパッケージのキャリアに再配置配線層が形成されたものであり、前記各配線は、前記再配置配線層の配線であり、前記導電部は、前記キャリアの表面の導体層であってもよい。 Further, the inspection object is a fanout wafer level package in which a rearrangement wiring layer is formed on a carrier, each of the wirings is a wiring of the rearrangement wiring layer, and the conductive portion is the carrier. It may be a conductor layer on the surface of.

この構成によれば、ファンアウトウェハレベルパッケージの再配置配線層に形成された配線相互間の短絡不良を検査することができる。 With this configuration, it is possible to inspect a short circuit defect between the wirings formed in the rearranged wiring layer of the fan-out wafer level package.

1 短絡検査装置(短絡検査システム)
2 スキャナ部
3 電流供給部
4 電圧検出部
5 制御部
51 配線選択部
52 検査処理部
53 記憶部
100 キャリア
101 絶縁基板
102 導電層(導電部)
103 再配置配線層
106 ICダイ
A 検査対象物
G1 第一配線
G2 第二配線
I,I1,I2 電流
L,L1〜L8 配線
P,P1〜P8 パッド(他端)
Pr プローブ
R1,R21,R22,R31,R32,R4,Rc1〜Rc3 抵抗
Re 短絡部
V 電圧
1 Short-circuit inspection device (short-circuit inspection system)
2 Scanner Section 3 Current Supply Section 4 Voltage Detection Section 5 Control Section 51 Wiring Selection Section 52 Inspection Processing Section 53 Storage Section 100 Carrier 101 Insulating Substrate 102 Conductive Layer (Conductive Section)
103 relocation wiring layer 106 IC die A inspection object G1 first wiring G2 second wiring I, I1, I2 current L, L1 to L8 wiring P, P1 to P8 pad (other end)
Pr probe R1, R21, R22, R31, R32, R4, Rc1 to Rc3 resistance Re short circuit V voltage

Claims (6)

四本以上の配線と、前記各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査するための短絡検査システムであって、
前記四本以上の配線のうち一対の第一配線における一方の他端と他方の他端との間に電流を流す電流供給部と、
前記一対の第一配線とは異なる配線であって、前記一対の第一配線のうち少なくとも一本に対して隣接する配線を含む一対の第二配線における一方の他端と他方の他端との間の電圧を検出する電圧検出部と、
前記電圧検出部によって検出された電圧が実質的にゼロでない場合に、不良と判定する検査処理部とを備える短絡検査システム。
A short-circuit inspection system for inspecting an object to be inspected, comprising four or more wirings, and a conductive portion for electrically connecting one end of each wiring to each other,
Of the four or more wirings, a current supply unit that causes a current to flow between the other end and the other end of the pair of first wires,
A wire different from the pair of first wires, and one of the other end and the other end of the pair of second wires including a wire adjacent to at least one of the pair of first wires A voltage detection unit that detects the voltage between
A short-circuit inspection system comprising: an inspection processing unit that determines a defect when the voltage detected by the voltage detection unit is not substantially zero.
前記一対の第一配線のうち一本と前記一対の第二配線のうち一本とが隣接し、前記一対の第一配線のうち他の一本と前記一対の第二配線のうち他の一本とが隣接している請求項1に記載の短絡検査システム。 One of the pair of first wirings is adjacent to one of the pair of second wirings, and another one of the pair of first wirings and another of the pair of second wirings are adjacent to each other. The short-circuit inspection system according to claim 1, wherein the book and the book are adjacent to each other. 前記四本以上の配線の中から、前記一対の第一配線と前記一対の第二配線とを選択する配線選択部をさらに備える請求項1又は2に記載の短絡検査システム。 The short-circuit inspection system according to claim 1, further comprising a wiring selection unit that selects the pair of first wirings and the pair of second wirings from the four or more wirings. 前記配線選択部は、前記一対の第一配線及び前記一対の第二配線として、前記一対の第一配線のうち一本と前記一対の第二配線のうち一本とが隣接し、前記一対の第一配線のうち他の一本と前記一対の第二配線のうち他の一本とが隣接する前記配線の組合せを優先的に選択する請求項3に記載の短絡検査システム。 The wiring selecting unit, as the pair of first wirings and the pair of second wirings, one of the pair of first wirings and one of the pair of second wirings are adjacent to each other, and The short-circuit inspection system according to claim 3, wherein a combination of the wirings in which another one of the first wirings and another one of the pair of second wirings are adjacent to each other is preferentially selected. 前記検査対象物は、ファンアウトウェハレベルパッケージのキャリアに再配置配線層が形成されたものであり、
前記各配線は、前記再配置配線層の配線であり、
前記導電部は、前記キャリアの表面の導体層である請求項1〜4のいずれか1項に記載の短絡検査システム。
The object to be inspected is a fanout wafer level package in which a rearrangement wiring layer is formed on a carrier,
Each of the wiring is a wiring of the relocation wiring layer,
The short-circuit inspection system according to claim 1, wherein the conductive portion is a conductor layer on the surface of the carrier.
四本以上の配線と、前記各配線の一端を互いに導通させる導電部とを備えた検査対象物を検査するための短絡検査方法であって、
前記四本以上の配線のうち一対の第一配線における一方の他端と他方の他端との間に電流を流す電流供給工程と、
前記一対の配線とは異なる配線であって、前記一対の第一配線のうち少なくとも一本に対して隣接する配線を含む一対の第二配線における一方の他端と他方の他端との間の電圧を検出する電圧検出工程と、
前記電圧検出工程によって検出された電圧が実質的にゼロでない場合に、不良と判定する検査工程とを含む短絡検査方法。
A short-circuit inspection method for inspecting an inspection object comprising four or more wirings, and a conductive portion for electrically connecting one end of each wiring to each other,
Of the four or more wiring, a current supply step of flowing a current between the other end of one and the other end of the pair of first wiring,
Between the other end and the other end of the pair of second wires including a wire adjacent to at least one of the pair of first wires, which is a wire different from the pair of wires A voltage detection step of detecting the voltage,
A short-circuit inspection method comprising: an inspection step of determining a defect when the voltage detected by the voltage detection step is not substantially zero.
JP2019020464A 2019-02-07 2019-02-07 Short circuit inspection system, and short circuit inspection method Pending JP2020128881A (en)

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TW109100251A TW202040155A (en) 2019-02-07 2020-01-06 Short circuit inspection system and short circuit inspection method capable of easily inspecting an inspection object having a plurality of wirings and a conductive portion enabling one ends of perspective wirings to conduct each other
KR1020200010306A KR20200097202A (en) 2019-02-07 2020-01-29 Short-circuit inspection system and short-circuit inspection method

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Citations (3)

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Publication number Priority date Publication date Assignee Title
JP2004045349A (en) * 2002-07-16 2004-02-12 Hioki Ee Corp Circuit wiring inspection method and apparatus
JP2005300240A (en) * 2004-04-08 2005-10-27 Hioki Ee Corp Circuit wiring inspection method and apparatus
JP2012220275A (en) * 2011-04-06 2012-11-12 Hioki Ee Corp Short-circuiting inspection apparatus and short-circuiting inspection method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004045349A (en) * 2002-07-16 2004-02-12 Hioki Ee Corp Circuit wiring inspection method and apparatus
JP2005300240A (en) * 2004-04-08 2005-10-27 Hioki Ee Corp Circuit wiring inspection method and apparatus
JP2012220275A (en) * 2011-04-06 2012-11-12 Hioki Ee Corp Short-circuiting inspection apparatus and short-circuiting inspection method

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