CN114267720A - Manufacturing structure and manufacturing process of enhanced gallium nitride high electron mobility transistor - Google Patents

Abstract

The invention discloses a manufacturing structure of an enhanced gallium nitride high electron mobility transistor, which comprises a substrate, an epitaxial layer, an auxiliary structure layer and a second layer of aluminum gallium nitrogen, wherein the epitaxial layer grows on the substrate, the auxiliary structure layer grows on the epitaxial layer, a gate region is defined on the auxiliary structure layer through photoetching, the auxiliary structure layer of a non-gate region is etched, and the second layer of aluminum gallium nitrogen grows on the epitaxial layer of the non-gate region and the auxiliary structure layer reserved in the gate region or the epitaxial layer of the non-gate region independently. By introducing the auxiliary structure into the gate region of the high-mobility transistor, the manufacturing structure and the manufacturing process of the groove gate are optimized, the problems that the etching thickness is difficult to control, the etching end point is difficult to monitor and the like are solved, and the reliability is higher. The invention also discloses a manufacturing process of the enhanced gallium nitride high electron mobility transistor.

Description

Manufacturing structure and manufacturing process of enhanced gallium nitride high electron mobility transistor

Technical Field

The invention belongs to the technical field of gallium nitride manufacturing, and particularly relates to a manufacturing structure and a manufacturing process of an enhanced gallium nitride high electron mobility transistor.

Background

Gallium nitride (GaN) material is used as a third-generation semiconductor, has a critical breakdown electric field (4MV/cm) and an electron peak velocity (3 multiplied by 107cm/s) far exceeding silicon (Si), and has wide application prospects in the fields of high power and high frequency. A device (HEMT) of a High Electron Mobility Transistor based on gallium nitride has been recently proposed. The gallium nitride high electron mobility transistor conducts electricity by utilizing two-dimensional electron gas in a quantum well formed by a gallium nitride heterojunction and an aluminum gallium nitrogen heterojunction due to energy band mismatching. The two-dimensional electron gas moves in the quantum well and is less scattered, so that the gallium nitride high electron mobility transistor has very high electron peak velocity and can work at very high frequency (>10MHz), and the limit frequency of a typical silicon-based device is about 1 MHz. The two-dimensional electron gas with high-efficiency migration also enables the on-resistance of the gallium nitride high-electron-mobility transistor to be very low, is suitable for power application, reduces the power loss of a switch, and improves the energy utilization efficiency. In addition, the current carriers of the silicon-based device are mainly from the ionization of impurities, and the ionization of the impurities is greatly influenced by the temperature, so that the temperature stability of the gallium nitride high electron mobility transistor is better than that of the silicon-based device because the two-dimensional electron gas does not come from the ionization of the impurities. For example, the threshold voltage is affected by temperature, the gallium nitride HEMT is 0.5V/150oC, and the silicon based device is 2V/150 oC.

However, since the two-dimensional electron gas exists without an applied voltage, and the applied voltage is required to deplete the two-dimensional electron gas layer to turn off the device, the gan hemt is depletion type, i.e. the threshold voltage is negative. This is disadvantageous for practical applications, since for better reliability of the system, especially for power applications, it is often desirable to have the transistor enhancement mode. The fabrication process of the current major enhancement mode gan hemts is as follows:

1. a depletion mode high electron mobility transistor (hemt) and an enhancement mode Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are fabricated in a Cascade (Cascade) manner and connected in series by means of package or board level interconnects.

2. And in the grid groove etching mode, the thickness of the aluminum gallium nitride below the grid is reduced by etching, the polarization effect of the aluminum gallium nitride in the grid region is weakened, and when the grid voltage is 0, the two-dimensional electron gas is in a depleted state.

3. Fluorine (F) ion injection mode, injecting fluorine ions into the gate area AlGaN, raising the AlGaN energy band, and exhausting the two-dimensional electron gas, so that the two-dimensional electron gas is exhausted under the gate zero-voltage state.

4. In the p-type gallium nitride process, a layer of p-type doped gallium nitride is inserted between a gate and aluminum gallium nitrogen to form a heterojunction, so that the energy band of the gallium nitride is raised, and two-dimensional electron gas is exhausted.

However: the existing enhanced gallium nitride high electron mobility transistor process has certain defects, and the improvement of the device performance is limited:

1. the cascade mode greatly weakens the performance of the gallium nitride electron mobility transistor because many performances of the metal oxide semiconductor field effect transistor are inferior to those of the gallium nitride high electron mobility transistor. Such as frequency, temperature stability, on-resistance, etc.

2. And (3) a gate groove etching mode, wherein the epitaxial growth of AlGaN with a certain thickness is performed firstly, then a part of the gate region is etched, for example, 50 nm AlGaN is grown, then 40 nm AlGaN of the gate region is etched, and 10 nm AlGaN is left. There are two problems with this approach. The first is that it is difficult to ensure accurate etching of a certain thickness by etching the same material of the semiconductor, and the thickness of the etched AlGaN determines the thickness of the remained AlGaN, thereby determining the parameters of the threshold voltage and the like of the device, which can lead to the deterioration of the consistency of the device. In addition, the semiconductor dry etching machine can judge the etched material by monitoring the glow generated by the reaction of the etching plasma and the material, and completely etch one material, and can judge the etching end point by glow detection, so that the specified thickness is left when one material is etched, and the process yield is difficult to control because the glow monitoring cannot be adopted.

3. In the fluorine ion implantation mode, the radius of fluorine ion atoms is very small, and the fluorine ions are easy to migrate in the material, so that the reliability of the device prepared by the process is difficult to guarantee.

4. The p-type gallium nitride process is the only mass production process except the cascade mode, but still has many problems. The first problem is that it is difficult to increase the threshold voltage and reduce the on-resistance simultaneously, because the thicker the algan in the non-gate region, the higher the concentration of the two-dimensional electron gas, and the algan thickness in the gate region affects the threshold voltage of the device. In the p-type gallium nitride process, the thickness of the aluminum gallium nitride of the gate region and the thickness of the aluminum gallium nitride of the non-gate region are the same, so that the loss of the on-resistance is inevitably caused by the increase of the threshold voltage. The second problem is that the grown gan is N-type and must be doped with p-type impurities to obtain p-type gan. Magnesium (Mg) is a commonly used impurity, but magnesium is a deep-level impurity, the theoretical value of the activation efficiency is 8-10%, and hydrogen (H) is inevitably introduced in the growth process of p-type gallium nitride, and the hydrogen and the magnesium form magnesium-hydrogen (Mg-H), so that the magnesium cannot be ionized to generate holes. Therefore, the carrier concentration of the p-type gallium nitride is difficult to promote, and the lifting effect on the aluminum gallium nitrogen energy level is difficult to promote, so that the two-dimensional electron gas is difficult to be effectively exhausted, and the threshold voltage is improved.

The groove gate technology is an important technical route, the thickness of the AlGaN at the lower edge of the gate is reduced through etching, the polarization effect of the AlGaN in the gate region is weakened, and when the gate voltage is 0, the two-dimensional electron gas is in a depleted state.

However, the trench gate technology also has inherent technical difficulties, and when the trench gate is manufactured, because the epitaxial structure of the AlGaN/GaN HEMT is multi-layered and the etching rates of the layers are different, the depth of the trench gate is difficult to control through etching time, so that the instability of threshold voltage Vth and transconductance is also caused. Moreover, various etching methods can form a damage layer on the interface of the bottom of the gate, and can reduce the mobility. Therefore, optimizing the etching process of the GaN material, accurately controlling the etching depth, reducing the influence of etching damage on the device characteristics, and ensuring the etching rate and good morphology while reducing the etching damage are the key points of the current research on the groove etching process. The mainstream process route at present is to control the etching depth by a circular etching method, but the accurate control (nanometer level) can not be realized yet

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a manufacturing structure and a manufacturing process of an enhanced gallium nitride high electron mobility transistor, wherein an auxiliary structure is introduced into a gate region of the high mobility transistor, so that the manufacturing structure and the manufacturing process of a groove gate are optimized, the problems that the etching thickness is difficult to control, the etching end point is difficult to monitor and the like are avoided, and the reliability is higher.

In order to achieve the purpose, the technical scheme of the invention is as follows: a manufacturing structure of an enhanced gallium nitride high electron mobility transistor comprises a substrate, an epitaxial layer, an auxiliary structure layer and a second layer of aluminum gallium nitride, wherein the epitaxial layer grows on the substrate, the auxiliary structure layer grows on the epitaxial layer, a grid region is defined on the auxiliary structure layer through photoetching, the auxiliary structure layer of a non-grid region is etched, and the second layer of aluminum gallium nitride grows on the epitaxial layer of the non-grid region and the auxiliary structure layer reserved in the grid region or on the epitaxial layer of the non-grid region independently.

Furthermore, the epitaxial layer comprises a gallium nitride layer and a first layer of aluminum gallium nitride, the auxiliary structure layer comprises a protective layer and a sacrificial layer, and the gallium nitride layer, the first layer of aluminum gallium nitride, the protective layer and the sacrificial layer form a laminated structure.

Furthermore, the gallium nitride layer grows on the substrate, the first layer of aluminum gallium nitrogen grows on the gallium nitride layer, the protective layer grows on the first layer of aluminum gallium nitrogen, and the sacrificial layer grows on the protective layer.

Furthermore, the protective layer is made of aluminum nitride or silicon nitride, the sacrificial layer is made of silicon nitride or aluminum nitride, the dry etching selection ratio of the sacrificial layer to the protective layer is more than 100, and the wet etching selection ratio of the protective layer to the aluminum gallium nitride layer and the sacrificial layer is more than 100.

Furthermore, the epitaxial layer comprises a buffer layer, an intrinsic gallium nitride layer, an aluminum nitride insertion layer and a thin aluminum gallium nitride layer, wherein the buffer layer grows on the substrate, the intrinsic gallium nitride layer grows on the buffer layer, the aluminum nitride insertion layer grows on the intrinsic gallium nitride layer, and the thin aluminum gallium nitride layer grows on the aluminum nitride insertion layer.

Furthermore, the auxiliary structure layer is a silicon dioxide sacrificial layer, the silicon dioxide sacrificial layer grows on the thin-layer AlGaN, and the buffer layer, the intrinsic gallium nitride layer, the aluminum nitride insertion layer, the thin-layer AlGaN and the silicon dioxide sacrificial layer form a laminated structure.

The invention also relates to a manufacturing process of the enhanced gallium nitride high electron mobility transistor, which is based on the manufacturing structure of the enhanced gallium nitride high electron mobility transistor and comprises the following steps:

a. growing a substrate, growing an epitaxial layer on the substrate, and growing an auxiliary structure layer on the epitaxial layer;

b. defining a gate region on the auxiliary structure layer by adopting photoetching, etching off the auxiliary structure layer of the non-gate region, and growing a second layer of aluminum gallium nitride on the epitaxial layer of the non-gate region and the auxiliary structure layer reserved in the gate region or on the epitaxial layer of the non-gate region independently;

c. and etching off the auxiliary structure layer of the gate region to form a gate region by adopting wet etching.

Further, when the epitaxial layer is a gallium nitride layer and a first layer of aluminum gallium nitride, and the auxiliary structure layer is a protective layer and a sacrificial layer, the specific manufacturing process is as follows:

growing a gallium nitride layer, a first layer of aluminum gallium nitride, a protective layer and a sacrificial layer on a substrate from bottom to top in sequence to form a laminated structure;

secondly, defining a gate region on the sacrificial layer by adopting photoetching, and etching off the sacrificial layer of the non-gate region; wet etching is adopted on the protective layer to remove the protective layer of the non-grid area;

growing a second layer of AlGaN on the first layer of AlGaN and the protective layer and the sacrificial layer reserved in the gate region in an epitaxial manner, wherein the thickness of the second layer of AlGaN is larger than that of the sacrificial layer;

grinding the second layer of aluminum gallium nitride by adopting chemical mechanical grinding, grinding the second layer of aluminum gallium nitride until the sacrificial layer is just exposed, wherein the second layer of aluminum gallium nitride of the non-grid region is flush with the sacrificial layer of the grid region;

and fifthly, etching by adopting a wet method, and completely corroding the sacrificial layer and the protective layer of the gate region to form the gate region.

Furthermore, the epitaxial layer is a buffer layer, an intrinsic gallium nitride layer, an aluminum nitride insertion layer and a thin aluminum gallium nitride layer, and when the auxiliary structure layer is a silicon dioxide sacrificial layer, the specific manufacturing process is as follows:

growing a buffer layer, an intrinsic gallium nitride layer, an aluminum nitride insertion layer, a thin aluminum gallium nitride layer and a silicon dioxide sacrificial layer on a substrate from bottom to top in sequence to form a laminated structure;

defining a gate region on the silicon dioxide sacrificial layer by photoetching, and etching off the silicon dioxide sacrificial layer in the non-gate region;

epitaxially growing a second layer of AlGaN on the thin layer of AlGaN in the non-gate region, wherein the thickness of the second layer of AlGaN is less than that of the silicon dioxide sacrificial layer;

completely removing the silicon dioxide sacrificial layer of the gate region to form a gate region by adopting wet etching;

and V, depositing a silicon dioxide dielectric layer on the second layer of aluminum gallium nitride, and manufacturing a grid on the grid region.

The technical scheme adopted by the invention has the advantages that:

1. the invention has free design, and can design the thickness of the aluminum gallium nitride of the grid region and the non-grid region according to the requirements of the device characteristics; the process flow is simple, complex etching and patterning processes are not needed, accurate control of etching is not needed, the groove gate structure is realized from bottom to top, and meanwhile, accurate thickness control of the barrier layer can be realized; the wet etching reduces etching damage, the first epitaxial growth interface defect can be repaired by twice epitaxial AlGaN, and the wet etching silicon dioxide has high selection ratio and self-termination effect. According to the invention, the silicon dioxide auxiliary structure layer is introduced in the manufacturing process of the high electron mobility transistor, and the silicon dioxide structure layer is removed through a subsequent wet process to form the groove gate structure.

2. Compared with the cascade mode, the application of the auxiliary structure layer does not need to be cascaded with a metal oxide semiconductor field effect transistor, so the technical defect of the invention is avoided; compared with a grid groove etching mode, the etching of the aluminum gallium nitrogen with the specified thickness is not needed, and the aluminum gallium nitrogen thickness of the grid region is directly determined by the aluminum gallium nitrogen thickness of the first epitaxial growth, so that the problems that the etching thickness is difficult to control, the etching end point is difficult to monitor and the like are solved; compared with a fluorine ion implantation method, the method avoids the influence of ions easy to migrate, thereby having better reliability; compared with p-type gallium nitride, the method avoids magnesium doping, so that the problem of low activation efficiency of magnesium impurities does not exist. In addition, the AlGaN of the gate region determines the threshold voltage, the AlGaN thickness of the non-gate region determines the on-resistance, the two thicknesses can be freely designed, and higher threshold voltage and lower on-resistance can be obtained simultaneously.

3. The traditional mode of growing and etching the gate groove first is not adopted in the groove manufacturing process, and the mode has the defects that the thickness of the aluminum gallium nitrogen remained after etching is difficult to control accurately and etching damage is easily caused. The invention adopts a mode of directly growing a groove, firstly deposits and patterns a thicker silicon dioxide sacrificial layer structure in a grid region, then epitaxially grows an aluminum gallium nitride material on the top, and finally removes the silicon dioxide sacrificial layer by wet etching by adopting a metal peeling-like principle to realize a grid groove structure.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a schematic process flow diagram of a first embodiment of the present invention;

FIG. 2 is a schematic process flow diagram of a second embodiment of the present invention.

The labels in the above figures are respectively: 1-a substrate; 2-an epitaxial layer; 21-a gallium nitride layer; 22-a first aluminum gallium nitride layer; (ii) a 3. An auxiliary structural layer; 31-a protective layer; 32-a sacrificial layer; 4-second layer of AlGaN; 5-gate region.

Detailed Description

In the present invention, it is to be understood that the term "length"; "Width"; "Up"; "Down"; "front"; "Back"; "left"; "Right"; "vertical"; "horizontal"; "Top"; "bottom" "inner"; "outer"; "clockwise"; "counterclockwise"; "axial"; "planar direction"; "circumferential" and the like indicate orientations or positional relationships that are based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the indicated device or element must have a particular orientation; constructed and operative in a particular orientation and therefore should not be construed as limiting the invention.

As shown in fig. 1 and fig. 2, a manufacturing structure of an enhanced gan high electron mobility transistor includes a substrate 1, an epitaxial layer 2, an auxiliary structure layer 3, and a second layer of aluminum gallium nitride 4, where the epitaxial layer 2 is grown on the substrate 1, the auxiliary structure layer 3 is grown on the epitaxial layer 2, a gate region 5 is defined on the auxiliary structure layer 3 by lithography, the auxiliary structure layer 3 in a non-gate region is etched away, and the second layer of aluminum gallium nitride 4 is grown on the epitaxial layer 2 in the non-gate region and the auxiliary structure layer 3 remaining in the gate region or on the epitaxial layer 2 in the non-gate region alone. By introducing the auxiliary structure into the gate region of the high-mobility transistor, the manufacturing structure and the manufacturing process of the groove gate are optimized, the problems that the etching thickness is difficult to control, the etching end point is difficult to monitor and the like are solved, and the reliability is higher.

In the first embodiment of the present invention, the epitaxial layer 2 includes a gallium nitride layer 21 and a first layer of aluminum gallium nitride 22, the auxiliary structure layer 3 includes a protective layer 31 and a sacrificial layer 32, and the gallium nitride layer 21, the first layer of aluminum gallium nitride 22, the protective layer 23 and the sacrificial layer 24 form a stacked structure. A gallium nitride layer 21 is grown on the substrate 1, a first layer of aluminum gallium nitride 22 is grown on the gallium nitride layer 21, a protective layer 31 is grown on the first layer of aluminum gallium nitride 22, and a sacrificial layer 32 is grown on the protective layer 31.

The enhanced gallium nitride formed by the first embodiment comprises a substrate 1, a gallium nitride layer 21, a first layer of aluminum gallium nitride 22, a second layer of aluminum gallium nitride 4 and a gate region 35, wherein the second layer of aluminum gallium nitride 254 and the gate region 5 are arranged on the first layer of aluminum gallium nitride 22, the gate region 5 is located in the middle, and the second layer of aluminum gallium nitride 4 is located on two sides of the gate region 5.

The material of the protection layer 31 is aluminum nitride or silicon nitride, the material of the sacrificial layer 32 is silicon nitride or aluminum nitride, generally, when the protection layer 31 is aluminum nitride, the sacrificial layer 32 is silicon nitride, and when the protection layer 31 is silicon nitride, the sacrificial layer 32 is aluminum nitride; the dry etching selection ratio of the sacrificial layer 32 to the protective layer 31 is more than 100, and the wet etching selection ratio of the protective layer to the aluminum gallium nitride layer and the sacrificial layer is more than 100.

And epitaxially growing a gallium nitride layer, a first aluminum gallium nitride layer, a protective layer and a sacrificial laminated layer structure on a substrate, wherein the substrate can be single crystal gallium nitride, silicon carbide or silicon and the like. Preferably, one or several buffer layers can be inserted in the stack to absorb the stress and obtain good epitaxial layer quality. The protective layer can be made of materials such as aluminum nitride and silicon nitride, the sacrificial layer can be made of materials such as silicon nitride or aluminum nitride, and the buffer layer can be arranged between any layers according to actual requirements.

The sacrificial layer and the protective layer need to have a relatively high dry etching selection ratio, preferably, the dry etching selection ratio of the sacrificial layer 32 to the protective layer 31 is more than 100; the protective layer, the AlGaN layer and the sacrificial layer need to have high wet etching selection ratio, and preferably, the wet etching selection ratio of the protective layer, the AlGaN layer and the sacrificial layer is more than 100. The sacrificial layer can be used as a substrate for epitaxial AlGaN.

Defining a gate region on the sacrificial layer 32 by adopting photoetching, and etching off the sacrificial layer of the non-gate region; wet etching is used to remove the protective layer in the non-gate region on the protective layer 31. And epitaxially growing a second layer of AlGaN 4 on the first layer of AlGaN 22 and the protective layer sacrificial layer reserved in the gate region.

The thickness of the first layer of gallium nitride 21 is selected according to the design of a device, and the thickness of the second layer of aluminum gallium nitride determines the thickness of the gate region of aluminum gallium nitride, influences the threshold voltage and needs to be reasonably designed. The protective layer is typically relatively thin, and may be chosen to be 3 nm. The sum of the thickness of the sacrificial layer, the thickness of the protective layer and the thickness of the AlGaN determines the thickness of the AlGaN in the non-gate region, influences the on-resistance, and needs to reasonably design the thickness of the sacrificial layer.

The thickness of the second layer of AlGaN 4 is greater than the thickness of the protective layer 31 and the sacrificial layer 32, preferably greater than 20 nm. The second layer of AlGaN 4 with the same thickness is arranged by taking the top surfaces of the first layer of AlGaN 22 and the sacrificial layer 32 as reference surfaces, the second layer of AlGaN 4 is of a concave-convex structure, the protective layer 31 and the sacrificial layer 32 reserved in the gate region are embedded in the concave part of the second layer of AlGaN 4, and the convex part of the second layer of AlGaN 4 is arranged above the second layer of AlGaN 4, which is opposite to the protective layer 31 and the sacrificial layer 32 in the gate region.

And grinding the second layer of AlGaN 4 by adopting chemical mechanical grinding, wherein the second layer of AlGaN 4 is ground to expose the sacrificial layer or grind off the sacrificial layer with a certain thickness, and if the sacrificial layer with a certain thickness is ground off, the thickness of the sacrificial layer needs to be properly increased in the first step. The second layer of AlGaN 4 of the non-gate region is flush with the sacrificial layer 32 of the gate region.

And (3) completely corroding the sacrificial layer and the protective layer of the gate region by adopting wet etching, and reserving the second aluminum gallium nitride layer 25 of the non-gate region. And finishing subsequent processes, namely forming the enhanced gallium nitride by conventional process steps including gate, source-drain metallization, passivation protection and the like.

The invention adopts a sacrificial layer and a chemical mechanical grinding mode to form an aluminum gallium nitrogen groove of a gate region, thereby preparing an enhanced gallium nitride high electron mobility transistor; the design is free, and the thickness of the aluminum gallium nitride of a grid region and a non-grid region can be designed according to the requirements of device characteristics, so that the optimized threshold voltage and the optimized on-resistance can be obtained simultaneously; secondly, a certain material with a specified thickness is not etched, so that the uniformity and the yield of the device are easily improved; the direct dry etching on the aluminum gallium nitrogen layer is avoided, so that the problem that the aluminum gallium nitrogen interface characteristic is poor and two-dimensional electron gas is influenced due to plasma bombardment is avoided; fourthly, the second AlGaN layer extends to repair the surface damage of the first AlGaN layer caused by the preorder process; fifth, easy-to-migrate atoms such as fluorine and magnesium are not doped, and the reliability of the device is better.

In a second embodiment of the invention, the epitaxial layer 2 comprises a buffer layer 23, an intrinsic gallium nitride layer 24, an aluminum nitride insertion layer 25 and a thin layer of aluminum gallium nitride 26, the buffer layer 23 being grown on the substrate 1, the intrinsic gallium nitride layer 24 being grown on the buffer layer 23, the aluminum nitride insertion layer 25 being grown on the intrinsic gallium nitride layer 24 and the thin layer of aluminum gallium nitride 26 being grown on the aluminum nitride insertion layer 25.

The auxiliary structure layer 3 is a silicon dioxide sacrificial layer, a silicon dioxide sacrificial layer grows on the thin aluminum gallium nitride layer 26, and the buffer layer 23, the intrinsic gallium nitride layer 24, the aluminum nitride insertion layer 25, the thin aluminum gallium nitride layer 26 and the silicon dioxide sacrificial layer form a laminated structure.

On the substrate 1, a buffer layer 23, an intrinsic gallium nitride layer 24, an aluminum nitride insertion layer 25, a thin aluminum gallium nitride 26 and a silicon dioxide sacrificial layer are grown in sequence from bottom to top to form a stacked structure. And defining a gate region on the silicon dioxide sacrificial layer by photoetching, and etching off the silicon dioxide sacrificial layer in the non-gate region. Epitaxially growing a second layer of AlGaN 4 on the thin layer of AlGaN 26 of the non-gate region, wherein the thickness of the second layer of AlGaN 4 is less than that of the silicon dioxide sacrificial layer; at this time, a small amount of thin aluminum gallium nitride can be attached to the surface of the silicon dioxide, but due to the lattice mismatch between the silicon dioxide and the aluminum gallium nitride, and the thickness of the epitaxially grown aluminum gallium nitride is very thin, the structure is loose, and the internal silicon dioxide structure layer can be further removed through the aluminum gallium nitride. Removing the silicon dioxide sacrificial layer part by adopting wet etching to expose the grid electrode sunken area; and finishing the subsequent processes including conventional process steps of gate, source drain metallization, passivation protection and the like.

The traditional mode of growing and etching the gate groove first is not adopted in the groove manufacturing process, and the mode has the defects that the thickness of the aluminum gallium nitrogen remained after etching is difficult to control accurately and etching damage is easily caused. The invention adopts a mode of directly growing a groove, firstly deposits and patterns a thicker silicon dioxide sacrificial layer structure in a grid region, then epitaxially grows an aluminum gallium nitride material on the top, and finally removes the silicon dioxide sacrificial layer by wet etching by adopting a metal peeling-like principle to realize a grid groove structure.

The buffer layer is used for balancing stress and reducing the defects of the intrinsic gallium nitride layer; the intrinsic gallium nitride layer (channel layer) is the key for generating two-dimensional electron gas, and the two-dimensional electron gas is generated through spontaneous polarization effect and piezoelectric polarization effect at the interface of the aluminum gallium nitride and the intrinsic gallium nitride. Two-dimensional electron gas is generated on one side of the interface intrinsic gallium nitride, and because the intrinsic gallium nitride layer does not contain impurities, the scattering effect is small, and the electron mobility can be improved.

The aluminum nitride insertion layer is arranged at the heterojunction of the aluminum gallium nitride and the gallium nitride, and the gallium nitride channel layer and the aluminum gallium nitride barrier layer are inserted into the very thin aluminum nitride space insertion layer to reduce the scattering effect of the aluminum gallium nitride and further improve the mobility.

The thin aluminum gallium nitride layer is an aluminum gallium nitride layer reserved on the lower side of the concave grid, and numerous documents prove that the optimal regulation and control effect of the grid on a channel can be realized by reserving the thin aluminum gallium nitride layer (nm level) in a grid region. The aluminum nitride insertion layer is arranged between the thin aluminum gallium nitrogen layer and the aluminum gallium nitrogen barrier layer, plays a role in stopping etching, and the thin layer does not influence the whole stress, so that the effect of two-dimensional electron gas generated by the intrinsic gallium nitride channel layer on the upper aluminum gallium nitrogen barrier layer through spontaneous polarization and piezoelectric polarization is not influenced

Aluminum gallium nitrogen barrier layer (i.e. second layer of aluminum gallium nitrogen): the existence of the two-dimensional electron gas is mainly influenced by the barrier layer, and the aluminum composition and thickness of the aluminum gallium nitride influence the polarization electric field, so that the concentration of the two-dimensional electron gas is influenced. The aluminum oxide dielectric layer plays a role of a grid dielectric and a passivation role.

The structure of the invention improves the concentration of two-dimensional electron gas, enhances the control of the grid, simplifies the process flow and realizes accurate etching self-stop. The etching stop position is accurately controlled by inserting the thin aluminum nitride barrier layer, and the optimal channel control can be realized by the thin aluminum gallium nitride below the aluminum nitride barrier layer through the grid; meanwhile, the aluminum nitride layer is deposited in the whole area, and the aluminum nitride layer does not need to be patterned by photoetching, so that the process is simplified; meanwhile, the piezoelectric polarization effect of the aluminum gallium nitrogen barrier layer with the thicker upper layer cannot be influenced by the thin aluminum nitride, the spontaneous polarization direction of the aluminum nitride is consistent with that of the aluminum gallium nitrogen, the integral polarization effect is enhanced, the concentration of two-dimensional electron gas is improved, and the device performance is improved.

The invention also relates to a manufacturing process of the enhanced gallium nitride high electron mobility transistor, which is based on the manufacturing structure of the enhanced gallium nitride high electron mobility transistor and comprises the following steps:

a. growing a substrate 1, growing an epitaxial layer 2 on the substrate 1, and growing an auxiliary structure layer 3 on the epitaxial layer 2;

b. defining a gate region 5 on the auxiliary structure layer 3 by photoetching, etching off the auxiliary structure layer 3 in a non-gate region, and growing a second layer of AlGaN 4 on the epitaxial layer 2 in the non-gate region and the auxiliary structure layer 3 reserved in the gate region or on the epitaxial layer 2 in the non-gate region independently;

c. etching off the auxiliary structure layer 3 of the gate region by wet etching to form a gate region; and finishing the subsequent processes including conventional process steps of gate, source drain metallization, passivation protection and the like.

When the epitaxial layer 2 is the gallium nitride layer 21 and the first layer of aluminum gallium nitride 22, and the auxiliary structure layer 3 is the protective layer 31 and the sacrificial layer 32, the specific manufacturing process is as follows:

firstly, growing a gallium nitride layer 21, a first layer of aluminum gallium nitride 22, a protective layer 31 and a sacrificial layer 32 on a substrate 1 from bottom to top in sequence to form a laminated structure;

secondly, defining a gate region on the sacrificial layer 32 by adopting photoetching, and etching off the sacrificial layer of the non-gate region; wet etching is adopted on the protective layer 31 to remove the protective layer of the non-grid area;

growing a second layer of AlGaN 4 on the first layer of AlGaN 22 and the protective layer 31 and the sacrificial layer 32 reserved in the gate region in an epitaxial manner, wherein the thickness of the second layer of AlGaN 4 is greater than that of the sacrificial layer;

grinding the second layer of AlGaN 4 by adopting chemical mechanical grinding, grinding the second layer of AlGaN 4 until the sacrificial layer is just exposed, wherein the second layer of AlGaN 4 in the non-gate region is flush with the sacrificial layer 32 in the gate region;

fifthly, adopting wet etching to completely corrode the sacrificial layer and the protective layer of the gate region to form the gate region; and finishing the subsequent processes including conventional process steps of gate, source drain metallization, passivation protection and the like.

When the epitaxial layer 2 is the buffer layer 23, the intrinsic gallium nitride layer 24, the aluminum nitride insertion layer 25 and the thin aluminum gallium nitride layer 26, and the auxiliary structure layer 3 is the silicon dioxide sacrificial layer, the specific manufacturing process is as follows:

i, growing a buffer layer 23, an intrinsic gallium nitride layer 24, an aluminum nitride insertion layer 25, a thin-layer aluminum gallium nitride 26 and a silicon dioxide sacrificial layer on a substrate 1 from bottom to top in sequence to form a laminated structure;

defining a gate region on the silicon dioxide sacrificial layer by photoetching, and etching off the silicon dioxide sacrificial layer in the non-gate region;

epitaxially growing a second layer of AlGaN 4 on the thin layer of AlGaN 26 of the non-gate region, wherein the thickness of the second layer of AlGaN 4 is less than that of the silicon dioxide sacrificial layer;

completely removing the silicon dioxide sacrificial layer of the gate region to form a gate region by adopting wet etching;

depositing a silicon dioxide dielectric layer 6 on the second layer of AlGaN 4, and manufacturing a grid 7 on the grid region; and finishing the subsequent processes including conventional process steps of gate, source drain metallization, passivation protection and the like.

The invention has free design, and can design the thickness of the aluminum gallium nitride of the grid region and the non-grid region according to the requirements of the device characteristics; the process flow is simple, complex etching and patterning processes are not needed, accurate control of etching is not needed, the groove gate structure is realized from bottom to top, and meanwhile, accurate thickness control of the barrier layer can be realized; the wet etching reduces etching damage, the first epitaxial growth interface defect can be repaired by twice epitaxial AlGaN, and the wet etching silicon dioxide has high selection ratio and self-termination effect. According to the invention, the silicon dioxide auxiliary structure layer is introduced in the manufacturing process of the high electron mobility transistor, and the silicon dioxide structure layer is removed through a subsequent wet process to form the groove gate structure.

Compared with the cascade mode, the application of the auxiliary structure layer does not need to be cascaded with a metal oxide semiconductor field effect transistor, so the technical defect of the invention is avoided; compared with a grid groove etching mode, the etching of the aluminum gallium nitrogen with the specified thickness is not needed, and the aluminum gallium nitrogen thickness of the grid region is directly determined by the aluminum gallium nitrogen thickness of the first epitaxial growth, so that the problems that the etching thickness is difficult to control, the etching end point is difficult to monitor and the like are solved; compared with a fluorine ion implantation method, the method avoids the influence of ions easy to migrate, thereby having better reliability; compared with p-type gallium nitride, the method avoids magnesium doping, so that the problem of low activation efficiency of magnesium impurities does not exist. In addition, the AlGaN of the gate region determines the threshold voltage, the AlGaN thickness of the non-gate region determines the on-resistance, the two thicknesses can be freely designed, and higher threshold voltage and lower on-resistance can be obtained simultaneously.

The invention is described above with reference to the accompanying drawings, it is obvious that the specific implementation of the invention is not limited by the above-mentioned manner, and it is within the scope of the invention to adopt various insubstantial modifications of the technical solution of the invention or to apply the concept and technical solution of the invention directly to other occasions without modification.

Claims (9)

1. A manufacturing structure of an enhanced gallium nitride high electron mobility transistor is characterized in that: including substrate (1), epitaxial layer (2), auxiliary structure layer (3) and second floor aluminium gallium nitrogen (4), epitaxial layer (2) grow on substrate (1), and auxiliary structure layer (3) grow on epitaxial layer (2), photoetching definition bars district (5) on auxiliary structure layer (3), etch off auxiliary structure layer (3) of non-bars district, grow second floor aluminium gallium nitrogen (4) on epitaxial layer (2) of non-bars district or alone on epitaxial layer (2) of non-bars district on epitaxial layer (2) that epitaxial layer (2) and bars district remain of non-bars district.

2. The fabricated structure of an enhancement mode gan hemt according to claim 1, wherein: the epitaxial layer (2) comprises a gallium nitride layer (21) and a first layer of aluminum gallium nitride (22), the auxiliary structure layer (3) comprises a protective layer (31) and a sacrificial layer (32), and the gallium nitride layer (21), the first layer of aluminum gallium nitride (22), the protective layer (31) and the sacrificial layer (32) form a laminated structure.

3. The structure of claim 2, wherein: the gallium nitride layer (21) grows on the substrate (1), the first layer of aluminum gallium nitride (22) grows on the gallium nitride layer (21), the protective layer (31) grows on the first layer of aluminum gallium nitride (22), and the sacrificial layer (32) grows on the protective layer (31).

4. The fabricated structure of an enhancement mode gan hemt according to claim 3, wherein: the protective layer (31) is made of aluminum nitride or silicon nitride, the sacrificial layer (32) is made of silicon nitride or aluminum nitride, the dry etching selection ratio of the sacrificial layer (32) to the protective layer (31) is more than 100, and the wet etching selection ratio of the protective layer to the aluminum gallium nitride layer and the sacrificial layer is more than 100.

5. The fabricated structure of an enhancement mode gan hemt according to claim 1, wherein: the epitaxial layer (2) comprises a buffer layer (23), an intrinsic gallium nitride layer (24), an aluminum nitride insertion layer (25) and a thin-layer aluminum gallium nitride (26), wherein the buffer layer (23) grows on the substrate (1), the intrinsic gallium nitride layer (24) grows on the buffer layer (23), the aluminum nitride insertion layer (25) grows on the intrinsic gallium nitride layer (24), and the thin-layer aluminum gallium nitride (26) grows on the aluminum nitride insertion layer (25).

6. The fabricated structure of an enhancement mode gan hemt according to claim 5, wherein: the auxiliary structure layer (3) is a silicon dioxide sacrificial layer, the silicon dioxide sacrificial layer grows on the thin-layer AlGaN (26), and the buffer layer (23), the intrinsic gallium nitride layer (24), the aluminum nitride insertion layer (25), the thin-layer AlGaN (26) and the silicon dioxide sacrificial layer form a laminated structure.

7. A manufacturing process of an enhanced gallium nitride high electron mobility transistor is characterized in that: the structure of any one of claims 1 to 6, wherein the process comprises:

a. growing a substrate (1), growing an epitaxial layer (2) on the substrate (1), and growing an auxiliary structure layer (3) on the epitaxial layer (2);

b. defining a gate region (5) on the auxiliary structure layer (3) by adopting photoetching, etching off the auxiliary structure layer (3) of the non-gate region, and growing a second layer of aluminum gallium nitride (4) on the epitaxial layer (2) of the non-gate region and the auxiliary structure layer (3) reserved in the gate region or on the epitaxial layer (2) of the non-gate region independently;

c. and etching the auxiliary structure layer (3) of the gate region by adopting wet etching to form the gate region.

8. The process of claim 7, wherein the process comprises: when epitaxial layer (2) are gallium nitride layer (21) and first layer aluminium gallium nitrogen (22), auxiliary structure layer (3) are protective layer (31) and sacrificial layer (32), the concrete manufacturing process is:

growing a gallium nitride layer (21), a first layer of aluminum gallium nitride (22), a protective layer (31) and a sacrificial layer (32) on a substrate (1) from bottom to top in sequence to form a laminated structure;

secondly, defining a gate region on the sacrificial layer (32) by adopting photoetching, and etching off the sacrificial layer of the non-gate region; wet etching is adopted on the protective layer (31) to remove the protective layer of the non-grid area;

thirdly, epitaxially growing a second layer of aluminum gallium nitride (4) on the first layer of aluminum gallium nitride (22) and the protective layer (31) and the sacrificial layer (32) reserved in the gate region, wherein the thickness of the second layer of aluminum gallium nitride (4) is larger than that of the sacrificial layer;

grinding the second layer of AlGaN (4) by adopting chemical mechanical grinding, grinding the second layer of AlGaN (4) until the sacrificial layer is just exposed, and enabling the second layer of AlGaN (4) in the non-gate region to be flush with the sacrificial layer (32) in the gate region;

and fifthly, etching by adopting a wet method, and completely corroding the sacrificial layer and the protective layer of the gate region to form the gate region.

9. The process of claim 7, wherein the process comprises: the epitaxial layer (2) is a buffer layer (23), an intrinsic gallium nitride layer (24), an aluminum nitride insertion layer (25) and a thin-layer AlGaN (26), and when the auxiliary structure layer (3) is a silicon dioxide sacrificial layer, the specific manufacturing process is as follows:

growing a buffer layer (23), an intrinsic gallium nitride layer (24), an aluminum nitride insertion layer (25), a thin aluminum gallium nitride (26) and a silicon dioxide sacrificial layer on a substrate (1) from bottom to top in sequence to form a laminated structure;

defining a gate region on the silicon dioxide sacrificial layer by photoetching, and etching off the silicon dioxide sacrificial layer in the non-gate region;

epitaxially growing a second layer of AlGaN (4) on the thin layer of AlGaN (26) in the non-gate region, wherein the thickness of the second layer of AlGaN (4) is less than that of the silicon dioxide sacrificial layer;

completely removing the silicon dioxide sacrificial layer of the gate region to form a gate region by adopting wet etching;

and V, depositing a silicon dioxide dielectric layer (6) on the second layer of AlGaN (4) and manufacturing a grid on the grid region.

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