CN112736130A

CN112736130A - Gallium nitride based high electron mobility transistor and manufacturing method thereof

Info

Publication number: CN112736130A
Application number: CN202011644255.3A
Authority: CN
Inventors: 毛维; 刘晓雨; 杨翠; 高北鸾; 王海永; 杜鸣; 马佩军; 张进成; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-04-30

Abstract

The invention discloses a gallium nitride-based high-electron-mobility transistor and a manufacturing method thereof, and mainly solves the problems that an existing gallium nitride-based device has current collapse and is complex in process when high breakdown voltage is realized. It includes: the device comprises a substrate (1), a transition layer (2) and a barrier layer (3); the left side edge of the barrier layer is provided with an active groove (7), the upper part of the active groove is deposited with a source electrode (9), the right side edge of the barrier layer is provided with a drain groove (8), the upper part of the drain groove is deposited with a drain contact (10), the upper part of the barrier layer is provided with a gate island (4), and the upper part of the barrier layer is deposited with a gate electrode (14); a floating island (5) and a drain island (6) are arranged on the barrier layer on the right side of the gate island, floating island metal (11) is deposited on the upper portion of the floating island, drain island metal (12) is deposited on the upper portion of the drain island, a groove (13) is arranged between the floating island and the drain contact, and Schottky contact (15) is deposited on the inner portion and the upper portion of the groove. The invention has good forward blocking and reverse blocking, strong current collapse inhibition and can be used as a basic device of a high-reliability power electronic system.

Description

Gallium nitride based high electron mobility transistor and manufacturing method thereof

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a gallium nitride-based high-electron-mobility transistor which can be used as a basic device of a power electronic system.

Technical Field

The power electronic system is widely applied to the fields of aerospace, industrial equipment, electric automobiles, household appliances and the like, and the power device is an important element of the power electronic system and is an important tool for realizing energy conversion and control. Therefore, the performance and reliability of the power device have a decisive influence on various technical indexes and performances of the whole power electronic system.

At present, the performance of Si-based and GaAs-based semiconductor power devices approaches the theoretical limit. In order to break through the research and development bottleneck of the current semiconductor power device and further improve the performance of a power system, the gallium nitride (GaN) heterojunction-based high-electron-mobility transistor has the advantages of good high-temperature resistance, high switching speed, low on resistance, high working frequency, high voltage resistance and the like, and can meet the requirements of next-generation power electronic equipment on higher power, higher frequency, smaller volume and worse high-temperature work of the power device, so that the gallium nitride (GaN) heterojunction-based high-electron-mobility transistor has a wide application prospect.

The traditional GaN-based HEMT power device is based on a GaN-based heterojunction structure, and comprises: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a gate column 5 and a protective layer 8; a source 5 is deposited on the left side above the barrier layer 3, a drain 6 is deposited on the right side above the barrier layer 3, a P-type layer 4 is epitaxially deposited on the barrier layer 3 between the source 5 and the drain 6, a gate 7 is deposited on the P-type layer 4, and a protective layer 8 completely covers the barrier layer 3, the P-type layer 4, the source 5, the drain 6 and the region above the gate 7, as shown in fig. 1.

When a traditional GaN-based HEMT power device works, the electric field distribution in a semiconductor between a grid and a drain of the device is extremely uneven, and an extremely high electric field is formed near the grid and the drain, so that the reliability problems of Current Collapse and the like of the device occur, and the practical application of the device is seriously influenced, which is shown in tracking Effects on Leakage and Current collagen in AlGaN/GaN HEMTs, Electronic Materials,2020,49(10): 5687-. In order to effectively inhibit the current collapse effect, researchers have conducted a variety of research and exploration with great success. Liu Jing et al, by introducing a partial groove structure of a barrier layer into a GaN-based power device, reduce the electric field peak value at the edge drain side of a gate, and effectively inhibit the Current collapse effect under the bias of 20V drain compressive stress, see Current collepse application in AlGaN/GaN high electron mobility transistor with groove structure, Acta Phys.sin,2019(24) 248501. But the introduction of the grooves can lose part of the two-dimensional electron gas, so that the on-resistance of the device is increased. In order to improve the device characteristics, Nishitani et al adopts a gate-source dual Field plate structure, and weakens the electric Field near the edge of the drain electrode through the Field plate, so as to effectively inhibit Current Collapse under the drain bias of 100V, see Improved Current Collapse in AlGaN/GaN MOSHEMs with dual Field-Plates, IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK),21-22June 2018. However, the field plate structure has a complicated process, and increases the device capacitance, thereby attenuating the frequency characteristics of the device. The Sheng Gao et al introduces NiO into the device_X/SiN_XOr Al₂O₃/SiN_XThe passivation layer effectively inhibits current collapse under 200V stress biasSee Breakdown Enhancement and Current Collapse Suppression in AlGaN/GaN HEMT by NiOx/SiNx and Al₂O₃the/SiNx as Gate Dielectric Layer and Passivation Layer, IEEE Electron Device Letters,2019,40(12): 1921-. However, the passivation process has poor repeatability, and can only suppress current collapse at a relatively low bias voltage, and when the device is biased at a high voltage, the current collapse is still very serious.

Disclosure of Invention

The present invention aims to overcome the defects of the prior art, and provide a gallium nitride-based high electron mobility transistor and a manufacturing method thereof, so as to suppress the current collapse effect of a device, improve the breakdown voltage of the device, reduce the forward turn-on voltage drop of the device, reduce the manufacturing complexity of the device, and improve the reliability of the device.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

1. a gallium nitride-based high electron mobility transistor comprising, from bottom to top: substrate 1, transition layer 2, barrier layer 3, the left side edge of barrier layer 3 is equipped with active groove 7, and its upper portion deposit has source 9, and the right side edge of barrier layer 3 is equipped with small groove 8, and its upper portion deposit has the drain contact 10, and the upper portion of barrier layer 3 is equipped with gate island 4, and its upper portion deposit has grid 14, its characterized in that:

a floating island 5 and a drain island 6 are sequentially arranged on the barrier layer 3 on the right side of the gate island 4, floating island metal 11 is deposited on the upper part of the floating island 5, drain island metal 12 is deposited on the upper part of the drain island 6, a groove 13 is arranged between the floating island 6 and a drain contact 10, and Schottky contacts 15 are deposited inside and on the upper part of the groove;

the floating island 5 comprises 2n-1 independent P-type semiconductor blocks with the same size, the nth independent P-type semiconductor block is used as the center and is correspondingly arranged left and right, and n is more than or equal to 1;

the height of the drain island 6 is the same as the height f of each independent P-type semiconductor block in the floating island 5, the drain island comprises m P-type semiconductor cuboid blocks, and m is more than or equal to 1;

the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12, the gate electrode 14 and the Schottky contact 15 are all wrapped by a passivation layer 16.

Preferably, the height h of the barrier layer 3 is 5to 100 nm; the height g of the gate island 4 is 5-500 nm, and the doping concentration is 4 multiplied by 10¹⁵～5×10²⁰cm^-3。

Preferably, the width t and the height f of each independent P-type semiconductor block in the floating island 5 are the same, the value of t is 0.2-10 μm, the value of f is 1-400 nm, and f is smaller than the height g of the gate island 4; the doping concentration of each P-type semiconductor block was 4X 10¹⁵～5×10²⁰cm^-3。

Preferably, the drain island 6 is composed of m P-type semiconductor rectangular blocks with equal spacing, the spacing j is 0.1-40 μm, m is more than or equal to 1, the width a of each rectangular block is 0.2-50 μm, the length b is 0.1-50 μm, the height f is 1-400 nm, and the doping concentration of each P-type semiconductor block is 4 x 10¹⁵～5×10²⁰cm^-3。

Preferably, the width c of the groove 13 is 0.2 μm to 10 μm, and the depth e is 1nm to 150 nm.

Preferably, the floating island 5 is centered on the nth independent P-type semiconductor block, and the distance between the left first independent P-type semiconductor block and the gate island 4 is M₁The second independent P-type semiconductor block is spaced from the first independent P-type semiconductor block by a distance M₂And by analogy, the distance between the nth independent P-type semiconductor block and the (n-1) th independent P-type semiconductor block on the left side is M_nAnd 0.1 μ M or less of M₁<M₂<...<M_nLess than or equal to 10 mu m; on the right side of the nth independent P-type semiconductor block, the distance between the 1 st independent P-type semiconductor block and the drain island 6 is N₁The distance between the 2 nd independent P-type semiconductor block and the 1 st independent P-type semiconductor block is N₂And by analogy, the distance between the nth independent P-type semiconductor block on the right side and the (N-1) th independent P-type semiconductor block is N_nAnd 0.1 μm or less of N₁<N₂<...<N_n≤10μm，n≥1。

Preferably, the floating island metal 11 and the drain island metal 12 are the same, and both adopt a multi-layer metal combination, and the work function of the lowest layer metal is less than or equal to 5.15 eV.

2. A method for manufacturing a gallium nitride-based high electron mobility transistor is characterized by comprising the following steps:

A) a GaN-based wide bandgap semiconductor material is epitaxially grown on a substrate 1 by adopting a metal organic chemical vapor deposition technology to form a transition layer 2 with the thickness of 1-9 mu m;

B) extending a GaN-based wide bandgap semiconductor material on the transition layer 2 by adopting a metal organic chemical vapor deposition technology to form a barrier layer 3 with the thickness of 5-100 nm;

C) a P-type GaN semiconductor material is epitaxially formed on the barrier layer 3 by adopting a metal organic chemical vapor deposition technology to form a GaN semiconductor layer with the thickness of 5-500 nm and the doping concentration of 4 multiplied by 10¹⁵～5×10²⁰cm^-3A P-type layer of (a);

D) manufacturing a gate island 4, a floating island 5 and a drain island 6:

D1) manufacturing a mask on the P-type layer for the first time, and etching the P-type layer on two sides by using the mask, wherein the etching depth is i, and i is g-f;

D2) continuing to use the mask in D1), making a mask on the P-type layer for the second time, simultaneously etching by using the mask and the mask in the step D1) until the upper surface of the barrier layer 3 is etched to form a gate island 4, a floating island 5 and a drain island 6;

E) manufacturing a source electrode 9 and a drain contact 10:

E1) making masks on the barrier layer 3, the gate island 4, the floating island 5 and the drain island 6 for the third time, and etching the left side and the right side of the barrier layer 3 by using the masks to respectively form a source groove 7 and a drain groove 8;

E2) continuously using the mask to deposit Ti/Al/Ni/Au or Ti/Al/Mo/Au or Ti/Al/Ti/Au multilayer metal on the barrier layers 3 at the left and right sides by adopting the electron beam evaporation technology, and depositing the Ti/Al/Ni/Au multilayer metal on the N₂Performing rapid thermal annealing in the atmosphere to complete the manufacture of the source electrode 9 and the drain contact 10;

F) making a mask on the barrier layer 3, the gate island 4, the source electrode 9 and the drain contact 10 for the fourth time, depositing Ta/Ni/Au or Ti/Mo/Au or Cu/Ni/Au multilayer metal on the floating island 5 and the drain island 6 by using the mask by adopting an electron beam evaporation technology, and finishing the making of the floating island metal 11 and the drain island metal 12, wherein the work function of the metal at the lowest layer is less than or equal to 5.15 eV;

G) making a mask on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the fifth time, and etching the barrier layer 3 between the drain island 6 and the drain contact 10 by using the mask to form a groove 13 with the depth of e;

H) making masks on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the sixth time, and depositing Gd/Au or Zr/Pt or Ta/Ni multilayer metal on the upper part of the gate island 4 by using the masks by adopting an electron beam evaporation technology to complete the manufacture of the gate 14;

I) a seventh mask is manufactured on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12 and the grid electrode 14, and Ni or W or Mo single-layer metal is deposited inside and on two sides of the groove 13 by using the mask through an electron beam evaporation technology to complete the manufacture of the Schottky contact 15;

J) and depositing a passivation layer 16 with the thickness of more than or equal to 350nm on the barrier layer 3, the upper parts of the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12, the gate electrode 14 and the Schottky contact 15 and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology to finish the manufacture of the whole device.

Compared with the traditional GaN-based HEMT power device, the device has the following advantages:

firstly, the device adopts the drain island structure, when the device is in forward drain high-voltage bias, a pn junction formed by the drain island and the barrier layer is in a forward conduction state, and the pn junction can inject holes into the device body, so that the capture effect of the internal defects of the device on electrons is inhibited, and the current collapse effect of the device can be effectively inhibited; when the device applies negative drain high-voltage bias, the pn junction formed by the drain island and the barrier layer is in a reverse turn-off state, and a space charge region near the drain can be expanded, so that the reverse withstand voltage capability of the device is improved.

Secondly, the device of the invention adopts the floating island structure, when the device is in a forward blocking state, namely the drain electrode is applied with forward high-voltage bias, a space charge region formed by reverse bias of a pn junction formed by the gate island and the barrier layer of the device can expand to the drain electrode side, and along with the increase of the bias voltage of the drain electrode, the space charge region can expand to a first independent P-type semiconductor block in the floating island from the gate island to the drain electrode direction, so that the space charge region of the reverse bias pn junction formed by the first independent P-type semiconductor block and the barrier layer further expands to the drain electrode direction, and further, a second independent P-type semiconductor block to an nth independent P-type semiconductor block in the gate island to drain electrode direction are connected with the space charge region of the reverse bias pn junction formed by the barrier layer, therefore, the forward blocking voltage of the device can be improved; when the device is in a reverse blocking state, namely when a negative high-voltage bias is applied to a drain electrode, a space charge region formed by reverse bias of a pn junction formed by a drain island and a barrier layer of the device can expand towards one side of a gate island, and along with the increase of the bias voltage of the drain electrode, the space charge region can expand to a first independent P-type semiconductor block in the floating island from the drain electrode to the gate island, so that the space charge region of the reverse bias pn junction formed by the first independent P-type semiconductor block and the barrier layer further expands towards the gate island, and a structure that a second independent P-type semiconductor block in the drain electrode to gate island direction to an nth independent P-type semiconductor block and the space charge region of the reverse bias pn junction formed by the barrier layer are connected together is formed, so that the reverse blocking voltage of the device is improved.

Thirdly, the floating island and the drain island in the device can be manufactured at the same time, and the manufacturing process of the device is simple. In addition, the floating island and the drain island have almost no depletion effect on the current carriers in the channel below the floating island and the drain island, so that the on-resistance of the device cannot be increased.

Drawings

Fig. 1 is a structural view of a conventional GaN-based HEMT power transistor;

FIG. 2 is a block diagram of a gallium nitride based HEMT of the present invention;

FIG. 3 is a top view of a GaN-based HEMT of the present invention;

FIG. 4 is a schematic overall flow chart of the present invention for fabricating a GaN-based HEMT;

FIG. 5 is a graph showing simulation results of current collapse characteristics of a conventional transistor and a transistor according to the present invention;

fig. 6 is a graph showing simulation results of breakdown characteristics of the conventional transistor and the transistor of the present invention.

Detailed Description

Embodiments and effects of the present invention will be described in further detail below with reference to the accompanying drawings.

Referring to fig. 2, the gallium nitride-based high electron mobility transistor given in this example includes: substrate 1, transition layer 2, barrier layer 3, gate island 4, floating island 5, drain island 6, source slot 7, drain slot 8, source 9, drain contact 10, floating island metal 11, drain island metal 12, groove 13, gate 14, schottky contact 15 and passivation layer 16, wherein:

the substrate 1 is made of sapphire, silicon carbide, silicon or graphene;

the transition layer 2 is positioned on the upper part of the substrate 1 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the transition layer is 1-9 mu m;

the barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness of the barrier layer is 5-100 nm;

the gate island 4, the floating island 5 and the drain island 6 are sequentially positioned on the barrier layer 3 from left to right, and the height g of the gate island 4 is 5-500 nm.

The floating island 5 is composed of 2n-1 identical independent P-type semiconductor blocks, n is more than or equal to 1, the n is centered on the nth independent P-type semiconductor block, and the distance between the first independent P-type semiconductor block on the left side of the floating island and the gate island 4 is M₁The second independent P-type semiconductor block is spaced from the first independent P-type semiconductor block by a distance M₂And by analogy, the distance between the nth independent P-type semiconductor block and the (n-1) th independent P-type semiconductor block on the left side is M_nAnd 0.1 μ M or less of M₁<M₂<...<M_nLess than or equal to 10 mu m; on the right side of the nth independent P-type semiconductor block, the distance between the 1 st independent P-type semiconductor block and the drain island 6 is N₁The distance between the 2 nd independent P-type semiconductor block and the 1 st independent P-type semiconductor block is N₂And so on, the nth independent P-type semiconductor block and the (n-1) th independent P-type semiconductor block on the right sideHas a pitch of N_nAnd 0.1 μm or less of N₁<N₂<...<N_nThe width t and the height f of each independent P-type semiconductor block are the same, t is 0.2-10 mu m, f is 1-400 nm, and f is less than the height g of the gate island 4;

the leakage island 6 is composed of m identical P-type semiconductor cuboid blocks, wherein m is more than or equal to 1, the width a of each cuboid block is 0.2-50 mu m, the length b is 0.1-40 mu m, the height is the same as the height f of each independent P-type semiconductor block in the floating island 5, the spacing is j, and j is 0.1-40 mu m, as shown in FIG. 3;

the source groove 7 is positioned at the left edge of the barrier layer 3, a source electrode 9 is deposited on the source groove, and the width L of the source electrode 9₁ 5to 500 μm, a height H₁5to 600 nm; the drain trench 8 is located at the right edge of the barrier layer 3, and has a drain contact 10 deposited thereon, the drain contact 10 having a width L₂5to 500 μm, a height H₂5to 600 nm; the source 9 and drain 10 contacts are each made of a combination of multi-layer metals including but not limited to Ti/Al/Ni/Au, Ti/Al/Mo/Au, and Ti/Al/Ti/Au, and are in N₂Carrying out rapid thermal annealing in the atmosphere;

the floating island metal 11 is positioned at the upper part of the floating island 5, and the height k of the floating island metal is 0.1-1 mu m; the drain island metal 12 is positioned at the upper part of the drain island 6, and the height of the drain island metal is the same as the height k of the floating island metal; the floating island metal 11 and the drain island metal 12 are both made of a multi-layer metal combination, the work function of the lowest layer metal is less than or equal to 5.15eV, and the multi-layer metal is made of Ta/Ni/Au, Ti/Mo/Au and Cu/Ni/Au;

the groove 13 is positioned between the drain island 6 and the drain contact 10, the depth e of the groove is 1-150 nm, Schottky contacts 15 are deposited inside and on the groove 13, the metal is Ni, W and Mo, the width of the lower part of the groove is the same as the width c of the groove 13, and the upper part of the groove partially overlaps with the drain island 6 on the left side, the drain island metal 12 and the drain contact 10 on the right side;

the grid electrode 14 is positioned on the upper part of the grid island 4 and adopts a multi-layer metal combination, and the multi-layer metal adopts Gd/Au, Zr/Pt and Ta/Ni;

the passivation layer 16 with the thickness more than or equal to 350nm completely covers the barrier layer 3, the gate island 4 and the floating island5. The upper parts of the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12, the grid electrode 14 and the Schottky contact 15 and the peripheral area thereof, and the passivation layer 16 adopts SiO₂、SiN、Al₂O₃、Sc₂O₃、HfO₂And TiO₂Or other insulating dielectric material.

Referring to fig. 4, the gallium nitride-based hemt fabricated according to the present invention includes the following three examples.

The first embodiment is as follows: the height f of the floating island 5 and the drain island 6 made of the sapphire substrate is 1nm, and the doping concentration is 4 multiplied by 10¹⁵cm^-3The number of independent P-type semiconductor blocks in the floating island 5 is 1, and the number of semiconductor rectangular solid blocks in the drain island 6 is 1.

Step 1, epitaxial growth of GaN material on sapphire substrate 1 to form transition layer 2, as shown in fig. 4 a.

1a) A GaN material with the thickness of 30nm is epitaxially grown on a sapphire substrate 1 by using a metal organic chemical vapor deposition technology, and the process conditions are as follows: the temperature is 530 ℃, the pressure is 45Torr, the hydrogen flow is 4400sccm, the ammonia flow is 4400sccm, and the gallium source flow is 22 mu mol/min;

1b) GaN material with the thickness of 0.97 mu m is epitaxially grown on the GaN material by using a metal organic chemical vapor deposition technology to form an undoped transition layer 2, and the process conditions are as follows: the temperature was 960 deg.C, the pressure was 45Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, and the gallium source flow was 120. mu. mol/min.

Step 2, depositing undoped Al on the undoped GaN transition layer 2_0.3Ga_0.7N produces the barrier layer 3 as shown in fig. 4 b.

Depositing undoped Al with a thickness of 5nm and an aluminum composition of 0.3 on the GaN transition layer 2 by using a metal organic chemical vapor deposition technique_0.3Ga_0.7The process conditions of the N barrier layer 3 are as follows: the temperature was 980 ℃, the pressure was 45Torr, the hydrogen flow was 4400sccm, the ammonia flow was 4400sccm, the gallium source flow was 35. mu. mol/min, and the aluminum source flow was 7. mu. mol/min.

Step 3. epitaxial P-type layer on barrier layer 3, as shown in fig. 4 c.

Using molecular beam epitaxy technique, the barrier layer 3 is epitaxially grown to a thickness of 5nm and a doping concentration of 4 × 10¹⁵cm^-3Forming a P-type layer.

The process conditions adopted by molecular beam epitaxy are as follows: vacuum degree of 1.0X 10 or less^-10mbar, radio frequency power of 400W, and N as reactant₂And a high purity Ga source.

And 4, manufacturing a gate island 4 with the height of 5nm, a floating island 5 with the height of 1nm and a drain island 6 with the height of 1nm, as shown in figures 4d and 4 e.

4a) Manufacturing a mask on the P-type layer for the first time, etching the two sides of the P-type layer by using a reactive ion etching technology, wherein the etching depth i is 4nm, and the etching adopts the following process conditions: cl₂The flow is 15sccm, the pressure is 10mTorr, and the power is 100W;

4b) making a mask on the P-type layer for the second time, etching simultaneously by using the mask and the mask in the step 4a) until the upper surface of the barrier layer 3, and simultaneously forming a gate island 4 with the height of 5nm, a floating island 5 with the height of 1nm and the width of 0.2 mu M and a drain island 6 with the height of 1nm and the width of 0.2 mu M, wherein the distance M between the floating island 5 and the gate island 4₁0.2 μm, the spacing N between the floating island 5 and the drain island 6₁3 μm, the etching conditions adopted are as follows: cl₂The flow rate is 15sccm, the pressure is 10mTorr, and the power is 100W.

Step 5. make source 9 and drain contact 10, as shown in fig. 4f and 4 g.

5a) Making masks on the barrier layer 3, the gate island 4, the floating island 5 and the drain island 6 for the third time, etching the left side and the right side of the barrier layer 3 by using the masks until the upper surface of the transition layer 2 is etched, and respectively forming a source groove 7 and a drain groove 8 with the depths of 5nm, wherein the etching adopts the following process conditions: cl₂The flow is 15sccm, the pressure is 10mTorr, and the power is 100W;

5b) continuously using the mask to deposit multiple layers of metal on the left and right barrier layers 3 by electron beam evaporation, wherein the deposited metal adopts Ti/Al/Ni/Au metal combination, i.e. Ti, Al, Ni and Au are respectively arranged from bottom to top, and the thickness of the deposited metal is 0.001 μm// 5 μm0.001 μm/0.002 μm in N₂Performing rapid thermal annealing in the atmosphere to complete the manufacture of the source electrode 9 and the drain contact 10;

the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.7X 10^-3Pa, power 400W, evaporation rate

The process conditions adopted by the rapid thermal annealing are as follows: the temperature was 850 ℃ and the time was 35 s.

And 6, manufacturing a floating island metal 11 and a drain island metal 12, as shown in FIG. 4 h.

Making a mask on the barrier layer 3, the gate island 4, the source electrode 9 and the drain contact 10 for the fourth time, depositing a plurality of layers of metals on the floating island 5 and the drain island 6 by using the mask through an electron beam evaporation technology, wherein the deposited metals adopt Ta/Ni/Au metal combination, namely Ta, Ni and Au are respectively arranged from bottom to top, and the thicknesses of the Ta, the Ni and the Au are 0.013 mu m/0.053 mu m/0.034 mu m, and finishing the making of the floating island metals 11 and the drain island metals 12;

the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.5X 10^-3Pa, power 450W, evaporation rate

Step 7, manufacturing a groove 13, as shown in fig. 4 i.

Making a mask on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the fifth time, and etching the barrier layer 3 between the drain island 6 and the drain contact 10 by using the mask, wherein the etching width c is 0.2 mu m, the depth e is 1nm, and a groove 13 is formed;

the etching adopts the following process conditions: CF (compact flash)₄The flow rate was 45sccm, O₂The flow rate is 5sccm, the pressure is 15mTorr, and the power is 300W.

Step 8, manufacturing the grid 14, as shown in fig. 4 j.

Making masks on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the sixth time, and depositing a multi-layer metal combination on the upper part of the gate island 4 by using the masks by adopting an electron beam evaporation technology to make a gate 14, wherein the deposited metal is a Gd/Au metal combination, namely the lower layer is Gd, the upper layer is Au, and the thickness of the Gd/Au combination is 0.045 mu m/0.20 mu m;

the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.6X 10^-3Pa, power of 250W, evaporation rate of

Step 9, manufacturing the schottky contact 15, as shown in fig. 4 k.

A seventh mask is manufactured on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12 and the grid electrode 14, the mask is utilized to deposit metal inside and on two sides of the groove 13 by adopting an electron beam evaporation technology, wherein the deposited metal is Ni, the thickness is 0.207 mu m, and the Schottky contact 15 is manufactured;

the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.6X 10^-3Pa, power 350W, evaporation rate

Step 10, passivation layer 16 is fabricated, as shown in fig. 4 l.

Depositing a passivation layer 16 with the thickness of 350nm on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12, the gate electrode 14 and the Schottky contact 15 and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology;

the process conditions for depositing the passivation layer 16 are as follows: n is a radical of₂O flow rate of 740sccm, SiH₄The flow rate is 200sccm, the temperature is 240 ℃, the RF power is 20W, and the pressure is 1900mT, thereby completing the manufacture of the whole device.

Example two: the height f of the floating island 5 and the drain island 6 made of the silicon carbide substrate is 200nm, and the doping concentration is 5 multiplied by 10¹⁷cm^-3The number of independent P-type semiconductor blocks in the floating island 5 is 5, and the number of semiconductor rectangular solid blocks in the drain island 6 is 3.

Step one, a transition layer 2 is made by extending AlN and GaN materials from bottom to top on a silicon carbide substrate 1, as shown in figure 4 a.

1.1) extending an undoped AlN material with the thickness of 100nm on a silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the aluminum source flow is 5 mu mol/min;

1.2) using a metal organic chemical vapor deposition technology to epitaxially grow a GaN material with the thickness of 4.9 mu m on the AlN material under the process conditions that the temperature is 1000 ℃, the pressure is 45Torr, the hydrogen flow is 4600sccm, the ammonia flow is 4600sccm and the gallium source flow is 120 mu mol/min, and thus the manufacture of the transition layer 2 is completed.

Step two, depositing undoped Al on the GaN transition layer 2_0.2Ga_0.8N produces the barrier layer 3 as shown in fig. 4 b.

Under the process conditions of 980 ℃, 45Torr of pressure, 4600sccm of hydrogen flow, 4600sccm of ammonia flow, 37 mu mol/min of gallium source flow and 7 mu mol/min of aluminum source flow, the metal organic chemical vapor deposition technology is used for depositing 50nm of undoped Al with 0.2 of aluminum component on the GaN transition layer 2_0.2Ga_0.8An N barrier layer 3.

Step three, a P-type layer is epitaxially grown on the barrier layer 3, as shown in fig. 4 c.

Using molecular beam epitaxy technique under vacuum degree of 1.0 × 10^-10mbar, radio frequency power of 350W, and N as reactant₂Under the process conditions of high-purity Ga source, the epitaxial thickness on the barrier layer 3 is 300nm, and the doping concentration is 5 multiplied by 10¹⁷cm^-3Forming a P-type layer.

And step four, manufacturing a gate island 4, five floating islands 5 and three drain islands 6 on the barrier layer 3, as shown in fig. 4d and 4 e.

4.1) first making a mask on the P-type layer, and using a reactive ion etching technology to etch Cl₂Etching two sides of the P-type layer under the process conditions of 15sccm of flow, 10mTorr of pressure and 50W of power, wherein the etching depth i is 100 nm;

4.2) Using the maskAnd 4.1) masking in step (a) while using reactive ion etching technique in Cl₂Etching the P-type layer under the process conditions of 15sccm flow, 10mTorr pressure and 50W power, and simultaneously forming a gate island 4 with the height of 300nm, five same floating islands 5 with the heights of 200nm and the widths of 5 micrometers, and three same drain islands 6 with the heights of 200nm and the widths of 20 micrometers; wherein:

five independent P-type semiconductor blocks in the floating island 5 are correspondingly arranged left and right by taking the third as the center, and the space M between the first independent P-type semiconductor block and the grid island 4 is arranged on the left side of the third independent P-type semiconductor block ₁1 μ M, the pitch M of the second independent P-type semiconductor block and the first independent P-type semiconductor block₂A pitch M of the third independent P-type semiconductor block to the second independent P-type semiconductor block of 3 μ M₃Is 5 μm; the distance N between the 1 st independent P-type semiconductor block and the drain island 6 is arranged at the right side of the third P-type semiconductor block₁A pitch N of the 2 nd independent P-type semiconductor block and the 1 st independent P-type semiconductor block of 2 μm₂A pitch N of 3 μm between the 3 rd and 2 nd independent P-type semiconductor blocks₃Is 4 μm;

three P-type semiconductor rectangular solid blocks in the drain island 6 are placed symmetrically in front and rear with the second as a center of symmetry, each P-type semiconductor rectangular solid block has a width a of 20 μm, a length b of 30 μm, and a pitch j of 25 μm.

Step five, manufacturing a source electrode 9 and a drain contact 10, as shown in fig. 4f and 4 g.

5.1) making a mask on the P-type layer for the third time, and performing reactive ion etching on the Cl layer by using a reactive ion etching technology₂Etching the two sides of the P-type layer until the upper surface of the transition layer 2 under the process conditions of 15sccm of flow, 10mTorr of pressure and 90W of power, and respectively forming a source groove 7 and a drain groove 8 with the depth of 20 nm;

5.2) continuing to use the mask of 5.1), again using the electron beam evaporation technique at a vacuum of 1.5X 10^-3Pa, power 300W, evaporation rate

Process conditions ofThen, a plurality of layers of metal are deposited and processed under the process conditions of 850 ℃ and 35s for N₂And carrying out rapid thermal annealing in the atmosphere to manufacture the source electrode 9 and the drain contact 10, wherein the deposited metal is a Ti/Al/Mo/Au metal combination, namely Ti, Al, Mo and Au are respectively arranged from bottom to top, and the height of the deposited metal is 0.095 mu m/0.131 mu m/0.108 mu m/0.066 mu m.

And step six, manufacturing floating island metal 11 and drain island metal 12, as shown in fig. 4 h.

Making mask on the barrier layer 3, gate island 4, source 9 and drain contact 10 for the fourth time, and adopting electron beam evaporation technique at vacuum degree of 1.7 × 10^-3Pa, power 650W, evaporation rate

Under the process conditions of (1), depositing a plurality of layers of metals to manufacture a floating island metal 11 and a drain island metal 12, wherein the deposited metals are Ti/Mo/Au metal combinations, namely Ti, Mo and Au are respectively from bottom to top, and the thickness of the metals is 0.152 mu m/0.216 mu m/0.132 mu m.

Step seven, manufacturing the groove 13 as shown in fig. 4 i.

Making a mask on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the fifth time, and using the mask to etch the barrier layer 3 between the drain island 6 and the drain contact 10 by using reactive ions to form CF₄The flow rate was 45sccm, O₂The groove 13 is etched under the process conditions of 5sccm flow, 15mT pressure and 450W power, the width c of the groove 13 is 5 μm, and the depth e is 50 nm.

Step eight, the gate 14 is fabricated as shown in fig. 4 j.

Making a mask on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the sixth time, and using the mask to make an electron beam evaporation technology on the gate island 4 at a vacuum degree of 1.4 multiplied by 10^-3Pa, power 650W, evaporation rate

Under the process conditions of (1), depositing a plurality of layers of metal to form the gate 14, wherein the deposited metal is ZThe r/Pt metal combination, i.e., Zr for the lower layer and Pt for the upper layer, had a thickness of 0.18 μm/0.32. mu.m.

Step nine, manufacturing the schottky contact 15, as shown in fig. 4 k.

A mask is made on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12 and the grid electrode 14 for the seventh time, and the mask is used for using electron beam evaporation technology to make the vacuum degree inside and at two sides of the groove 13 be 1.4 multiplied by 10^-3Pa, power of 250W, evaporation rate of

The schottky contact 15 is made by depositing a metal of W with a thickness of 1 μm under the process conditions of (a).

Step ten, the passivation layer 16 is fabricated as shown in fig. 4 l.

The barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12, the grid electrode 14 and the Schottky contact 15 are arranged on the upper part and the peripheral area of the N by adopting the plasma enhanced chemical vapor deposition technology₂O flow rate of 750sccm, SiH₄And depositing the SiN passivation layer 16 with the thickness of 1000nm under the process conditions of the flow rate of 250sccm, the temperature of 250 ℃, the RF power of 50W and the pressure of 2000mT, thereby completing the manufacture of the whole device.

Example three: the height f of the floating island 5 and the drain island 6 made of the silicon substrate is 400nm, and the doping concentration is 5 multiplied by 10²⁰cm^-3The number of independent P-type semiconductor blocks in the floating island 5 is 7, and the number of semiconductor rectangular parallelepiped blocks in the drain island 6 is 7.

Step A. epitaxial growth of AlN and GaN materials on a silicon substrate 1 from bottom to top to form a transition layer 2, as shown in FIG. 4 a.

Firstly, a metal organic chemical vapor deposition technology is used for extending AlN material with the thickness of 400nm on a silicon substrate 1, and the process conditions are as follows: the temperature is 800 ℃, the pressure is 40Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the aluminum source flow is 25 mu mol/min;

then, a GaN material with the thickness of 8.6 μm is epitaxially grown on the AlN material by using a metal organic chemical vapor deposition technology, and the manufacture of the transition layer 2 is completed, wherein the process conditions are as follows: the temperature is 980 ℃, the pressure is 45Torr, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 120 mu mol/min.

Step B, depositing undoped Al on the GaN transition layer 2_0.1Ga_0.9N produces the barrier layer 3 as shown in fig. 4 b.

Depositing undoped Al with a thickness of 100nm and an aluminum composition of 0.1 on the GaN transition layer 2 by using a metal organic chemical vapor deposition technique_0.1Ga_0.9An N barrier layer 3; the deposition process conditions are as follows:

the temperature was 980 ℃, the pressure was 45Torr, the hydrogen flow was 4500sccm, the ammonia flow was 4500sccm, the gallium source flow was 36. mu. mol/min, and the aluminum source flow was 7. mu. mol/min.

Step c. epitaxial P-type layer on barrier layer 3, fig. 4 c.

Using molecular beam epitaxy technique, the barrier layer 3 is epitaxially grown to a thickness of 500nm and a doping concentration of 5 × 10²⁰cm^-3The P-type GaN semiconductor material forms a P-type layer, and the process conditions are as follows:

vacuum degree of 1.0X 10 or less^-10mbar, radio frequency power of 450W, and N as reactant₂And a high purity Ga source.

Step d, a gate island 4, seven floating islands 5 and seven drain islands 6 are fabricated on the barrier layer 3, as shown in fig. 4d and 4 e.

First, in Al_0.2Ga_0.8A mask is manufactured on the N barrier layer 3 for the first time, etching is carried out on two sides of the N barrier layer 3, and the etching depth i is 100 nm;

then, in Al_0.2Ga_0.8Making a mask on the N barrier layer 3 for the second time, etching the P type layer by using a reactive ion etching technology, and simultaneously forming a gate island 4 with the height of 500nm, seven floating islands 5 with the height of 400nm and seven drain islands 6 with the height of 400nm, wherein:

seven independent P-type semiconductor blocks in the floating island 5 are arranged in a left-right corresponding mode by taking the fourth as the center, and the first independent P-type semiconductor block and the gate island are arranged on the left side of the fourth independent P-type semiconductor block4 of pitch M₁0.1 μ M, the pitch M of the second isolated P-type semiconductor block and the first isolated P-type semiconductor block₂5 μ M, the distance M between the third independent P-type semiconductor block and the second independent P-type semiconductor block₃A pitch M of the fourth independent P-type semiconductor block and the third independent P-type semiconductor block of 7 μ M₄Is 10 μm; the distance N between the 1 st independent P-type semiconductor block and the drain island 6 is arranged at the right side of the fourth independent P-type semiconductor block₁A pitch N of the 2 nd and 1 st independent P type semiconductor blocks of 0.1 μm₂A pitch N of the 3 rd and 2 nd independent P type semiconductor blocks of 4 μm₃A pitch N of the fourth independent P-type semiconductor block to the 3 rd independent P-type semiconductor block of 8 μm₄Is 10 μm;

seven P-type semiconductor rectangular blocks in the drain island 6 are symmetrically placed in front and back with the fourth as a symmetry center, the width a of each P-type semiconductor rectangular block is 50 micrometers, the length b of each P-type semiconductor rectangular block is 40 micrometers, and the distance j between the P-type semiconductor rectangular blocks is 40 micrometers;

the process conditions of the reactive ion etching technology are as follows: cl₂The flow rate is 15sccm, the pressure is 10mTorr, and the power is 70W.

Step e. source 9 and drain contact 10 are made as in fig. 4f and 4 g.

Firstly, a mask is made on the barrier layer 3 for the third time, etching is carried out on two sides of the barrier layer 3 by using a reactive ion etching technology until the etching reaches the upper surface of the transition layer 2, and a source groove 7 and a drain groove 8 with the depth of 100nm are formed;

then, continuing to use the previous mask, depositing multiple layers of metal again by electron beam evaporation technology, and depositing N₂Carrying out rapid thermal annealing in the atmosphere to manufacture a source electrode 9 and a drain contact 10, wherein the deposited metal is a Ti/Al/Ti/Au metal combination, namely Ti, Al, Ti and Au are respectively arranged from bottom to top, and the thicknesses of the metals are 0.104 mu m/0.236 mu m/0.141 mu m/0.119 mu m in sequence;

the etching adopts the following process conditions: cl₂The flow is 15sccm, the pressure is 10mTorr, and the power is 70W; the technological conditions of the electron beam evaporation technology are as follows: vacuum degree of 1.5X 10^-3Pa, power 950W, evaporation rate

And F, manufacturing a floating island metal 11 and a drain island metal 12, as shown in FIG. 4 h.

Making a mask on the barrier layer 3, the gate island 4, the source electrode 9 and the drain contact 10 for the fourth time, and depositing a plurality of layers of metals on the upper parts of the floating island 5 and the drain island 6 by using an electron beam evaporation technology, wherein the deposited metals are Cu/Ni/Au metal combinations, namely Cu, Ni and Au from bottom to top respectively, and the thicknesses of the metals are 0.216 mu m/0.521 mu m/0.263 mu m;

the electron beam evaporation technology adopts the following process conditions: vacuum degree of 1.9X 10^-3Pa, power 750W, evaporation rate

Step g, the groove 13 is made, as shown in fig. 4 i.

Making a mask on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the fifth time, and etching the barrier layer 3 between the drain island 6 and the drain contact 10 by using a reactive ion etching technology by using the mask to make a groove 13, wherein the width c of the groove is 10 microns, and the depth e of the groove is 150 nm;

the etching adopts the following process conditions: CF (compact flash)₄The flow rate was 45sccm, O₂The flow rate is 5sccm, the pressure is 15mTorr, and the power is 250W.

Step h. make gate 14, as in fig. 4 j.

Making masks on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11 and the drain island metal 12 for the sixth time, depositing a plurality of layers of metals on the gate island 4 by using an electron beam evaporation technology by using the masks to make the gate 14, wherein the deposited metals are Ta/Ni metal combinations, namely the lower layer is Ta, the upper layer is Ni, and the thickness of the deposited metals is 0.25 mu m/0.38 mu m;

the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.8X 10^-3Pa, power 850W, evaporation rateA rate of

Step i. make schottky contact 15 as in fig. 4 k.

A seventh mask is manufactured on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12 and the grid electrode 14, metal is deposited inside and on two sides of the groove 13 by using an electron beam evaporation technology through the mask to manufacture the Schottky contact 15, wherein the thickness of the deposited metal Mo is 1.6 mu m;

the process conditions adopted for depositing the metal are as follows: vacuum degree of 1.8X 10^-3Pa, power 800W, evaporation rate

Step j. passivation layer 16 is fabricated as in fig. 4 l.

Depositing SiO with the thickness of 1500nm on the barrier layer 3, the gate island 4, the floating island 5, the drain island 6, the source electrode 9, the drain contact 10, the floating island metal 11, the drain island metal 12, the gate electrode 14 and the Schottky contact 15 and the peripheral area thereof by adopting a plasma enhanced chemical vapor deposition technology₂ A passivation layer 16;

the process conditions for depositing the passivation layer 16 are as follows: n is a radical of₂O flow rate is 760sccm, SiH₄The flow rate is 300sccm, the temperature is 260 ℃, the RF power is 90W, and the pressure is 2400mT, so that the whole device is manufactured.

The effects of the present invention can be further illustrated by the following simulations.

First, simulation parameter

The traditional GaN-based HEMT power switch device and the device of the invention adopt the same main structure parameters, the device of the invention adopts 6 floating islands, and the width of each floating island is 1.1 μm.

Second, simulation content

Simulation 1: the current collapse characteristic simulation was performed on the conventional transistor and the transistor of the present invention, respectively, and the results are shown in fig. 5.

As can be seen from fig. 5, the conventional transistor has a significant current collapse phenomenon, and the transistor of the present invention can effectively suppress the current collapse effect, which shows that the effect of suppressing the current collapse of the transistor of the present invention is significantly better than that of the conventional transistor.

Simulation 2: the breakdown characteristics of the conventional transistor and the transistor of the present invention were simulated, respectively, and the results are shown in fig. 6.

As can be seen from fig. 6, the conventional transistor can only realize forward blocking, and the transistor breaks down, i.e., the drain-source voltage when the drain current rapidly increases is 260V, while the transistor of the present invention can realize forward blocking and reverse blocking, and the breakdown voltage of the transistor during forward blocking is 983V, and the breakdown voltage of the transistor during reverse blocking is 996V, which indicates that the transistor of the present invention can realize bidirectional blocking characteristics, and the breakdown voltage is much greater than that of the conventional transistor.

The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.

Claims

1. A gallium nitride-based high electron mobility transistor, comprising from bottom to top: a substrate (1), a transition layer (2), a barrier layer (3), and a left edge of the barrier layer (3) is provided. An active trench (7), on which a source electrode (9) is deposited, a drain trench (8) is provided on the right edge of the barrier layer (3), a drain contact (10) is deposited on its upper portion, and the barrier layer The upper part of (3) is provided with a gate island (4), and a gate electrode (14) is deposited on the upper part, which is characterized in that:

A floating island (5) and a drain island (6) are arranged on the barrier layer (3) on the right side of the gate island (4) in sequence, and a floating island metal (11) is deposited on the upper part of the floating island (5). A drain island metal (12) is deposited on the upper part of (6), a groove (13) is arranged between the floating island (6) and the drain contact (10), and a Schottky contact (15) is deposited inside and on the upper part of the floating island (6) ;

The floating island (5) includes 2n-1 independent P-type semiconductor blocks of the same size, and is placed in a left-right correspondence with the nth independent P-type semiconductor block as the center, and n≥1;

The height of the drain island (6) is the same as the height f of each independent P-type semiconductor block in the floating island (5), which includes m P-type semiconductor cuboid blocks, and m≥1;

The barrier layer (3), the gate island (4), the floating island (5), the drain island (6), the source electrode (9), the drain contact (10), the floating island metal (11), the drain island metal ( 12), the gate (14) and the upper part of the Schottky contact (15) are all wrapped with a passivation layer (16).

2. The transistor according to claim 1, wherein:

The height h of the barrier layer (3) is 5-100 nm;

The height g of the gate island (4) is 5˜500 nm, and the doping concentration is 4×10 ¹⁵ ˜5×10 ²⁰ cm ⁻³ .

3 . The transistor according to claim 1 , wherein the substrate ( 1 ) is made of sapphire or silicon carbide or silicon or graphene material. 4 .

4 . The transistor according to claim 1 , wherein the width t and the height f of each independent P-type semiconductor block in the floating island ( 5 ) are the same, and the value of t is 0.2-10 μm, and the value of f is 1˜400 nm, and f is smaller than the height g of the gate island (4); the doping concentration of each P-type semiconductor block is 4×10 ¹⁵ to 5×10 ²⁰ cm ⁻³ .

5 . The transistor according to claim 1 , wherein the drain island ( 6 ) is composed of m equal-spaced P-type semiconductor cuboid blocks, the spacing j of which is 0.1 μm˜40 μm, m≧1, and each The width a of each cuboid block is 0.2 μm˜50 μm, the length b is 0.1 μm˜40 μm, the height f is 1˜400 nm, and the doping concentration of each P-type semiconductor block is 4×10 ¹⁵ ˜5×10 ²⁰ cm ⁻³ .

6 . The transistor according to claim 1 , wherein the groove ( 13 ) has a width c of 0.2 μm to 10 μm, and a depth e of 1 to 150 nm. 7 .

7. The transistor according to claim 1, wherein the floating island (5) is centered on the nth independent P-type semiconductor block, and the first independent P-type semiconductor block on the left side of the floating island (5) is centered on the gate island ( 4) The spacing is M ₁ , the spacing between the second independent P-type semiconductor block and the first independent P-type semiconductor block is M ₂ , and so on, the nth independent P-type semiconductor block on the left is connected to the n-1th independent P-type semiconductor block. The spacing of the individual P-type semiconductor blocks is _Mn , and 0.1μm≤M ₁ <M ₂ <...< _Mn ≤10μm; on the right side of the nth independent P-type semiconductor block, the first independent P-type The distance between the semiconductor block and the drain island (6) is N ₁ , the distance between the second independent P-type semiconductor block and the first independent P-type semiconductor block is N ₂ , and so on, the nth independent P-type semiconductor on the right The spacing between the block and the n-1 th independent P-type semiconductor block is N _n , and 0.1 μm≦N ₁ <N ₂ <...<N _n ≦10 μm, and n≥1.

8 . The transistor according to claim 1 , wherein the floating island metal ( 11 ) and the drain island metal ( 12 ) are the same, and both adopt a multi-layer metal combination, and the work function of the lowermost metal is less than or equal to 5.15. 9 . eV.

9. A method for making a GaN-based high electron mobility transistor, characterized in that, comprising the steps of:

A) Epitaxial GaN-based wide-bandgap semiconductor material is used on the substrate (1) using metal organic chemical vapor deposition technology to form a transition layer (2) with a thickness of 1-9 μm;

B) epitaxial GaN-based wide bandgap semiconductor material using metal organic chemical vapor deposition technology on the transition layer (2) to form a barrier layer (3) with a thickness of 5-100 nm;

C) Epitaxy of P-type GaN semiconductor material on the barrier layer (3) using metal organic chemical vapor deposition technology to form a P-type GaN semiconductor material with a thickness of 5 to 500 nm and a doping concentration of 4 × 10 ¹⁵ to 5 × 10 ²⁰ cm ^-3 type layer;

D) Make grid island (4), floating island (5) and drain island (6):

D1) making a mask on the P-type layer for the first time, and using the mask to etch the P-type layers on both sides, and the etching depth is i, i=g-f;

D2) Continue to use the mask in D1), and make a mask on the P-type layer for the second time, use the mask and the mask in step D1) to etch at the same time, and etch to the barrier layer (3) Up to the upper surface, a gate island (4), a floating island (5) and a drain island (6) are formed;

E) Making source (9) and drain contacts (10):

E1) A third mask is made on the barrier layer (3), the gate island (4), the floating island (5) and the drain island (6), and the left side of the barrier layer (3) and the The right side is etched to form a source groove (7) and a drain groove (8) respectively;

E2) Continue to use the mask to deposit Ti/Al/Ni/Au or Ti/Al/Mo/Au or Ti/Al/Ti/Au multilayers on the left and right barrier layers (3) by electron beam evaporation technology metal, and perform rapid thermal annealing in _N2 atmosphere to complete the fabrication of source electrode (9) and drain contact (10);

F) A fourth mask is made on the barrier layer (3), the gate island (4), the source electrode (9) and the drain contact (10), and the floating island (5) and the drain island (6) are formed using the mask for the fourth time. ) using electron beam evaporation technology to deposit Ta/Ni/Au or Ti/Mo/Au or Cu/Ni/Au multi-layer metal, and the work function of the lowermost metal is less than or equal to 5.15eV to complete the floating island metal (11) and the fabrication of island metal (12);

G) In barrier layer (3), gate island (4), floating island (5), drain island (6), source (9), drain contact (10), floating island metal (11) and drain island metal (12) A mask is made for the fifth time, and the mask is used to etch the barrier layer (3) between the drain island (6) and the drain contact (10) to a depth of e to form a groove (13) );

H) In the barrier layer (3), gate island (4), floating island (5), drain island (6), source (9), drain contact (10), floating island metal (11) and drain island metal (12) Making a mask for the sixth time, using the mask to deposit Gd/Au or Zr/Pt or Ta/Ni multi-layer metal on the upper part of the gate island (4) by electron beam evaporation technology, to complete the gate (14) );

I) In the barrier layer (3), gate island (4), floating island (5), drain island (6), source electrode (9), drain contact (10), floating island metal (11), drain island metal (12) A mask is made for the seventh time on the gate (14), using the mask to deposit Ni or W or Mo single-layer metal inside and on both sides of the groove (13) by using electron beam evaporation technology, to complete the The making of Teki contact (15);

J) At barrier layer (3), at gate island (4), floating island (5), drain island (6), source electrode (9), drain contact (10), floating island metal (11), drain island The metal (12), the gate (14) and the upper part of the Schottky contact (15) and its peripheral region, a passivation layer (16) with a thickness greater than or equal to 350 nm is deposited by plasma-enhanced chemical vapor deposition technology to complete the whole process. device fabrication.

10. The method according to claim 9, wherein:

The process conditions of the electron beam evaporation technology are as follows: the degree of vacuum is less than 2×10 ^-3 Pa, the power is 200-1000W, and the evaporation rate is less than

For the plasma enhanced chemical vapor deposition technology, the process conditions are that the N ₂ O flow is 740 sccm, the SiH ₄ flow is 200 sccm, the temperature is 240° C., the RF power is 20-90 W, and the pressure is 1900 mT.