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CN113990918B - Vertical III-nitride power semiconductor device with stepped shielding ring and preparation method thereof - Google Patents

Vertical III-nitride power semiconductor device with stepped shielding ring and preparation method thereof Download PDF

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CN113990918B
CN113990918B CN202111184629.2A CN202111184629A CN113990918B CN 113990918 B CN113990918 B CN 113990918B CN 202111184629 A CN202111184629 A CN 202111184629A CN 113990918 B CN113990918 B CN 113990918B
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CN113990918A (en
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刘超
王珩
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Shandong University
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107Buried supplementary regions, e.g. buried guard rings 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126Top-view geometrical layouts of the regions or the junctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/01Manufacture or treatment
    • H10D8/051Manufacture or treatment of Schottky diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 

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Abstract

The invention relates to a vertical III-nitride power semiconductor device with a stepped shielding ring and a preparation method thereof, wherein the vertical III-nitride power semiconductor device sequentially comprises a cathode electrode, a heavily doped N-nitride substrate region, a lightly doped N-nitride drift region, a heavily doped P-nitride region and an anode electrode from bottom to top, wherein a lightly doped P-nitride shielding ring is embedded below the heavily doped P-nitride region in the lightly doped N-nitride drift region; through a large number of simulation calculation analyses, the lightly doped P-type nitride shielding ring is embedded in the lightly doped N-type nitride drift region, so that the reverse voltage withstand capability of the device can be greatly improved on the premise of keeping the size of the device unchanged, and meanwhile, the reverse leakage is further reduced, so that the device can be applied to a higher voltage scene.

Description

一种具有阶梯屏蔽环的垂直型Ⅲ族氮化物功率半导体器件及 其制备方法A vertical type III nitride power semiconductor device with a stepped shielding ring and Its preparation method

技术领域Technical field

本发明涉及一种具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构及其制备方法与应用,属于半导体器件技术领域。The invention relates to a Group III nitride vertical power device structure with a shielding ring structure and its preparation method and application, and belongs to the technical field of semiconductor devices.

背景技术Background technique

相较于以硅为代表的第一代半导体和以砷化镓为代表的第二代半导体,以碳化硅和III族氮化物为代表的第三代半导体,因其禁带宽度大、高临界击穿场强、高热导率、电子饱和漂移速率高等优良特性,在高频通信、电力电子等领域具有广阔的应用前景。Compared with the first-generation semiconductors represented by silicon and the second-generation semiconductors represented by gallium arsenide, the third-generation semiconductors represented by silicon carbide and group III nitrides have large bandgaps and high criticality. With excellent characteristics such as breakdown field strength, high thermal conductivity, and high electron saturation drift rate, it has broad application prospects in high-frequency communications, power electronics and other fields.

目前,可以广泛应用的氮化镓基器件主要是横向型高电子迁移率晶体管(HighElectron Mobility Transistors,HEMT)。但横向型器件的主要缺点是器件的反向击穿电压与器件横向的电极间距成比例,导致高压工作场景应用中需要更大的器件尺寸,这大大提高了器件的工艺制备成本。为了解决这一问题,完全垂直型器件能够以增加器件的垂直漂移层厚度实现更大的反向击穿电压,同时有效避免横向结构和准垂直结构中出现的电流拥挤效应,减小正向导通电阻。At present, gallium nitride-based devices that can be widely used are mainly lateral high electron mobility transistors (HEMT). However, the main disadvantage of lateral devices is that the reverse breakdown voltage of the device is proportional to the lateral electrode spacing of the device, resulting in the need for larger device sizes in high-voltage working scenarios, which greatly increases the process preparation cost of the device. In order to solve this problem, fully vertical devices can achieve a larger reverse breakdown voltage by increasing the thickness of the vertical drift layer of the device, while effectively avoiding the current crowding effect that occurs in lateral structures and quasi-vertical structures, and reducing forward conduction. resistance.

在器件的反向阻断过程中,优良的反向击穿特性可以通过调节器件内部的电场分布均匀实现,但同时在器件结构参数优化过程中,会产生局部电场聚集导致的器件提前击穿现象。During the reverse blocking process of the device, excellent reverse breakdown characteristics can be achieved by adjusting the electric field distribution inside the device to be uniform. However, during the optimization of the device structure parameters, premature breakdown of the device will occur due to local electric field accumulation. .

肖特基势垒二极管因其具有压降低、开关速度快等优点而成为现代电力电子系统的重要组成部分。为了满足消费电子、高频通讯器件的应用,对传统肖特基二极管在高压、大功率应用场景中提出了更高要求,器件的性能限制也越来越突出。Schottky barrier diodes have become an important part of modern power electronic systems due to their advantages such as voltage drop and fast switching speed. In order to meet the application of consumer electronics and high-frequency communication devices, higher requirements have been put forward for traditional Schottky diodes in high-voltage and high-power application scenarios, and the performance limitations of the devices have become increasingly prominent.

在高反向偏压场景中,平面型肖特基势垒二极管(Planar Schottky BarrierDiode,SBD)往往因为肖特基接触势垒下方的强电场聚集而产生明显的势垒降低效应,从而产生较大的反向漏电流,限制了肖特基势垒二极管的反向击穿特性。这个问题可以通过采用混合PiN结势垒肖特基二极管(Merged PiN Schottky diode,MPS diode)新结构得以解决。相对比于传统平面肖特基势垒二极管,氮化镓垂直型混合PiN结势垒肖特基二极管能有效的调制肖特基接触势垒下方的电场分布,利用相邻PN结的耗尽区叠加,可以对肖特基接触势垒形成良好的电场屏蔽效应,避免因势垒降低效应引起的大泄露电流和提前击穿问题。但当p-GaN的掺杂浓度过高时,强电场聚集发生在p-GaN结构底部的拐角处,从而再次造成器件的提前击穿,限制了器件的反向阻断性能。In a high reverse bias scenario, Planar Schottky Barrier Diode (SBD) often produces an obvious barrier lowering effect due to the strong electric field accumulation under the Schottky contact barrier, resulting in a large The reverse leakage current limits the reverse breakdown characteristics of the Schottky barrier diode. This problem can be solved by using a new structure of a mixed PiN junction barrier Schottky diode (Merged PiN Schottky diode, MPS diode). Compared with traditional planar Schottky barrier diodes, gallium nitride vertical hybrid PiN junction barrier Schottky diodes can effectively modulate the electric field distribution under the Schottky contact barrier and utilize the depletion region of adjacent PN junctions. Superposition can form a good electric field shielding effect on the Schottky contact barrier and avoid large leakage current and early breakdown problems caused by the barrier reduction effect. However, when the doping concentration of p-GaN is too high, strong electric field accumulation occurs at the corners at the bottom of the p-GaN structure, causing premature breakdown of the device again and limiting the reverse blocking performance of the device.

发明内容Contents of the invention

针对现有技术的不足,本发明提供了一种具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构;本发明提出一种有效解决p-GaN高掺杂情况下氮化镓垂直型混合PiN结势垒肖特基二极管局部电场聚集问题的技术方案,具体如下:In view of the shortcomings of the existing technology, the present invention provides a Group III nitride vertical power device structure with a shielding ring structure; the present invention proposes an effective solution to the problem of vertical gallium nitride mixed PiN under the condition of high p-GaN doping. The technical solution to the local electric field accumulation problem of junction barrier Schottky diodes is as follows:

1、通过二次外延或多次外延加离子注入的生长方法实现重掺杂p-GaN下方的浅掺杂阶梯状屏蔽环结构,屏蔽环的耗尽作用可以有效的缓解重掺杂p-GaN结构底部的拐角处的强电场聚集,对其形成了电场屏蔽保护作用;1. Through the growth method of secondary epitaxy or multiple epitaxy plus ion implantation, a shallowly doped stepped shielding ring structure under the heavily doped p-GaN is realized. The depletion effect of the shielding ring can effectively alleviate the heavily doped p-GaN. The strong electric field gathers at the corners at the bottom of the structure, forming an electric field shielding protection for it;

2、通过优化p-GaN浅掺杂阶梯状屏蔽环的参数(镁离子掺杂浓度、上阶梯厚度、下阶梯厚度),得到大幅度提升的反向阻断特性。该器件结构的物理机理为浅掺杂p-GaN与n型漂移层形成PN结的空间电荷耗尽区,该空间电荷耗尽区的宽度会随着反偏压的变化而发生改变,从而实现将聚集的局部电场疏散,使得电场分布更加均匀,以达到提高器件反向击穿电压的目的。2. By optimizing the parameters of the p-GaN shallowly doped stepped shielding ring (magnesium ion doping concentration, upper step thickness, lower step thickness), the reverse blocking characteristics are greatly improved. The physical mechanism of the device structure is that lightly doped p-GaN and the n-type drift layer form a space charge depletion region of the PN junction. The width of the space charge depletion region will change with the change of the reverse bias voltage, thereby achieving Evacuate the accumulated local electric field to make the electric field distribution more uniform, so as to improve the reverse breakdown voltage of the device.

术语解释:Terminology explanation:

1、干法刻蚀,是用等离子体进行薄膜刻蚀的技术。1. Dry etching is a technology that uses plasma to etch thin films.

2、MOCVD法,是在MOCVD炉内气相外延生长(VPE)的基础上发展起来的一种新型气相外延生长技术。2. MOCVD method is a new vapor phase epitaxial growth technology developed on the basis of vapor phase epitaxial growth (VPE) in MOCVD furnace.

本发明的技术方案为:The technical solution of the present invention is:

一种具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构,由下自上依次包括阴极电极、重掺杂N型氮化物衬底区、轻掺杂N型氮化物漂移区、重掺杂P型氮化物区、阳极电极,在所述轻掺杂N型氮化物漂移区中重掺杂P型氮化物区下方嵌入有轻掺杂P型氮化物屏蔽环;A Group III nitride vertical power device structure with a shielding ring structure, including from bottom to top a cathode electrode, a heavily doped N-type nitride substrate region, a lightly doped N-type nitride drift region, a heavily doped P-type nitride region, anode electrode, and a lightly doped P-type nitride shielding ring embedded below the heavily doped P-type nitride region in the lightly doped N-type nitride drift region;

根据本发明优选的,所述轻掺杂P型氮化物屏蔽环呈阶梯状,上阶梯的厚度T1为0.5-2.0μm,下阶梯的厚度T2为1.0-10.0μm,下阶梯的宽度W为1.0-4.0μm;According to the preferred embodiment of the present invention, the lightly doped P-type nitride shielding ring is in the shape of a step. The thickness T 1 of the upper step is 0.5-2.0 μm, the thickness T 2 of the lower step is 1.0-10.0 μm, and the width W of the lower step is is 1.0-4.0μm;

最优选的,上阶梯的厚度T1为2.0μm,下阶梯的厚度T2为8.0μm,下阶梯的宽度W为2μm。Most preferably, the thickness T 1 of the upper step is 2.0 μm, the thickness T 2 of the lower step is 8.0 μm, and the width W of the lower step is 2 μm.

根据本发明优选的,所述轻掺杂P型氮化物屏蔽环中镁离子掺杂浓度为1e15cm-3-5e17cm-3According to the preferred embodiment of the present invention, the magnesium ion doping concentration in the lightly doped P-type nitride shielding ring is 1e15cm -3 -5e17cm -3 .

进一步优选的,所述轻掺杂P型氮化物屏蔽环中镁离子掺杂浓度为1e16cm-3-8e16cm-3Further preferably, the magnesium ion doping concentration in the lightly doped P-type nitride shielding ring is 1e16cm -3 -8e16cm -3 .

最优选的,所述轻掺杂P型氮化物屏蔽环中镁离子掺杂浓度为3e16cm-3Most preferably, the magnesium ion doping concentration in the lightly doped P-type nitride shielding ring is 3e16cm -3 .

根据本发明优选的,所述重掺杂N型氮化物衬底区为重掺杂N型氮化镓衬底区,所述轻掺杂N型氮化物漂移区为轻掺杂N型氮化镓漂移区,所述重掺杂P型氮化物区为重掺杂P型氮化镓区。According to the preferred embodiment of the present invention, the heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, and the lightly doped N-type nitride drift region is a lightly doped N-type nitride Gallium drift region, the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.

上述具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构的制备方法,包括步骤如下:The preparation method of the above-mentioned Group III nitride vertical power device structure with a shielding ring structure includes the following steps:

(1)在阴极电极上依次生长重掺杂N型氮化物衬底区、轻掺杂N型氮化物漂移区;(1) Sequentially grow a heavily doped N-type nitride substrate region and a lightly doped N-type nitride drift region on the cathode electrode;

(2)对轻掺杂N型氮化物漂移区进行ICP刻蚀后,进行二次外延生长形成阶梯状的轻掺杂P型氮化物屏蔽环;(2) After ICP etching the lightly doped N-type nitride drift region, perform secondary epitaxial growth to form a stepped lightly doped P-type nitride shielding ring;

(3)继续依次外延生长重掺杂P型氮化物区、阳极电极,既得。(3) Continue to epitaxially grow the heavily doped P-type nitride region and the anode electrode in sequence, and the result is obtained.

根据本发明优选的,步骤(2)中,进行二次外延生长形成阶梯状的轻掺杂P型氮化物屏蔽环,具体实现步骤包括:According to the preferred embodiment of the present invention, in step (2), secondary epitaxial growth is performed to form a stepped lightly doped P-type nitride shielding ring. The specific implementation steps include:

①利用干法刻蚀工艺,在轻掺杂N型氮化物漂移区上刻蚀沟槽区域,对刻蚀表面进行损伤处理;①Use a dry etching process to etch the trench area on the lightly doped N-type nitride drift area, and damage the etched surface;

②利用二氧化硅作为硬质掩膜,遮挡未刻蚀的轻掺杂N型氮化物漂移区,分别利用氨气作为N源,二茂镁作为掺杂源,H2作为载气,采用MOCVD法在轻掺杂N型氮化物漂移区上表面同质外延一层P型氮化物;②Use silicon dioxide as a hard mask to block the unetched lightly doped N-type nitride drift region, use ammonia as the N source, magnesium dicene as the doping source, H 2 as the carrier gas, and use MOCVD The method is to homoepitaxially grow a layer of P-type nitride on the surface of the lightly doped N-type nitride drift region;

③MOCVD炉内原位退火,激活P型掺杂的镁离子,生长形成阶梯状的轻掺杂P型氮化物屏蔽环。③ In-situ annealing in the MOCVD furnace activates P-type doped magnesium ions and grows to form a stepped lightly doped P-type nitride shielding ring.

根据本发明优选的,步骤(2)中,进行ICP刻蚀后,进行多次外延加离子注入的工艺生长形成阶梯状的轻掺杂P型氮化物屏蔽环,具体实现步骤包括:According to the preferred embodiment of the present invention, in step (2), after ICP etching, multiple epitaxy and ion implantation processes are performed to grow a stepped lightly doped P-type nitride shielding ring. The specific implementation steps include:

A、利用干法刻蚀工艺,在轻掺杂N型氮化物漂移区上刻蚀沟槽区域,对刻蚀表面进行损伤处理;A. Use a dry etching process to etch the trench area on the lightly doped N-type nitride drift area, and damage the etched surface;

B、利用离子注入机在轻掺杂N型氮化物漂移区的沟槽区域底面进行Mg离子注入,离子注入的功率能量设置为150~300keV,注入深度为0.3~0.6μm;B. Use an ion implanter to implant Mg ions on the bottom surface of the trench area of the lightly doped N-type nitride drift region. The power energy of the ion implantation is set to 150~300keV, and the implantation depth is 0.3~0.6μm;

C、在氮气、氨气、氩气、氢气中的一种或两种以上任意配比的混合物的气体氛围中,进行快速热退火处理,快速热退火处理的温度范围为400~1500℃,退火时间为10~90min;C. Perform rapid thermal annealing treatment in a gas atmosphere of one or more mixtures of nitrogen, ammonia, argon, and hydrogen in any proportion. The temperature range of the rapid thermal annealing treatment is 400 to 1500°C. Time is 10~90min;

D、采用MOCVD法外延生长0.3~0.6μm的N型氮化物,硅的掺杂浓度为2e16cm-3D. Use the MOCVD method to epitaxially grow N-type nitride of 0.3 to 0.6 μm, and the doping concentration of silicon is 2e16cm -3 ;

E、多次重复步骤B至步骤D,直至生成出规定厚度的轻掺杂P型氮化物屏蔽环。E. Repeat steps B to D multiple times until a lightly doped P-type nitride shielding ring with a specified thickness is generated.

Ⅲ族氮化物材料体系可以氮化镓材料。Group III nitride material systems can be gallium nitride materials.

上述具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构在高频、高压和大功率的功率电子与集成系统中的应用。The above-mentioned Group III nitride vertical power device structure with a shielding ring structure is used in high-frequency, high-voltage and high-power power electronics and integrated systems.

本发明的有益效果为:The beneficial effects of the present invention are:

1、本发明在垂直型混合PiN结势垒肖特基二极管的重掺杂p-GaN区域底部设置阶梯状浅掺杂阶梯状p-GaN区域,形成屏蔽环结构,有效地缓解在重掺杂p-GaN区域拐角处的局部电场聚集问题,从而提高器件的反向阻断性能。1. The present invention sets a stepped lightly doped stepped p-GaN region at the bottom of the heavily doped p-GaN region of the vertical mixed PiN junction barrier Schottky diode to form a shielding ring structure, which effectively alleviates the problem of heavy doping. The problem of local electric field concentration at the corners of the p-GaN region improves the reverse blocking performance of the device.

2、本发明利用ICP干法刻蚀形成沟槽区域,然后使用MOCVD二次外延生长浅掺杂阶梯状p-GaN屏蔽环。本发明制备方法适用于III族氮化物体系,工艺相对简单,且激活效率较高,获得的P型结构较为稳定。本发明所涉及的相关工艺是现有的,具体的工艺条件和沉积温度等也是本领域技术人员所熟知的。2. The present invention uses ICP dry etching to form the trench area, and then uses MOCVD secondary epitaxial growth to grow a shallowly doped stepped p-GaN shielding ring. The preparation method of the present invention is suitable for Group III nitride systems, the process is relatively simple, the activation efficiency is high, and the obtained P-type structure is relatively stable. The relevant processes involved in the present invention are existing, and the specific process conditions and deposition temperatures are also well known to those skilled in the art.

附图说明Description of the drawings

图1为本发明提出的具有浅掺杂阶梯状p-GaN屏蔽环的混合PiN结势垒肖特基二极管的结构示意图;Figure 1 is a schematic structural diagram of a hybrid PiN junction barrier Schottky diode with a lightly doped stepped p-GaN shielding ring proposed by the present invention;

图2为传统平面混合PiN结势垒肖特基二极管的结构示意图;Figure 2 is a schematic structural diagram of a traditional planar hybrid PiN junction barrier Schottky diode;

图3为阶梯状p-GaN屏蔽环的镁掺杂浓度和器件反向击穿电压的关系图。Figure 3 is a graph showing the relationship between the magnesium doping concentration of the stepped p-GaN shielding ring and the reverse breakdown voltage of the device.

图4为阶梯状p-GaN屏蔽环的上阶梯厚度和器件反向击穿电压的关系图;Figure 4 shows the relationship between the upper step thickness of the stepped p-GaN shielding ring and the reverse breakdown voltage of the device;

图5为阶梯状p-GaN屏蔽环的下阶梯厚度和器件反向击穿电压的关系图。Figure 5 shows the relationship between the lower step thickness of the stepped p-GaN shielding ring and the reverse breakdown voltage of the device.

具体实施方式Detailed ways

下面结合说明书附图和实施例对本发明作进一步限定,但不限于此。The present invention will be further limited below with reference to the accompanying drawings and examples of the description, but is not limited thereto.

实施例1Example 1

一种具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构,如图1所示,由下自上依次包括阴极电极、重掺杂N型氮化镓衬底区、轻掺杂N型氮化镓漂移区、重掺杂P型氮化镓区、阳极电极,在轻掺杂N型氮化镓漂移区中重掺杂P型氮化镓区下方嵌入有轻掺杂P型氮化镓屏蔽环;浅掺杂阶梯状p-GaN屏蔽环位于重掺杂p-GaN的下方,其可与n型浅掺杂的漂移层形成PN结,耗尽作用可以调控重掺杂p-GaN结构拐角处的强电场。A Group III nitride vertical power device structure with a shielded ring structure, as shown in Figure 1, including from bottom to top a cathode electrode, a heavily doped N-type gallium nitride substrate region, a lightly doped N-type nitrogen Gallium drift region, heavily doped P-type gallium nitride region, anode electrode, lightly doped P-type gallium nitride is embedded below the heavily doped P-type gallium nitride region in the lightly doped N-type gallium nitride drift region Shielding ring; the shallowly doped stepped p-GaN shielding ring is located below the heavily doped p-GaN. It can form a PN junction with the n-type shallowly doped drift layer, and the depletion effect can regulate the heavily doped p-GaN structure. Strong electric field around the corner.

传统平面混合PiN结势垒肖特基二极管的结构如图2所示,通过大量仿真计算分析得知,在轻掺杂N型氮化镓漂移区嵌入有轻掺杂P型氮化镓屏蔽环,可以在保持器件尺寸不变的前提下,大幅度提高器件的反向耐压能力,同时反向漏电也得到了进一步的降低,使器件应用在更高电压场景下成为可能。The structure of a traditional planar hybrid PiN junction barrier Schottky diode is shown in Figure 2. Through a large number of simulation calculations and analysis, it is known that a lightly doped P-type gallium nitride shielding ring is embedded in the lightly doped N-type gallium nitride drift region. , the reverse voltage withstand capability of the device can be greatly improved while keeping the size of the device unchanged. At the same time, the reverse leakage has been further reduced, making it possible for the device to be applied in higher voltage scenarios.

实施例2Example 2

根据实施例1所述的一种具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构,其区别在于:The difference between a Group III nitride vertical power device structure with a shielding ring structure according to Embodiment 1 is:

轻掺杂P型氮化镓屏蔽环呈阶梯状,上阶梯的厚度T1为0.5-2.0μm,下阶梯的厚度T2为1.0-10.0μm,下阶梯的宽度W为1.0-4.0μm;轻掺杂P型氮化镓屏蔽环中镁离子掺杂浓度为1e15cm-3-5e17cm-3The lightly doped P-type gallium nitride shielding ring is in the shape of a step. The thickness of the upper step T1 is 0.5-2.0μm, the thickness of the lower step T2 is 1.0-10.0μm, and the width W of the lower step is 1.0-4.0μm; light The magnesium ion doping concentration in the doped P-type gallium nitride shielding ring is 1e15cm -3 -5e17cm -3 .

当阶梯厚度T1、T2取值较大时,屏蔽环结构更加深入器件内部,耗尽区可以拓展到漂移层的深处,承担电压的区域增大,因此可以实现更高的反向击穿电压。镁离子掺杂浓度的选取,可以保证屏蔽环结构的有效耗尽保护作用,避免浓度过低时屏蔽环的耗尽作用太小可忽略,以及浓度过高时强耗尽作用造成局部电场聚集,引起器件的提前击穿。When the step thickness T 1 and T 2 are larger, the shielding ring structure goes deeper into the device, the depletion region can be expanded to the depth of the drift layer, and the area that bears the voltage increases, so a higher reverse voltage can be achieved. through voltage. The selection of the magnesium ion doping concentration can ensure the effective depletion protection of the shielding ring structure, and avoid the depletion effect of the shielding ring being too small and negligible when the concentration is too low, and the strong depletion effect causing local electric field accumulation when the concentration is too high. Cause premature breakdown of the device.

实施例3Example 3

根据实施例2所述的一种具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构,其区别在于:The difference between a Group III nitride vertical power device structure with a shielding ring structure according to Embodiment 2 is:

上阶梯的厚度T1为2.0μm,下阶梯的厚度T2为8.0μm,下阶梯的宽度W为2μm。The thickness T 1 of the upper step is 2.0 μm, the thickness T 2 of the lower step is 8.0 μm, and the width W of the lower step is 2 μm.

轻掺杂P型氮化镓屏蔽环中镁离子掺杂浓度为3e16cm-3The magnesium ion doping concentration in the lightly doped P-type gallium nitride shielding ring is 3e16cm -3 .

重掺杂N型氮化镓衬底区厚度为2μm,掺杂元素为硅,掺杂浓度为5e18cm-3;轻掺杂N型氮化镓漂移区厚度为15μm,掺杂元素为硅,掺杂浓度为2e16cm-3。重掺杂P型氮化镓区结构为方形,深度为2μm,宽度为4μm,掺杂离子为Mg离子,掺杂浓度为1e18cm-3。中间肖特基接触宽度设置为2μm。The thickness of the heavily doped N-type gallium nitride substrate region is 2 μm, the doping element is silicon, and the doping concentration is 5e18cm -3 ; the thickness of the lightly doped N-type gallium nitride drift region is 15 μm, the doping element is silicon, and the doping concentration is 5e18cm -3 The impurity concentration is 2e16cm -3 . The structure of the heavily doped P-type gallium nitride region is square, with a depth of 2 μm and a width of 4 μm. The doping ions are Mg ions, and the doping concentration is 1e18cm -3 . The middle Schottky contact width is set to 2μm.

实施例4Example 4

实施例1或2任一所述的具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构的制备方法,包括步骤如下:The method for preparing a Group III nitride vertical power device structure with a shielded ring structure as described in either embodiment 1 or 2 includes the following steps:

(1)在阴极电极上依次生长重掺杂N型氮化镓衬底区、轻掺杂N型氮化镓漂移区;(1) Sequentially grow a heavily doped N-type gallium nitride substrate region and a lightly doped N-type gallium nitride drift region on the cathode electrode;

(2)对轻掺杂N型氮化镓漂移区进行ICP刻蚀后,进行二次外延生长形成阶梯状的轻掺杂P型氮化镓屏蔽环;即得到具备浅掺杂阶梯状p-GaN屏蔽环的垂直型MPS二极管;利用MOCVD进行二次外延生长,材料层与层之间轮廓清晰,且分布均匀,避免了离子注入方式中材料的晶格损伤。(2) After ICP etching the lightly doped N-type gallium nitride drift region, perform secondary epitaxial growth to form a stepped lightly doped P-type gallium nitride shielding ring; that is, a lightly doped stepped p- Vertical MPS diode with GaN shielding ring; secondary epitaxial growth is performed using MOCVD. The outlines between the material layers are clear and evenly distributed, which avoids lattice damage to the material during ion implantation.

具体实现步骤包括:Specific implementation steps include:

①利用干法刻蚀工艺,在轻掺杂N型氮化镓漂移区上刻蚀沟槽区域,对刻蚀表面进行损伤处理;①Use a dry etching process to etch the trench area on the lightly doped N-type gallium nitride drift area, and damage the etched surface;

②利用二氧化硅作为硬质掩膜,遮挡未刻蚀的轻掺杂N型氮化镓漂移区,分别利用氨气(NH3)作为N源,二茂镁(Cp2Mg)作为掺杂源,H2作为载气,采用MOCVD法在轻掺杂N型氮化镓漂移区上表面同质外延一层P型氮化镓;②Use silicon dioxide as a hard mask to block the unetched lightly doped N-type gallium nitride drift region, use ammonia (NH 3 ) as the N source, and magnesium cyclocene (Cp 2 Mg) as the dopant. Source, H 2 as carrier gas, use MOCVD method to homoepitaxially grow a layer of P-type gallium nitride on the upper surface of the lightly doped N-type gallium nitride drift region;

③MOCVD炉内原位退火,激活P型掺杂的镁离子,生长形成阶梯状的轻掺杂P型氮化镓屏蔽环。③ In-situ annealing in the MOCVD furnace activates P-type doped magnesium ions and grows to form a stepped lightly doped P-type gallium nitride shielding ring.

(3)继续依次外延生长重掺杂P型氮化镓区、阳极电极,既得。(3) Continue to epitaxially grow the heavily doped P-type gallium nitride region and the anode electrode in sequence, and the result is obtained.

实施例5Example 5

根据实施例4所述的具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构的制备方法,其区别在于:According to the preparation method of a Group III nitride vertical power device structure with a shielding ring structure described in Embodiment 4, the difference is that:

步骤(2)中,进行ICP刻蚀后,进行多次外延加离子注入的工艺生长形成阶梯状的轻掺杂P型氮化镓屏蔽环,具体实现步骤包括:In step (2), after ICP etching, multiple epitaxy and ion implantation processes are performed to grow a stepped lightly doped P-type gallium nitride shielding ring. The specific implementation steps include:

A、利用干法刻蚀工艺,在轻掺杂N型氮化镓漂移区上刻蚀沟槽区域,对刻蚀表面进行损伤处理;A. Use a dry etching process to etch the trench area on the lightly doped N-type gallium nitride drift area, and damage the etched surface;

B、利用离子注入机在轻掺杂N型氮化镓漂移区的沟槽区域底面进行Mg离子注入,离子注入的功率能量设置为150~300keV,注入深度为0.3~0.6μm;B. Use an ion implanter to implant Mg ions on the bottom surface of the trench area of the lightly doped N-type gallium nitride drift region. The power energy of the ion implantation is set to 150~300keV, and the implantation depth is 0.3~0.6μm;

C、在氮气、氨气、氩气、氢气中的一种或两种以上任意配比的混合物的气体氛围中,进行快速热退火处理,快速热退火处理的温度范围为400~1500℃,退火时间为10~90min;以提高Mg离子在氮化镓内的激活率;C. Perform rapid thermal annealing treatment in a gas atmosphere of one or more mixtures of nitrogen, ammonia, argon, and hydrogen in any proportion. The temperature range of the rapid thermal annealing treatment is 400 to 1500°C. The time is 10~90min; to increase the activation rate of Mg ions in gallium nitride;

D、采用MOCVD法外延生长0.3~0.6μm的N型氮化镓,硅的掺杂浓度为2e16cm-3D. Use MOCVD method to epitaxially grow 0.3-0.6μm N-type gallium nitride, and the doping concentration of silicon is 2e16cm -3 ;

E、多次重复步骤B至步骤D,直至生成出规定厚度的轻掺杂P型氮化镓屏蔽环。E. Repeat steps B to D multiple times until a lightly doped P-type gallium nitride shielding ring with a specified thickness is generated.

离子注入工艺实现注入层与基体之间没有界面,结合强度高、附着性好,不会改变器件的外形尺寸和表面光洁度。The ion implantation process achieves no interface between the implanted layer and the substrate, high bonding strength and good adhesion, and does not change the external dimensions and surface finish of the device.

实施例6Example 6

实施例3所述的具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构的制备方法,包括步骤如下:The preparation method of a Group III nitride vertical power device structure with a shielding ring structure described in Embodiment 3 includes the following steps:

(1)分别利用三甲基铵(TMGa),氨气(NH3)作为Ga源和N源,SiH3CH3作为N型杂质源,H2作为载气,在MOCVD中实现在2μm厚的低缺陷,低位错的重掺杂N型氮化镓衬底区,硅的掺杂浓度为5e18cm-3(1) Use trimethylammonium (TMGa) and ammonia (NH 3 ) as Ga source and N source respectively, Si H 3 CH 3 as N-type impurity source, and H 2 as carrier gas to achieve 2 μm in MOCVD. Thick, low-defect, low-dislocation heavily doped N-type gallium nitride substrate region, the silicon doping concentration is 5e18cm -3 ;

(2)分别利用三甲基铵(TMGa),氨气(NH3)作为Ga源和N源,SiH3CH3作为N型杂质源,H2作为载气,在重掺杂N型氮化镓衬底区表面同质外延一层15μm厚的轻掺杂N型氮化镓漂移区,硅的掺杂浓度为2e16cm-3(2) Use trimethylammonium (TMGa) and ammonia (NH 3 ) as the Ga source and N source respectively, Si H 3 CH 3 as the N-type impurity source, H 2 as the carrier gas, and heavily dope the N-type A 15 μm thick lightly doped N-type gallium nitride drift region is homoepitaxially formed on the surface of the gallium nitride substrate area, and the silicon doping concentration is 2e16cm -3 ;

(3)在外延片上利用SiO2做硬质掩膜版,起到遮挡外延片中部分不进行刻蚀区域的作用,在Cl2/BCl3/Ar的混合气氛中利用电感耦合等离子体刻蚀(ICP)进行阶梯沟槽区域刻蚀;(3) Use Si O 2 as a hard mask on the epitaxial wafer to block some areas of the epitaxial wafer that will not be etched, and use inductively coupled plasma in a mixed atmosphere of Cl 2 /BCl 3 /Ar Etching (ICP) is used to etch the step trench area;

(4)干法刻蚀后,材料表面存在大量的带有斜坡的尖峰和毛刺,将样品放入25%的TMAH溶液中,在85℃条件下处理1小时去除因刻蚀造成的表面损伤:然后将样品放入丙酮中加热至85℃,水浴加热10分钟;异丙醇超声清洗5分钟,去离子水冲洗6遍,氮气吹干后使用热板烘干;将浓度为25wt%的氨水溶液水浴加热至85℃,放入样品,水浴加热10分钟;从氨水中取出样品后使用去离子水冲洗6遍,去除表面的氨水,终止氨水的表面处理作用,吹干后使用热板烘干;利用原子力显微镜测试刻蚀深度和刻蚀形貌;(4) After dry etching, there are a large number of sharp peaks and burrs with slopes on the material surface. Put the sample into a 25% TMAH solution and treat it at 85°C for 1 hour to remove the surface damage caused by etching: Then put the sample into acetone and heat it to 85°C, and heat it in a water bath for 10 minutes; ultrasonically clean it with isopropyl alcohol for 5 minutes, rinse it 6 times with deionized water, blow it dry with nitrogen and dry it using a hot plate; add an ammonia solution with a concentration of 25wt% Heat the water bath to 85°C, put the sample in, and heat in the water bath for 10 minutes; remove the sample from the ammonia water and rinse it with deionized water 6 times to remove the ammonia water on the surface, terminate the surface treatment effect of the ammonia water, blow dry and dry using a hot plate; Use atomic force microscopy to test the etching depth and etching morphology;

(5)利用三甲基镓(TMGa)、二茂镁(Cp2Mg)和氨气(NH3)分别作为Ga、Mg和N源,H2作为载气,利用MOCVD方法在阶梯状沟槽区域同质外延生长P型浅掺杂氮化镓层,形成阶梯屏蔽环,镁的掺杂浓度区间为1e16cm-3-8e16cm-3(5) Use trimethylgallium (TMGa), magnocene (Cp 2 Mg) and ammonia (NH 3 ) as the Ga, Mg and N sources respectively, H 2 as the carrier gas, and use the MOCVD method to create a step-shaped trench. Regional homoepitaxial growth of P-type lightly doped gallium nitride layer to form a stepped shielding ring, the magnesium doping concentration range is 1e16cm -3 -8e16cm -3 ;

(6)继续依次外延生长重掺杂P型氮化镓区、阳极电极。(6) Continue to epitaxially grow the heavily doped P-type gallium nitride region and the anode electrode in sequence.

实施例7Example 7

实施例3所述的具有屏蔽环结构的Ⅲ族氮化物垂直型功率器件结构的制备方法,利用多次外延加离子注入方式制备,包括步骤如下:The preparation method of the Group III nitride vertical power device structure with a shielded ring structure described in Example 3 is prepared by multiple epitaxy plus ion implantation, including the following steps:

(1)分别利用三甲基铵(TMGa),氨气(NH3)作为Ga源和N源,SiH3CH3作为N型杂质源,H2作为载气,在MOCVD中实现在2μm厚的低缺陷,低位错的N型重掺杂氮化镓衬底层,硅的掺杂浓度为5e18cm-3(1) Use trimethylammonium (TMGa) and ammonia (NH 3 ) as Ga source and N source respectively, Si H 3 CH 3 as N-type impurity source, and H 2 as carrier gas to achieve 2 μm in MOCVD. Thick N-type heavily doped gallium nitride substrate layer with low defects and low dislocations, the silicon doping concentration is 5e18cm -3 ;

(2)分别利用三甲基铵(TMGa),氨气(NH3)作为Ga源和N源,SiH3CH3作为N型杂质源,H2作为载气,在N型重掺杂氮化镓衬底层表面同质外延一层15μm厚的N型轻掺杂氮化镓漂移层,硅的掺杂浓度为2e16cm-3(2) Use trimethylammonium (TMGa) and ammonia (NH 3 ) as Ga source and N source respectively, Si H 3 CH 3 as N-type impurity source, H 2 as carrier gas, and heavily doped in N-type A 15 μm thick N-type lightly doped gallium nitride drift layer is homoepitaxially formed on the surface of the gallium nitride substrate layer, and the silicon doping concentration is 2e16cm -3 ;

(3)在外延片上利用SiO2做硬质掩膜版,起到遮挡外延片中部分不进行刻蚀区域的作用,在Cl2/BCl3/Ar的混合气氛中利用电感耦合等离子体刻蚀(ICP)进行阶梯沟槽区域刻蚀;(3) Use Si O 2 as a hard mask on the epitaxial wafer to block some areas of the epitaxial wafer that will not be etched, and use inductively coupled plasma in a mixed atmosphere of Cl 2 /BCl 3 /Ar Etching (ICP) is used to etch the step trench area;

(4)干法刻蚀后,材料表面存在大量的带有斜坡的尖峰和毛刺,将样品放入25%的TMAH溶液中,在85℃条件下处理1小时去除因刻蚀造成的表面损伤:然后将样品放入丙酮中加热至85℃,水浴加热10分钟;异丙醇超声清洗5分钟,去离子水冲洗6遍,氮气吹干后使用热板烘干;将浓度为25wt%的氨水溶液水浴加热至85℃,放入样品,水浴加热10分钟;从氨水中取出样品后使用去离子水冲洗6遍,去除表面的氨水,终止氨水的表面处理作用,吹干后使用热板烘干;利用原子力显微镜测试刻蚀深度和刻蚀形貌;(4) After dry etching, there are a large number of sharp peaks and burrs with slopes on the material surface. Put the sample into a 25% TMAH solution and treat it at 85°C for 1 hour to remove the surface damage caused by etching: Then put the sample into acetone and heat it to 85°C, and heat it in a water bath for 10 minutes; ultrasonically clean it with isopropyl alcohol for 5 minutes, rinse it 6 times with deionized water, blow it dry with nitrogen and dry it using a hot plate; add an ammonia solution with a concentration of 25wt% Heat the water bath to 85°C, put the sample in, and heat in the water bath for 10 minutes; remove the sample from the ammonia water and rinse it with deionized water 6 times to remove the ammonia water on the surface, terminate the surface treatment effect of the ammonia water, blow dry and dry using a hot plate; Use atomic force microscopy to test the etching depth and etching morphology;

(5)利用三甲基镓(TMGa),氨气(NH3)分别作为Ga源和N源,H2作为载气,利用MOCVD方法在阶梯状沟槽区域同质外延生长300nm~500nm厚的N型氮化镓层;(5) Use trimethylgallium (TMGa) and ammonia (NH 3 ) as the Ga source and N source respectively, H 2 as the carrier gas, and use the MOCVD method to homoepitaxially grow 300nm to 500nm thick in the stepped trench area. N-type gallium nitride layer;

(6)利用离子注入机对阶梯状沟槽底部外延生长的N型氮化镓层进行Mg离子注入,调整离子注入的能量,实现300nm~500nm厚P型氮化镓层作为屏蔽环区域,随后去除表面SiO2硬质掩膜,进行快速热退火处理(PIA),处理过程为在氮气氛围中进行快速热退火处理,高温退火的温度范围为450℃,退火时间为20分钟,以提高P型氮化镓层内部的空穴激活率。(6) Use an ion implanter to implant Mg ions into the epitaxially grown N-type gallium nitride layer at the bottom of the stepped trench, and adjust the energy of the ion implantation to achieve a 300nm to 500nm thick P-type gallium nitride layer as the shielding ring area, and then Remove the surface SiO 2 hard mask and perform rapid thermal annealing (PIA). The process is rapid thermal annealing in a nitrogen atmosphere. The temperature range of high-temperature annealing is 450°C and the annealing time is 20 minutes to improve the P-type Hole activation rate inside the gallium nitride layer.

(7)多次重复步骤(5)与步骤(6),生长出规定厚度的p-GaN屏蔽环;(7) Repeat steps (5) and (6) multiple times to grow a p-GaN shielding ring with a specified thickness;

(8)继续依次外延生长重掺杂P型氮化镓区、阳极电极。(8) Continue to epitaxially grow the heavily doped P-type gallium nitride region and the anode electrode in sequence.

实施例8Example 8

变化实施例1中具有浅掺杂阶梯状p-GaN屏蔽环的平面混合PiN结势垒肖特基二极管结构中屏蔽环的镁离子掺杂浓度(变化范围为1e16cm-3-8e16cm-3),通过数值仿真获得器件的反向击穿电压与浅掺杂阶梯状p-GaN屏蔽环区域中镁离子掺杂浓度的关系图,如图3所示。The magnesium ion doping concentration of the shielding ring in the planar mixed PiN junction barrier Schottky diode structure with a shallowly doped stepped p-GaN shielding ring in Variation Embodiment 1 (the variation range is 1e16cm -3 -8e16cm -3 ), Through numerical simulation, the relationship between the reverse breakdown voltage of the device and the magnesium ion doping concentration in the shallowly doped stepped p-GaN shielding ring region is obtained, as shown in Figure 3.

图3中标注出了无屏蔽环结构的传统平面混合PiN结势垒肖特基二极管的反向击穿电压为1123V,用作参照。此时N型浅掺杂漂移层浓度设置为2e16cm-3。相对比于传统平面混合PiN结势垒肖特基二极管的反向击穿电压(1123V),具有浅掺杂阶梯状p-GaN屏蔽环的器件表现出更高的反向击穿电压;进一步地,最优镁离子掺杂浓度为3e16cm-3。随着镁离子掺杂浓度的增大,反向击穿电压表现出先增大后减小的趋势,但均表现出高于1123V的反向击穿电压数值。通过TCAD仿真的结果分析可得,具备了阶梯状屏蔽环结构之后,可以有效提高反向击穿电压,表现出更优良的反向阻断特性,通过优化镁离子的掺杂浓度,可以进一步实现更好的反向耐压能力。反向阻断性能的优劣主要表现在反向击穿电压的大小上。The reverse breakdown voltage of a traditional planar hybrid PiN junction barrier Schottky diode without a shielding ring structure is marked as 1123V in Figure 3, which is used as a reference. At this time, the concentration of the N-type lightly doped drift layer is set to 2e16cm -3 . Compared with the reverse breakdown voltage (1123V) of the traditional planar hybrid PiN junction barrier Schottky diode, the device with a shallowly doped stepped p-GaN shielding ring shows a higher reverse breakdown voltage; further , the optimal magnesium ion doping concentration is 3e16cm -3 . As the magnesium ion doping concentration increases, the reverse breakdown voltage shows a trend of first increasing and then decreasing, but all show reverse breakdown voltage values higher than 1123V. Through the analysis of TCAD simulation results, it can be seen that with the stepped shielding ring structure, the reverse breakdown voltage can be effectively improved and better reverse blocking characteristics can be achieved. By optimizing the doping concentration of magnesium ions, this can be further achieved. Better reverse pressure resistance. The quality of reverse blocking performance is mainly reflected in the magnitude of reverse breakdown voltage.

实施例9Example 9

变化实施例1中具有浅掺杂阶梯状p-GaN屏蔽环的平面混合PiN结势垒肖特基二极管结构中屏蔽环的上阶梯厚度(变化范围为0.5μm-2.0μm),通过数值仿真获得器件的反向击穿电压与浅掺杂阶梯状p-GaN屏蔽环上阶梯厚度的关系图,如图4所示。此时阶梯状p-GaN屏蔽环的镁掺杂浓度设置为4e16cm-3。T1的值越大,表现出越高的反向击穿电压。随着屏蔽环上阶梯厚度的增大,反向击穿电压表现出单调上升的趋势,在T1为2.0μm的条件下,实现最高1811V的反向击穿电压。The upper step thickness of the shielding ring in the planar mixed PiN junction barrier Schottky diode structure with a lightly doped stepped p-GaN shielding ring in Variation Embodiment 1 (variation range is 0.5μm-2.0μm), obtained through numerical simulation The relationship between the reverse breakdown voltage of the device and the step thickness on the shallowly doped stepped p-GaN shielding ring is shown in Figure 4. At this time, the magnesium doping concentration of the stepped p-GaN shielding ring is set to 4e16cm -3 . The larger the value of T1 , the higher the reverse breakdown voltage is exhibited. As the thickness of the step on the shielding ring increases, the reverse breakdown voltage shows a monotonous rising trend, and the highest reverse breakdown voltage of 1811V is achieved under the condition that T1 is 2.0μm.

实施例10Example 10

变化实施例1中具有浅掺杂阶梯状p-GaN屏蔽环的平面混合PiN结势垒肖特基二极管结构中屏蔽环的下阶梯厚度(变化范围为1μm-10μm),通过数值仿真获得器件的反向击穿电压与浅掺杂阶梯状p-GaN屏蔽环下阶梯厚度的关系图,如图5所示。此时阶梯状p-GaN屏蔽环的镁掺杂浓度设置为4e16cm-3。T2的值越大,表现出越高的反向击穿电压,并在其宽度到达8μm时趋于饱和,器件内部结构表现为p-GaN屏蔽环下阶梯接近于n型重掺杂衬底区。随着屏蔽环下阶梯厚度的增大,反向击穿电压表现出近乎单调上升的趋势,在T2为10μm的条件下,实现最高2381V的反向击穿电压。通过TCAD仿真的结果分析可得,越大的阶梯厚度可以实现越深的耗尽区深度,有效的利用N型轻掺杂氮化镓漂移层来均匀电场分布,以实现较好的反向阻断性能。In Variation Embodiment 1, the lower step thickness of the shielding ring in the planar mixed PiN junction barrier Schottky diode structure with a shallowly doped stepped p-GaN shielding ring (the variation range is 1 μm-10 μm) was obtained through numerical simulation. The relationship between the reverse breakdown voltage and the step thickness under the lightly doped stepped p-GaN shielding ring is shown in Figure 5. At this time, the magnesium doping concentration of the stepped p-GaN shielding ring is set to 4e16cm -3 . The larger the value of T 2 is, the higher the reverse breakdown voltage will be, and it will tend to be saturated when its width reaches 8μm. The internal structure of the device appears to be that the lower step of the p-GaN shielding ring is close to the n-type heavily doped substrate. district. As the thickness of the step under the shielding ring increases, the reverse breakdown voltage shows an almost monotonic rising trend. Under the condition of T2 of 10μm, the highest reverse breakdown voltage of 2381V is achieved. Through the analysis of TCAD simulation results, it can be seen that the larger the step thickness, the deeper the depletion region depth can be achieved, and the N-type lightly doped gallium nitride drift layer can be effectively used to uniform the electric field distribution to achieve better reverse resistance. interruption performance.

Claims (10)

1. The III-nitride vertical power device structure with the shielding ring structure is characterized by comprising a cathode electrode, a heavily-doped N-type nitride substrate region, a lightly-doped N-type nitride drift region, a heavily-doped P-type nitride region and an anode electrode from bottom to top in sequence, wherein a lightly-doped P-type nitride shielding ring is embedded below the heavily-doped P-type nitride region in the lightly-doped N-type nitride drift region;
the lightly doped P-type nitride shielding ring is stepped and has the thickness T of the upper step 1 Thickness T of the lower step is 0.5-2.0 μm 2 The width W of the lower step is 1.0-4.0 μm and is 1.0-10.0 μm.
2. The group iii nitride vertical power device structure with shield ring structure of claim 1, wherein the thickness T of the upper step 1 Thickness T of the lower step of 2.0 μm 2 The width W of the lower step was 8.0 μm and 2. Mu.m.
3. The group iii nitride vertical power device structure with shield ring structure of claim 1, wherein the lightly doped P-type nitride shieldThe doping concentration of magnesium ions in the ring is 1e15cm -3 -5e17cm -3
4. The vertical power device structure of group iii nitride with shielding ring structure of claim 1, wherein the doping concentration of magnesium ions in the lightly doped P-type nitride shielding ring is 1e16cm -3 -8e16cm -3
5. The group iii nitride vertical power device structure of claim 1, wherein the magnesium ion doping concentration in the lightly doped P-type nitride shield ring is 3e16cm -3
6. The vertical power device structure of claim 1, wherein the heavily doped N-type nitride substrate region is a heavily doped N-type gallium nitride substrate region, the lightly doped N-type nitride drift region is a lightly doped N-type gallium nitride drift region, and the heavily doped P-type nitride region is a heavily doped P-type gallium nitride region.
7. The method for manufacturing a group iii nitride vertical power device structure having a shield ring structure as set forth in any one of claims 1 to 6, comprising the steps of:
(1) Sequentially growing a heavily doped N-type nitride substrate region and a lightly doped N-type nitride drift region on the cathode electrode;
(2) Performing ICP etching on the lightly doped N-type nitride drift region, and performing secondary epitaxial growth to form a stepped lightly doped P-type nitride shielding ring;
(3) And continuing to epitaxially grow a heavily doped P-type nitride region and an anode electrode in sequence to obtain the semiconductor device.
8. The method for manufacturing a group iii nitride vertical power device structure with a shielding ring structure according to claim 7, wherein in the step (2), the step of performing a second epitaxial growth to form a stepped lightly doped P-type nitride shielding ring, the specific implementation steps include:
(1) etching a groove region on the lightly doped N-type nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
(2) the silicon dioxide is used as a hard mask to shield an unetched lightly doped N-type nitride drift region, ammonia is used as an N source, magnesium oxide is used as a doping source, and H 2 As carrier gas, adopting MOCVD method to homoepitaxial a layer of P-type nitride on the upper surface of lightly doped N-type nitride drift region;
(3) and (3) in-situ annealing in the MOCVD furnace, activating P-type doped magnesium ions, and growing to form a stepped lightly doped P-type nitride shielding ring.
9. The method for manufacturing a group iii nitride vertical power device structure with a shielding ring structure according to claim 7, wherein in the step (2), after performing ICP etching, a step-shaped lightly doped P-type nitride shielding ring is formed by performing epitaxial and ion implantation for a plurality of times, and the specific implementation steps include:
A. etching a groove region on the lightly doped N-type nitride drift region by using a dry etching process, and performing damage treatment on the etched surface;
B. carrying out Mg ion implantation on the bottom surface of the groove area of the lightly doped N-type nitride drift region by using an ion implanter, wherein the power energy of the ion implantation is set to be 150-300 keV, and the implantation depth is 0.3-0.6 mu m;
C. carrying out rapid thermal annealing treatment in a gas atmosphere of a mixture of one or more than two of nitrogen, ammonia, argon and hydrogen in any proportion, wherein the temperature range of the rapid thermal annealing treatment is 400-1500 ℃ and the annealing time is 10-90 min;
D. epitaxially growing N-type nitride with thickness of 0.3-0.6 μm by MOCVD method, and doping concentration of silicon is 2e16cm -3
E. Repeating the steps B to D for a plurality of times until the lightly doped P-type nitride shielding ring with the specified thickness is generated.
10. Use of a group iii nitride vertical power device structure with a shield ring structure according to any of claims 1-6, characterized in that the group iii nitride vertical power device structure with a shield ring structure is used in high frequency, high voltage and high power electronics and integration systems.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251772A (en) * 2007-03-30 2008-10-16 Toshiba Corp Semiconductor device
CN104425574A (en) * 2013-08-28 2015-03-18 三菱电机株式会社 Silicon carbide semiconductor device
CN105405897A (en) * 2015-10-29 2016-03-16 中山大学 Longitudinal conduction-type GaN-based groove junction barrier Schottky diode and manufacturing method thereof
CN106024850A (en) * 2015-03-24 2016-10-12 三垦电气株式会社 Semiconductor device

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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251772A (en) * 2007-03-30 2008-10-16 Toshiba Corp Semiconductor device
CN104425574A (en) * 2013-08-28 2015-03-18 三菱电机株式会社 Silicon carbide semiconductor device
CN106024850A (en) * 2015-03-24 2016-10-12 三垦电气株式会社 Semiconductor device
CN105405897A (en) * 2015-10-29 2016-03-16 中山大学 Longitudinal conduction-type GaN-based groove junction barrier Schottky diode and manufacturing method thereof

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