CN113539827B - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, the method of forming a semiconductor structure comprising: providing a substrate; forming a dummy gate on the substrate; forming source-drain doped regions in the substrate at two sides of the pseudo gate; forming an interlayer dielectric layer covering the source-drain doped region on two sides of the pseudo gate; after the interlayer dielectric layer is formed, carrying out surface treatment on the dummy gate, wherein the surface treatment is suitable for reducing the surface contact angle of the dummy gate; after the surface treatment is carried out on the pseudo gate, removing the pseudo gate by adopting a wet etching process, and forming a gate opening in the interlayer dielectric layer; a gate structure is formed in the gate opening. The embodiment of the invention is suitable for reducing the surface contact angle of the dummy gate by carrying out surface treatment on the dummy gate, thereby being beneficial to improving the hydrophilicity of the dummy gate, being beneficial to enabling the wet etching process to remove the dummy gate cleanly and reducing the probability of generating the dummy gate residue in the process of removing the dummy gate by adopting the wet etching process, and improving the performance and the production yield of the semiconductor structure.

Description

Method for forming semiconductor structure

Technical Field

The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure.

Background Art

In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making the subthreshold leakage phenomenon, the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control over the channel and can effectively suppress the short channel effect; and compared with other devices, FinFETs have better compatibility with existing integrated circuit manufacturing.

In addition, in the field of semiconductor integrated circuit devices, as the size of transistors continues to shrink, high-K metal gate (HKMG) technology has gradually been widely used. At present, the process of forming HKMG structure transistors can be divided into the gate-first process and the gate-last process. Among them, the gate-last process usually forms a metal gate after the drain/source region ion implantation operation and the subsequent high-temperature annealing process are completed on the silicon wafer, and generally before forming the metal gate, a dummy gate is formed first, and then the dummy gate is removed to form a metal gate.

Summary of the invention

The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to reducing the probability of generating dummy gate residues, thereby facilitating improving the performance and production yield of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dummy gate on the substrate; forming source-drain doped regions in the substrate on both sides of the dummy gate; forming an interlayer dielectric layer covering the source-drain doped regions on both sides of the dummy gate; after forming the interlayer dielectric layer, performing surface treatment on the dummy gate to reduce the surface contact angle of the dummy gate; after performing surface treatment on the dummy gate, removing the dummy gate by a wet etching process to form a gate opening in the interlayer dielectric layer; and forming a gate structure in the gate opening.

Optionally, the method for forming the semiconductor structure further includes: after forming the interlayer dielectric layer and before performing surface treatment on the dummy gate, removing a portion of the thickness of the dummy gate, so that the top surface of the remaining dummy gate is higher than the top surface of the substrate.

Optionally, a dry etching process is used to remove a portion of the thickness of the dummy gate.

Optionally, the base includes a substrate and a fin protruding from the substrate; in the step of forming the dummy gate, the dummy gate spans the fin and covers a portion of the top and a portion of the side wall of the fin; in the step of removing a portion of the thickness of the dummy gate, the remaining top surface of the dummy gate is higher than the top surface of the fin.

Optionally, in the step of removing a portion of the thickness of the dummy gate, the distance from the remaining top surface of the dummy gate to the top surface of the fin is at least 200 angstroms.

Optionally, the step of performing surface treatment on the dummy gate includes: performing surface treatment on the dummy gate using an NH ₄ OH solution having a temperature higher than room temperature.

Optionally, the temperature of the NH ₄ OH solution is at least 50°C.

Optionally, the temperature of the NH ₄ OH solution is 50°C to 70°C.

Optionally, parameters for surface treatment of the dummy gate include: a ratio of NH ₄ OH to water in the NH ₄ OH solution of 1:40 to 1:4, and a treatment time of 20 seconds to 60 seconds.

Optionally, the etching solution of the wet etching process includes a tetramethylammonium hydroxide solution.

Optionally, the etching time of the wet etching process is 120 seconds to 360 seconds.

Optionally, in the step of forming the dummy gate, the dummy gate includes a dummy gate layer, and a material of the dummy gate layer includes polysilicon.

Optionally, in the step of forming the dummy gate, the material of the dummy gate layer includes silicon of a first crystal orientation; before performing surface treatment on the dummy gate, the method for forming the semiconductor structure includes: performing heat treatment to transform the silicon of the first crystal orientation into silicon of a second crystal orientation; performing surface treatment on the dummy gate to reduce the difference in etching rate between the silicon of the first crystal orientation and the silicon of the second crystal orientation by the wet etching process.

Optionally, the first crystal orientation is a <100> crystal orientation, and the second crystal orientation is a <111> crystal orientation.

Optionally, the wet etching process has an etching selectivity ratio of 1.8:1 to 3.7:1 for silicon in the first crystal orientation and silicon in the second crystal orientation.

Optionally, the heat treatment includes: using an epitaxial process to form the source and drain doped regions; or, after forming the source and drain doped regions and before forming the interlayer dielectric layer, annealing the source and drain doped regions; or, along the extension direction of the dummy gate, the dummy gate includes a cut-off region; after forming the interlayer dielectric layer and before performing surface treatment on the dummy gate, removing the dummy gate located in the cut-off region to form an isolation opening surrounded by the remaining dummy gate and the interlayer dielectric layer; and forming an isolation structure in the isolation opening.

Optionally, the process of forming the isolation structure includes a deposition process, and the process temperature of the deposition process is 500° C. to 700° C.

Optionally, the temperature of the epitaxial process is 700°C to 900°C.

Optionally, the process temperature of the annealing treatment is 800°C to 1100°C.

Optionally, in the step of providing a substrate, the substrate includes a substrate and a fin protruding from the substrate; in the step of forming the dummy gate, the dummy gate spans the fin and covers a portion of the top and a portion of the sidewall of the fin; in the step of forming the source-drain doped region, the source-drain doped region is formed in the fin on both sides of the dummy gate.

Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the interlayer dielectric layer, the dummy gate is also surface treated to reduce the surface contact angle of the dummy gate. By reducing the surface contact angle of the dummy gate, the hydrophilicity of the dummy gate is improved, so that in the process of removing the dummy gate by a wet etching process, the contact area between the etching solution and the dummy gate is increased, the etching rate of the dummy gate by the etching solution is increased, and the dummy gate is easier to be removed by the etching solution, which is beneficial to enable the wet etching process to completely remove the dummy gate and reduce the probability of generating dummy gate residues, which is beneficial to provide a good interface for the subsequent formation of a gate structure, and correspondingly beneficial to improving the performance and production yield of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 4 are schematic structural diagrams corresponding to various steps in a method for forming a semiconductor structure;

5 to 10 are schematic structural diagrams corresponding to the steps in an embodiment of a method for forming a semiconductor structure of the present invention.

DETAILED DESCRIPTION

The devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

1 to 4 , schematic structural diagrams corresponding to various steps in a method for forming a semiconductor structure are shown.

Referring to FIG1 , a substrate 1 is provided; a dummy gate 2 is formed on the substrate 1; source and drain doping regions (not shown) are formed in the substrate 1 on both sides of the dummy gate 2; and an interlayer dielectric layer 3 covering the source and drain doping regions is formed on the substrate 1 on both sides of the dummy gate 2. The material of the dummy gate 2 is polysilicon.

2 , a dry etching process is used to remove a portion of the thickness of the dummy gate 2 .

3 , a wet etching process is adopted to remove the remaining dummy gate 2 and form a gate opening 4 in the interlayer dielectric layer 3 .

4 , a gate structure 5 is formed in the gate opening 4 .

In the above formation method, in the process of removing the dummy gate 2 , the dummy gate 2 is likely to remain, thereby easily reducing the yield and the performance of the semiconductor structure.

Specifically, the inventors have found that the residue of the dummy gate 2 is usually silicon with a <111> crystal orientation.

Through the research of the inventors, it is found that in the step of forming the dummy gate 2, the material of the dummy gate 2 is usually polycrystalline silicon, and the polycrystalline silicon is usually of a <100> crystal orientation. In the subsequent process, a high-temperature process is usually also included. For example, in the formation process of the source and drain doping regions, an epitaxial process and an annealing process are usually required. The process temperatures of the epitaxial process and the annealing process are usually high. Silicon with a <100> crystal orientation is easily crystallized in a high-temperature environment and transformed into silicon with a <111> crystal orientation. The wet etching process for removing the dummy gate 2 is mainly used to remove silicon with a <100> crystal orientation. The etching rate of silicon with a <111> crystal orientation is usually low, which easily produces residues of the dummy gate 2.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a dummy gate on the substrate; forming source-drain doped regions in the substrate on both sides of the dummy gate; forming an interlayer dielectric layer covering the source-drain doped regions on both sides of the dummy gate; after forming the interlayer dielectric layer, performing surface treatment on the dummy gate, suitable for reducing the surface contact angle of the dummy gate; after performing surface treatment on the dummy gate, removing the dummy gate by a wet etching process, forming a gate opening in the interlayer dielectric layer; and forming a gate structure in the gate opening.

In the method for forming a semiconductor structure provided by an embodiment of the present invention, after forming the interlayer dielectric layer, the dummy gate is also surface treated to reduce the surface contact angle of the dummy gate. By reducing the surface contact angle of the dummy gate, the hydrophilicity of the dummy gate is improved, so that in the process of removing the dummy gate by a wet etching process, the contact area between the etching solution and the dummy gate is increased, the etching rate of the dummy gate by the etching solution is increased, and the dummy gate is easier to be removed by the etching solution, which is beneficial to the wet etching process to completely remove the dummy gate and reduce the probability of generating the dummy gate residue, which is beneficial to provide a good interface for the subsequent formation of a gate structure, and correspondingly beneficial to improving the performance and production yield of the semiconductor structure.

In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

5 to 10 are schematic structural diagrams corresponding to the steps in an embodiment of a method for forming a semiconductor structure of the present invention.

5 , a substrate 100 is provided.

The substrate 100 is used to provide a process platform for forming transistors.

In this embodiment, the substrate 100 is used to form a fin field effect transistor (FinFET) as an example, and the substrate 100 includes a substrate (not labeled) and a fin portion (not labeled) protruding from the substrate (not labeled). In other embodiments, the substrate may also be a planar substrate, and the substrate only includes a substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

The fin is used to provide a conductive channel when the device is working.

In this embodiment, the material of the fin is the same as that of the substrate, and the material of the fin is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.

In this embodiment, the substrate 100 includes a core region I for forming a core device and a peripheral region II for forming an input/output device.

Among them, core devices mainly refer to devices used inside the chip, which usually use lower voltages, and the operating frequency of core devices is usually higher; input/output devices are devices used when the chip interacts with external interfaces. The operating voltage of such devices is generally higher, and the operating frequency of input/output devices is usually lower.

In this embodiment, an isolation layer (not shown) is further formed on the substrate 100 of the core region I and the peripheral region II. The isolation layer is used to isolate adjacent devices. Specifically, the isolation layer is used to isolate the core region I and the peripheral region II.

The material of the isolation layer includes one or more of silicon oxide, silicon oxynitride and silicon nitride.

Subsequent steps also include: forming a dummy gate on the substrate 100 .

In this embodiment, after providing the substrate 100 and before forming the dummy gate, the method for forming the semiconductor structure further includes: forming a gate oxide layer 110 on the substrate 100 .

Accordingly, in the subsequent step of forming a dummy gate, the dummy gate is formed on the gate oxide layer 110 .

The gate oxide layer 110 can be used as a stop layer in the subsequent process of removing the dummy gate, thereby protecting the substrate 100. Specifically, in this embodiment, the gate oxide layer 110 is used to protect the fin.

The gate oxide layer 110 located in the peripheral region II is retained in subsequent processes. After the gate structure is subsequently formed, the gate oxide layer 110 located in the peripheral region II is also used to isolate the gate structure from the substrate 100 .

The material of the gate oxide layer 110 may be silicon oxide or silicon oxynitride. In this embodiment, the material of the gate oxide layer 110 is silicon oxide.

The process of forming the gate oxide layer 110 includes a deposition process or an oxidation process. Specifically, the deposition process may be an atomic layer deposition process, and the oxidation process includes a dry oxygen oxidation process or a wet oxygen oxidation process.

In this embodiment, during the process of forming the gate oxide layer 110 , the gate oxide layer 110 covers the surface of the fin.

Continuing to refer to FIG. 5 , a dummy gate 120 is formed on the substrate 100 .

The dummy gate 120 is used to occupy a space for subsequently forming a gate structure.

In this embodiment, in the step of forming the dummy gate 120 , the dummy gate 120 spans across the fin and covers a portion of the top and a portion of the sidewall of the fin.

In this embodiment, in the step of forming the dummy gate 120 , the dummy gate 120 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon.

In this embodiment, in the step of forming the dummy gate 120, the material of the dummy gate layer includes silicon of a first crystal orientation. Specifically, in this embodiment, the first crystal orientation is a <100> crystal orientation.

In this embodiment, the step of forming the dummy gate 120 includes: forming a dummy gate material layer (not shown) covering the substrate 100 ; and patterning the dummy gate material layer. The remaining dummy gate material layer is used as the dummy gate 120 .

In this embodiment, in the process of patterning the dummy gate material layer, the gate oxide layer 110 located at the bottom of the dummy gate material layer is also patterned as an example. Accordingly, after the dummy gate 120 is formed, the gate oxide layer 110 is only located at the bottom of the dummy gate 120. In other embodiments, in the process of patterning the dummy gate material layer, the gate oxide layer may not be patterned. Accordingly, after the dummy gate is formed, the dummy gate oxide layer is still located on the surface of the substrate.

In this embodiment, after forming the dummy gate 120 , the method for forming the semiconductor structure further includes: forming a spacer (not shown) on the sidewall of the dummy gate 120 .

The sidewall spacer is used to protect the sidewall of the dummy gate 120 , and the sidewall spacer is also used to define the formation position of the source and drain doping regions.

The material of the sidewalls may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride, and the sidewalls may be a single-layer structure or a stacked-layer structure.

In this embodiment, the side wall is a single-layer structure, and the material of the side wall is silicon nitride.

5 , source and drain doped regions (not shown) are formed in the substrate 100 on both sides of the dummy gate 120 .

The source-drain doping region is used to provide stress to the channel when the device is working, thereby improving the carrier mobility in the channel region.

In this embodiment, source and drain doping regions are formed by epitaxy and doping processes, and the material of the source and drain doping regions includes a stress layer doped with ions. When forming a PMOS transistor, the material of the stress layer is Si or SiGe, and the stress layer is used to provide compressive stress to the channel region of the PMOS transistor, and the doped ions in the stress layer are P-type ions, such as B ions, Ga ions, or In ions; when forming an NMOS transistor, the material of the stress layer is Si or SiC, and the stress layer is used to provide tensile stress to the channel region of the NMOS transistor, and the doped ions in the stress layer are N-type ions, such as P ions, As ions, or Sb ions.

In this embodiment, in the step of forming the source-drain doped regions, the source-drain doped regions are formed in the fins on both sides of the dummy gate 120 .

5 , an interlayer dielectric layer 130 is formed on both sides of the dummy gate 120 to cover the source and drain doping regions.

The interlayer dielectric layer 130 is used to isolate adjacent devices.

Therefore, the material of the interlayer dielectric layer 130 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride, and the interlayer dielectric layer 130 can be a single-layer structure or a stacked structure.

In this embodiment, the interlayer dielectric layer 130 is a single-layer structure, and the material of the interlayer dielectric layer 130 is silicon oxide.

It should be noted that, in this embodiment, after forming the source and drain doping regions and before forming the interlayer dielectric layer 130 , the method for forming the semiconductor structure further includes: forming an etching stop layer 140 conformally covering the surface of the source and drain doping regions and the sidewalls of the dummy gate 120 .

In this embodiment, the etch stop layer 140 is a contact hole etch stop layer (Contact Etch Stop Layer, CESL). In the subsequent process of etching the interlayer dielectric layer 130 to form a contact hole exposing the source and drain doped regions, the etch stop layer 140 is used to define the etching stop position of the contact hole etching process, thereby helping to reduce the damage of the contact hole etching process to the source and drain doped regions.

Correspondingly, in this embodiment, the interlayer dielectric layer 130 covers the etching stop layer 140 .

In this embodiment, the material of the etching stop layer 140 is silicon nitride.

The subsequent steps further include: performing surface treatment on the dummy gate 120 , which is suitable for reducing the surface contact angle of the dummy gate 120 .

It should be noted that, in this embodiment, before performing surface treatment on the dummy gate 120 , the method for forming the semiconductor structure includes: performing heat treatment to transform silicon of the first crystal orientation into silicon of the second crystal orientation.

In the present embodiment, the first crystal orientation is the <100> crystal orientation, and the heat treatment generally includes a high-temperature treatment process. Polycrystalline silicon is easily crystallized in a high-temperature environment, thereby causing the silicon in the <100> crystal orientation to be transformed into the silicon in the <111> crystal orientation. That is to say, the second crystal orientation is the <111> crystal orientation. The silicon in the <100> crystal orientation and the silicon in the <111> crystal orientation have different etching rates. Specifically, the silicon in the <111> crystal orientation is more difficult to remove. Therefore, in the subsequent process of removing the dummy gate 120, it is easy to cause the dummy gate 120 to be difficult to be completely removed, thereby easily increasing the probability of the dummy gate 120 remaining.

In this embodiment, the first crystal orientation is <100> and the second crystal orientation is <111> as an example. In other embodiments, the first crystal orientation and the second crystal orientation may be other crystal orientations according to actual process conditions, materials of dummy gates and other factors.

Specifically, in this embodiment, the heat treatment includes:

Adopting epitaxial process to form the source-drain doped region;

Alternatively, after forming the source/drain doped regions and before forming the interlayer dielectric layer 130, the source/drain doped regions are annealed;

Alternatively, along the extension direction of the dummy gate 120, the dummy gate 120 includes a cut-off area (not shown); after forming the interlayer dielectric layer 130 and before performing surface treatment on the dummy gate 120, the dummy gate 120 located in the cut-off area is removed, and an isolation opening (not shown) is formed in the dummy gate 120; and an isolation structure is formed in the isolation opening.

Among them, the temperature of the epitaxial process is 700℃ to 900℃, for example, the temperature of the epitaxial process is 800℃; the process temperature of the annealing treatment is 800℃ to 1100℃, for example, the process temperature of the annealing treatment is 900℃; the process of forming the isolation structure includes a deposition process, the process temperature of the deposition process is 500℃ to 700℃, for example, the temperature of the deposition process is 600℃, and the process time of the deposition process is relatively long, for example, the process time of the deposition process is 10 hours.

The process temperatures of the epitaxial process, the annealing process and the deposition process are all relatively high, so that after the heat treatment, the silicon in the first crystal orientation is easily crystallized and transformed into silicon in the second crystal orientation.

6 , in this embodiment, the method for forming the semiconductor structure further includes: after forming the interlayer dielectric layer 130 and before performing surface treatment on the dummy gate 120 , removing a portion of the thickness of the dummy gate 120 , and the remaining top surface of the dummy gate 120 is higher than the top surface of the substrate 100 .

By removing a portion of the thickness of the dummy gate 120, the thickness of the remaining dummy gate 120 is reduced. In the subsequent process of removing the remaining dummy gate 120 by a wet etching process, the thickness of the dummy gate 120 that needs to be etched by the wet etching process is smaller, and the remaining dummy gate 120 is less difficult to remove. Therefore, after the dummy gate 120 is subsequently surface treated, the remaining dummy gate 120 is easy to be completely removed.

In the present embodiment, the base 100 includes a substrate and a fin protruding from the substrate. After removing a portion of the thickness of the dummy gate 120, the remaining top surface of the dummy gate 120 is higher than the top surface of the fin, thereby reducing the damage to the fin caused by removing a portion of the thickness of the dummy gate 120, which is beneficial to improving process compatibility. Moreover, the dummy gate 120 spans the fin and covers a portion of the top and a portion of the side wall of the fin. Compared with the dummy gate 120 located at the top of the fin, the dummy gate 120 located at the side wall of the fin is more difficult to be completely removed. By removing the portion of the thickness of the dummy gate 120 that is higher than the fin, it is easy to subsequently remove the dummy gate 120 located at the side wall of the fin.

In this embodiment, in the step of removing a portion of the dummy gate 120 , the top surface of the remaining dummy gate 120 is higher than the top surface of the fin, thereby preventing the fin from being damaged by removing a portion of the dummy gate 120 .

It should be noted that, in the step of removing a portion of the thickness of the dummy gate 120, the distance from the remaining top surface of the dummy gate 120 to the top surface of the fin should not be too small, otherwise the process of removing a portion of the thickness of the dummy gate 120 is likely to cause damage to the gate oxide layer 110 or the fin, which is likely to cause damage to the gate oxide layer 110, and is also likely to reduce the protective effect of the gate oxide layer 110 on the substrate 100, especially the protective effect of the gate oxide layer 110 on the fin. For this reason, in the step of removing a portion of the thickness of the dummy gate 120 in this embodiment, the distance from the remaining top surface of the dummy gate 120 to the top surface of the fin is at least 200 angstroms.

In this embodiment, a dry etching process, for example, an anisotropic dry etching process, is used to remove a portion of the thickness of the dummy gate 120. By using the dry etching process, it is easy to achieve anisotropic etching, which is conducive to accurately controlling the etching thickness of the dummy gate 120. Moreover, by selecting the dry etching process, it is also conducive to achieving a higher etching selectivity, thereby reducing the risk of damaging other film layer structures in the process of removing a portion of the thickness of the dummy gate 120.

7 , after the interlayer dielectric layer 130 is formed, the dummy gate 120 is subjected to surface treatment, which is suitable for reducing the surface contact angle of the dummy gate 120 .

After forming the interlayer dielectric layer 130, the embodiment of the present invention further performs surface treatment on the dummy gate 120, which is suitable for reducing the surface contact angle of the dummy gate 120. By reducing the surface contact angle of the dummy gate 120, it is beneficial to improve the hydrophilicity of the dummy gate 120, so that in the subsequent process of removing the dummy gate 120 by a wet etching process, it is beneficial to increase the contact area between the etching solution and the dummy gate 120, and improve the etching rate of the dummy gate 120 by the etching solution, so that the dummy gate 120 is easier to be removed by the etching solution, which is beneficial to enable the wet etching process to completely remove the dummy gate 120 and reduce the probability of generating residues of the dummy gate 120, and it is beneficial to provide a good interface for the subsequent formation of a gate structure, which is correspondingly beneficial to improving the performance and production yield of the semiconductor structure.

Among them, in this embodiment, the surface contact angle refers to the contact angle of the liquid on the surface of the solid material. When the liquid is dropped on the solid surface, the angle between the tangent line of the droplet at the contact edge of the solid and the liquid and the solid plane is the surface contact angle. The minimum contact angle is 0° and the maximum is 180°. The smaller the contact angle, the better the wettability of the solid, and the better the hydrophilicity of the solid surface.

In this embodiment, by reducing the surface contact angle of the dummy gate 120, the surface of the dummy gate 120 is more easily wetted by the liquid, thereby correspondingly improving the surface hydrophilicity of the dummy gate 120, which is beneficial to increasing the contact area between the etching solution and the dummy gate 120 in the subsequent wet etching process, making the dummy gate 120 easier to be removed by the etching solution.

Specifically, in this embodiment, the surface treatment is performed on the dummy gate 120, which is suitable for reducing the etching selectivity ratio of the wet etching process to the silicon of the first crystal orientation and the silicon of the second crystal orientation. By reducing the etching selectivity ratio of the wet etching process to the silicon of the first crystal orientation and the silicon of the second crystal orientation, the difference in etching rate of the wet etching process to the silicon of the first crystal orientation and the silicon of the second crystal orientation is reduced, which is conducive to improving the uniformity of the etching rate of the subsequent wet etching process to the silicon of the first crystal orientation and the silicon of the second crystal orientation, and further conducive to reducing the probability of residual materials of the dummy gate 120 with different crystal orientations when the dummy gate 120 is removed by the wet etching process in the future.

In this embodiment, surface treatment is performed on the dummy gate 120 , which is beneficial to improving the etching rate of silicon in the <111> crystal orientation in the subsequent wet etching process, thereby reducing the probability of residual silicon in the <111> crystal orientation.

In this embodiment, the step of performing surface treatment on the dummy gate 120 includes: performing surface treatment on the dummy gate 120 using an NH ₄ OH solution having a temperature higher than room temperature.

By using an NH ₄ OH solution at a temperature higher than room temperature, the solution temperature of the NH ₄ OH solution is higher, which is beneficial to improving the effect of the surface treatment for reducing the surface contact angle of the dummy gate 120. Moreover, the NH ₄ OH solution at a temperature higher than room temperature can also etch away a portion of silicon in the <111> crystal orientation, thereby facilitating the subsequent wet etching process to etch the silicon in the <111> crystal orientation. Correspondingly, it is beneficial to further reduce the probability of generating residual dummy gates 120.

In this embodiment, the NH ₄ OH solution can also remove the natural oxide layer generated on the surface of the dummy gate 120 , thereby facilitating preparation for the subsequent removal of the remaining dummy gate 120 using a wet etching process.

In this embodiment, in order to ensure that the surface treatment has a more significant effect on reducing the surface contact angle of the dummy gate 120 , the temperature of the NH ₄ OH solution is at least 50° C.

However, the temperature of the NH ₄ OH solution should not be too high, otherwise it will easily cause the subsequent wet etching process to etch the dummy gate 120 too fast, thereby easily reducing process stability. Therefore, in this embodiment, the temperature of the NH ₄ OH solution is 50°C to 70°C.

In this embodiment, parameters for surface treatment of the dummy gate 120 include: a volume ratio of NH ₄ OH to water in the NH ₄ OH solution of 1:40 to 1:4, and a treatment time of 20 seconds to 60 seconds.

The volume ratio of NH ₄ OH to water in the NH ₄ OH solution should not be too small or too large. If the volume ratio of NH ₄ OH to water is too small, it is easy to cause the surface treatment rate to be too slow, or it is easy to cause the surface treatment to reduce the surface contact angle of the dummy gate 120. The effect is not obvious; if the volume ratio of NH ₄ OH to water is too large, it is easy to reduce the uniformity and stability of the surface treatment. For this reason, in this embodiment, the volume ratio of NH ₄ OH to water in the NH ₄ OH solution is 1:40 to 1:4.

The processing time of the surface treatment should not be too short or too long. If the processing time of the surface treatment is too short, the effect of the surface treatment is not obvious, and the effect of the surface treatment for reducing the surface contact angle of the pseudo gate 120 is not obvious; if the processing time of the surface treatment is too long, it is easy to reduce the process stability, produce side effects, and also easy to waste production capacity. For this reason, in this embodiment, the processing time of the surface treatment is 20 seconds to 60 seconds.

8 , after the dummy gate 120 is surface treated, the dummy gate 120 is removed by a wet etching process, and a gate opening 10 is formed in the interlayer dielectric layer 130 .

The gate opening 10 is used to provide a space for subsequently forming a gate structure.

Moreover, in this embodiment, the bottom of the gate opening 10 exposes the gate oxide layer 110 , and the gate opening 10 is also used to prepare for the subsequent removal of the gate oxide layer 110 in the core region I.

The embodiment of the present invention reduces the surface contact angle of the dummy gate 120 by performing surface treatment on the dummy gate 120, which is beneficial to improving the hydrophilicity of the dummy gate 120. Therefore, in the process of removing the dummy gate 120 by a wet etching process, it is beneficial to increase the contact area between the etching solution and the dummy gate 120, so that the dummy gate 120 is easier to be removed by the etching solution, which is beneficial to the wet etching process to cleanly remove the dummy gate 120 and reduce the probability of generating residual dummy gate 120, which is beneficial to provide a good interface for the subsequent formation of a gate structure, and correspondingly beneficial to improving the performance and production yield of the semiconductor structure.

Specifically, the surface treatment is suitable for reducing the difference in etching rate between the silicon in the first crystal orientation and the silicon in the second crystal orientation by the wet etching process. Therefore, in the present embodiment, in the process of removing the pseudo gate 120 by the wet etching process, the difference in etching rate between the silicon in the first crystal orientation and the silicon in the second crystal orientation is small, and the etching rate uniformity of the silicon in the first crystal orientation and the silicon in the second crystal orientation by the wet etching process is high.

In this embodiment, the wet etching process has an etching selectivity ratio of 1.8:1 to 3.7:1 for silicon in the first crystal orientation and silicon in the second crystal orientation, and the wet etching process has an etching selectivity ratio of 1.8:1 to 3.7:1 for silicon in the first crystal orientation and silicon in the second crystal orientation, and the wet etching process has an etching selectivity ratio of 1 to silicon in the first crystal orientation and silicon in the second crystal orientation, thereby ensuring that the wet etching process has a high uniformity in etching rate for silicon in the first crystal orientation and silicon in the second crystal orientation. Specifically, in this embodiment, the surface treatment is conducive to improving the etching rate of the wet etching process for silicon in the second crystal orientation.

In this embodiment, the first crystal orientation is the <100> crystal orientation, and the second crystal orientation is the <111> crystal orientation. The wet etching process has a higher etching rate for silicon in the <111> crystal orientation, which is beneficial to reducing the etching selectivity ratio between silicon in the <100> crystal orientation and silicon in the <111> crystal orientation.

In this embodiment, the etching solution of the wet etching process includes a tetramethylammonium hydroxide (TMAH) solution.

In this embodiment, the etching time of the wet etching process is 120 seconds to 360 seconds, so that the etching time of the wet etching process is neither too long nor too short, thereby ensuring that the wet etching process can remove the pseudo gate 120 cleanly while preventing waste of production capacity and reducing damage to other film layers.

9 and 10 , a gate structure 150 is formed in the gate opening 10 (as shown in FIG. 10 ).

The gate structure 150 is used to control the opening and closing of the conductive channel.

In this embodiment, the gate structure 150 is a metal gate structure, and the steps of forming the gate structure 150 include: forming a high-k gate dielectric layer (not shown) at the bottom and sidewalls of the gate opening 10; and forming a gate electrode layer (not shown) filling the gate opening 10 on the high-k gate dielectric layer.

The material of the high-k gate dielectric layer is a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material having a relative dielectric constant greater than that of silicon oxide, and the high-k gate dielectric material may be HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ . In this embodiment, the material of the high-k gate dielectric layer is HfO ₂ .

The material of the gate electrode layer is a conductive material such as Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the gate electrode layer is W.

In this embodiment, the substrate 100 includes a core region I for forming a core device and a peripheral region II for forming an input/output device. The operating voltage of the input/output device is usually much greater than the operating voltage of the core device. To ensure the performance of the input/output device (for example, to prevent breakdown and other problems), the thickness of the gate dielectric layer of the input/output device is usually greater than the thickness of the gate dielectric layer of the core device.

To this end, as shown in FIG. 9 , in this embodiment, after forming the gate opening 10 and before forming the gate structure 150 , the method for forming the semiconductor structure further includes: removing the gate oxide layer 110 at the bottom of the gate opening 10 of the core region I.

By removing the gate oxide layer 110 of the core area I, the gate dielectric layer of the core device only includes the high-k gate dielectric layer, and the gate dielectric layer of the input/output device includes the gate oxide layer 110 and the high-k gate dielectric layer located on the gate oxide layer 110, thereby making the thickness of the gate dielectric layer of the core area I greater than the thickness of the gate dielectric layer of the peripheral area II.

As an example, in this embodiment, a wet etching process is used to remove the gate oxide layer 110 at the bottom of the gate opening 10 of the core region I. Specifically, the etching solution of the wet etching process can be a diluted hydrofluoric acid solution.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate;

Forming a dummy gate on the substrate, wherein the material of the dummy gate layer comprises silicon with a first crystal orientation;

forming source-drain doped regions in the substrate at two sides of the pseudo gate;

Forming an interlayer dielectric layer covering the source-drain doped region on two sides of the pseudo gate;

after the interlayer dielectric layer is formed and before the surface treatment of the dummy gate, removing part of the thickness of the dummy gate, wherein the top surface of the rest dummy gate is higher than the top surface of the substrate;

Before the surface treatment of the dummy gate, performing heat treatment to convert the silicon with the first crystal orientation into silicon with a second crystal orientation; after the interlayer dielectric layer is formed, carrying out surface treatment on the dummy gate, wherein the surface treatment is suitable for reducing the surface contact angle of the dummy gate; performing surface treatment on the dummy gate, which is suitable for reducing the etching rate difference of the wet etching process on the silicon in the first crystal orientation and the silicon in the second crystal orientation;

After the surface treatment is carried out on the pseudo gate, removing the pseudo gate by adopting a wet etching process, and forming a gate opening in the interlayer dielectric layer;

A gate structure is formed in the gate opening.

2. The method of forming a semiconductor structure of claim 1, wherein a dry etching process is used to remove a portion of the thickness of the dummy gate.

3. The method of forming a semiconductor structure of claim 1, wherein the base comprises a substrate and a fin protruding from the substrate;

In the step of forming the dummy gate, the dummy gate spans across the fin portion and covers part of the top and part of the side wall of the fin portion;

and in the step of removing part of the dummy gate with the thickness, the top surface of the rest dummy gate is higher than the top surface of the fin part.

4. The method of claim 3, wherein in removing a portion of the dummy gate thickness, a distance from a top surface of the dummy gate to a top surface of the fin is at least 200 a.

5. The method of forming a semiconductor structure of claim 1, wherein the step of surface treating the dummy gate comprises: and adopting NH ₄ OH solution higher than room temperature to carry out surface treatment on the pseudo gate.

6. The method of forming a semiconductor structure of claim 5, wherein the NH ₄ OH solution has a temperature of at least 50 ℃.

7. The method of claim 5, wherein the NH ₄ OH solution is at a temperature of 50 ℃ to 70 ℃.

8. The method of forming a semiconductor structure of claim 5, wherein the parameters for surface treating the dummy gate include: the ratio of NH ₄ OH to water in the NH ₄ OH solution is 1:40 to 1:4, the treatment time is 20 seconds to 60 seconds.

9. The method of forming a semiconductor structure of claim 1, wherein the etching solution of the wet etching process comprises a tetramethylammonium hydroxide solution.

10. The method of claim 1, wherein the wet etching process has an etching time of 120 seconds to 360 seconds.

11. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the dummy gate, the dummy gate comprises a dummy gate layer, and a material of the dummy gate layer comprises polysilicon.

12. The method of claim 11, wherein the first crystal orientation is a <100> crystal orientation and the second crystal orientation is a <111> crystal orientation.

13. The method of claim 11, wherein the wet etching process has an etch selectivity to silicon of the first crystal orientation and silicon of the second crystal orientation of 1.8:1 to 3.7:1.

14. The method of forming a semiconductor structure of claim 11, wherein the heat treatment comprises:

forming the source-drain doped region by adopting an epitaxial process;

Or annealing the source-drain doped region before forming the interlayer dielectric layer after forming the source-drain doped region;

Or along the extending direction of the dummy gate, the dummy gate comprises a cutting-off region; removing the dummy gate in the cutting area after forming the interlayer dielectric layer and before carrying out surface treatment on the dummy gate, and forming an isolation opening surrounded by the rest of the dummy gate and the interlayer dielectric layer; an isolation structure is formed in the isolation opening.

15. The method of forming a semiconductor structure of claim 14, wherein the process of forming the isolation structure comprises a deposition process having a process temperature of 500 ℃ to 700 ℃.

16. The method of forming a semiconductor structure of claim 14, wherein the temperature of the epitaxial process is 700 ℃ to 900 ℃.

17. The method of forming a semiconductor structure of claim 14, wherein the annealing process is performed at a process temperature of 800 ℃ to 1100 ℃.

18. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a base, the base comprises a substrate and a fin protruding from the substrate;

In the step of forming the dummy gate, the dummy gate spans across the fin portion and covers part of the top and part of the side wall of the fin portion;

In the step of forming the source-drain doped region, the source-drain doped region is formed in the fin portions at two sides of the dummy gate.