CN109003976B

CN109003976B - Semiconductor structure and method of forming the same

Info

Publication number: CN109003976B
Application number: CN201710418208.9A
Authority: CN
Inventors: 李勇
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-06-06
Filing date: 2017-06-06
Publication date: 2021-05-04
Anticipated expiration: 2037-06-06
Also published as: CN109003976A

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate and a discrete fin part on the substrate; forming an isolation structure on the substrate, wherein the top of the isolation structure is lower than the top of the fin part; forming a pseudo gate structure crossing the fin part, wherein the pseudo gate structure covers partial side wall and top surface of the fin part, the pseudo gate structure comprises a gate oxide layer and a gate layer positioned on the gate oxide layer, and the gate layer also covers part of the isolation structure; removing the gate layer to expose the isolation structure; forming a protective layer on the isolation structure after removing the gate layer; removing the gate oxide layer after forming the protective layer; and after removing the gate oxide layer, forming a high-k gate dielectric layer crossing the fin part, wherein the high-k gate dielectric layer covers part of the side wall and the top of the fin part. In the process of removing the gate oxide layer, the protective layer plays a role in protecting the isolation structure, so that the isolation structure is prevented from being etched and lost, and the deterioration of a short channel effect is avoided.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.

Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processes are gradually starting to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.

However, the electrical performance and yield of the semiconductor devices formed by the prior art are still to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can improve the electrical performance and yield of semiconductor devices.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and discrete fin parts positioned on the substrate; forming an isolation structure on the substrate, wherein the top of the isolation structure is lower than the top of the fin part; forming a pseudo gate structure crossing the fin part, wherein the pseudo gate structure covers partial side wall and top surface of the fin part, the pseudo gate structure comprises a gate oxide layer and a gate layer positioned on the gate oxide layer, and the gate layer also covers part of the isolation structure; removing the gate layer to expose the isolation structure; after removing the gate layer, forming a protective layer on the isolation structure; after the protective layer is formed, removing the gate oxide layer; and after removing the gate oxide layer, forming a high-k gate dielectric layer crossing the fin part, wherein the high-k gate dielectric layer covers part of the side wall and the top of the fin part.

Accordingly, the present invention also provides a semiconductor structure comprising: a substrate; a fin portion on the substrate; the isolation structure is positioned on the substrate, and the top of the isolation structure is lower than the top of the fin part; a protective layer on the isolation structure; and the high-k gate dielectric layer stretches across the fin part and covers part of the side wall and the top of the fin part.

Compared with the prior art, the technical scheme of the invention has the following advantages:

after the grid layer is removed, a protective layer is formed on the isolation structure, so that in the subsequent process of removing the gate oxide layer, the protective layer plays a role in protecting the isolation structure, the isolation structure is prevented from being etched and lost, the problem that part of the fin part in the isolation structure is exposed is prevented, the problem that the fin part and the corner at the top of the isolation structure generate feet (Footing) can be prevented, the deterioration of a short channel effect is avoided, and the electrical performance and the yield of a semiconductor device are improved.

In an alternative, the protective layer is further located on the surface of the gate oxide layer on the top of the fin, and the remaining gate oxide layer and the protective layer on the top of the fin may be used as a part of a gate Dielectric layer of the formed semiconductor structure, that is, the thickness of the gate Dielectric layer at the corner of the top of the fin is increased, so as to be beneficial to improving the reliability performance of the semiconductor device, such as Time Dependent Dielectric Breakdown (TDDB).

Drawings

Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

fig. 5 to 38 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, the electrical performance and yield of semiconductor devices are still to be improved.

Referring to fig. 1 to 4 in combination, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown. The electrical performance and yield of the conventional semiconductor structure formation method are still to be analyzed.

Referring to fig. 1 and 2 in combination, fig. 1 is a perspective view (only two fins are shown), fig. 2 is a schematic cross-sectional view of fig. 1 along a cut line perpendicular to the extending direction of the fins (as shown by a1a2 cut line in fig. 1) at the position of a pseudo gate structure, and a substrate 10 and a discrete fin 11 located on the substrate 10 are provided; forming an isolation structure 12 on the substrate 10, wherein the top of the isolation structure 12 is lower than the top of the fin portion 11; and forming a dummy gate structure (not marked) crossing the fin part 11, wherein the dummy gate structure covers partial side wall and top surface of the fin part 11 and also covers part of the isolation structure 12, and comprises a gate oxide layer 13 positioned on partial surface of the fin part 11 and a gate layer 14 positioned on the gate oxide layer 13.

Referring to fig. 3, fig. 3 is a perspective view based on fig. 1, an interlayer dielectric layer 15 is formed on the isolation structure 12 exposed by the dummy gate structure (not labeled), and the interlayer dielectric layer 15 is exposed from the top of the dummy gate structure.

Referring to fig. 4, fig. 4 is a schematic cross-sectional view of fig. 3 taken along a line perpendicular to the extending direction of the fin at the position of the dummy gate structure (as shown by the line b1b2 in fig. 3), sequentially removing the gate layer 14 and the gate oxide layer 13, and forming an opening (not shown) in the interlayer dielectric layer 15 (shown in fig. 3) to expose a portion of the fin 11 and the isolation structure 12.

After the gate layer 14 is removed, the isolation structure 12 in the opening is exposed to a process environment for subsequently removing the gate oxide layer 13, in semiconductor manufacturing, generally, the materials of the gate oxide layer 13 and the isolation structure 12 are both silicon oxide, so during a process for removing the gate oxide layer 13, the isolation structure 12 is prone to have an etching Loss (i.e., STI Loss), which results in a reduction in the thickness of the isolation structure 12, and at corners of the fin portion 11 and the top of the isolation structure 12 (as shown by a dotted circle in fig. 4), the isolation structure 12 is prone to have a foot portion, that is, in a direction toward the sidewall of the fin portion 11, the thickness of the isolation structure 12 is gradually increased, and the top of the isolation structure 12 between adjacent fin portions 11 has a concave surface, which results in a deterioration of a short channel effect.

Moreover, when the sidewalls of the fin 11 are not perpendicular to the substrate 10, i.e., when the top dimension of the fin 11 is smaller than the bottom dimension, the loss of the isolation structure 12 results in an increase in the bottom dimension of the fin 11 exposed to the isolation structure 12.

For example, the dimension of the bottom of the fin 11 exposed out of the isolation structure 12 is L1 (as shown in fig. 2) before the dummy gate structure is removed, the dimension of the bottom of the fin 11 exposed out of the isolation structure 12 after the gate oxide layer 13 is removed is L2 (as shown in fig. 4), and when the sidewall of the fin 11 is not perpendicular to the substrate 10, L2 is greater than L1, so that the short channel effect is aggravated; and the larger the thickness of the gate oxide layer 13 is, the more serious the loss of the isolation structure 12 is, and correspondingly, the more serious the short channel effect is, the worse the electrical performance and yield of the formed semiconductor device is.

In order to solve the technical problem, after the gate electrode layer is removed, a protective layer is formed on the exposed isolation structure, and the protective layer plays a role in protecting the isolation structure in the process of removing the gate oxide layer, so that the isolation structure is prevented from being etched and lost, and the deterioration of a short channel effect is avoided.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 5, fig. 5 is a perspective view (only two fins are shown) providing a substrate 100 and discrete fins 110 on the substrate 100.

The substrate 100 provides a process operation basis for subsequent fin field effect transistor formation, and the fin 110 is used for providing a channel of the formed fin field effect transistor.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 100 may be selected to be suitable for process requirements or easy integration.

The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

The sidewalls of the fins 110 may not be perpendicular to the surface of the substrate 100, that is, the top dimension of the fins 110 is smaller than the bottom dimension, and the sidewalls of the fins 110 may also be perpendicular to the surface of the substrate 100, that is, the top dimension of the fins 110 is equal to the bottom dimension.

In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 100 includes a PMOS region i and an NMOS region ii, and the PMOS region i and the NMOS region ii are Core regions for forming a Core (Core) device. In other embodiments, the substrate may include only NMOS regions or only PMOS regions.

It should be noted that, in the present embodiment, the substrate 100 may further include a peripheral region (not shown) for forming a peripheral (I/O) device (or referred to as an input/output device).

With continued reference to fig. 5, an Isolation Structure (STI) 101 is formed on the substrate 100, wherein a top of the Isolation structure 101 is lower than a top of the fin 110.

The isolation structure 101 is used for isolating adjacent semiconductor devices and also used for isolating adjacent fins 110.

In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

Referring to fig. 6 to 10 in combination, fig. 6 is a perspective view based on fig. 5, fig. 7 is a schematic cross-sectional structure of fig. 6 along a cut line perpendicular to a fin extending direction at a position of one side of the Dummy Gate structure (as indicated by a cut line B1B2 in fig. 6), fig. 8 is a schematic cross-sectional structure of fig. 6 along a cut line in a fin extending direction at a position of the fin in the PMOS region (as indicated by a cut line C1C2 in fig. 6), fig. 9 is a schematic cross-sectional structure based on fig. 7, and fig. 10 is a schematic cross-sectional structure based on fig. 8, a Dummy Gate structure (Dummy Gate) (not labeled) is formed across the fin 110, the Dummy Gate structure covers a portion of the sidewall and the top surface of the fin 110, the Dummy Gate structure includes a Gate oxide layer 121 (as indicated in fig. 10) and a Gate layer 122 (as indicated in fig. 10) on the Gate oxide layer 121, and the Gate layer 122 covers a portion of the.

In this embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate last), and the dummy gate structure occupies a space for forming the metal gate structure subsequently.

The gate oxide layer 121 is made of silicon oxide or silicon oxynitride, and the gate layer 122 is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. In this embodiment, the gate oxide layer 121 is made of silicon oxide, and the gate layer 122 is made of polysilicon.

Specifically, with reference to fig. 6 to 8, a dummy gate oxide film 120 is formed on the surface of the fin 110 (as shown in fig. 6); forming a dummy gate film on the dummy gate oxide film 120, wherein the dummy gate film also covers the isolation structure 101; forming a gate mask layer 210 (as shown in fig. 6) on the surface of the dummy gate film, where the gate mask layer 210 defines a pattern of the gate layer 122 to be formed; and patterning the pseudo gate film by taking the gate mask layer 210 as a mask, forming a gate layer 122 on a part of the isolation structure 101, wherein the gate layer 122 spans the fin portion 110 and covers a part of the pseudo gate oxide film 120 on the top and the side wall of the fin portion 110.

In this embodiment, the process of forming the gate oxide layer 121 is a thermal oxidation process. Specifically, the gate oxide layer 121 is formed by an In-situ steam Generation oxidation (ISSG) process, i.e., the process of forming the dummy gate oxide film 120 is an In-situ steam Generation oxidation process.

The reaction gas of the in-situ steam generation oxidation process reacts only with silicon, and thus the dummy gate oxide film 120 is formed only on the surface of the fin 110.

Therefore, referring to fig. 9 and 10 in combination, after the gate layer 122 is formed, the gate mask layer 210 is used as a mask to remove the dummy gate oxide film 120 exposed to the gate layer 122 (as shown in fig. 6), the dummy gate oxide film 120 covered by the gate layer 122 is remained, and the remaining dummy gate oxide film 120 is used as the gate oxide layer 121 (as shown in fig. 10).

Correspondingly, after the dummy gate oxide film 120 exposed out of the gate layer 122 is removed, the surfaces of the fins 110 on both sides of the gate layer 122 are exposed.

In this embodiment, the dummy gate oxide film 120 exposed out of the gate layer 122 is removed by a dry etching process, which is a SiCoNi etching process.

The etching rate of the SiCoNi etching process to the pseudo gate oxide film 120 is greater than that to the fin portion 110, so that the loss to the fin portion 110 can be reduced while removing the pseudo gate oxide film 120 exposed out of the gate layer 122; and the SiCoNi etching process is beneficial to improving the Loading Effect (Loading Effect) of the etching process on a pattern Dense Area (Dense Area) and a pattern sparse Area (Iso Area), thereby improving the uniformity of the removal rate of the dummy gate oxide film 120 in each Area.

In another embodiment, a wet etching process may be further used to remove the dummy gate oxide film exposed out of the gate layer. The material of the pseudo gate oxide film is silicon oxide, and correspondingly, the etching solution adopted by the wet etching process is diluted hydrofluoric acid.

Note that after the dummy gate structure is formed, the gate mask layer 210 on the top of the gate layer 122 is remained. The gate mask layer 210 is made of silicon nitride, and the gate mask layer 210 is used for protecting the top of the gate layer 122 in a subsequent process.

It should be noted that, since the forming processes of the dummy gate structures of the PMOS region i and the NMOS region ii are the same, fig. 8 and fig. 10 are only described by taking the PMOS region i as an example, and a schematic structural diagram of the NMOS region ii is not shown.

In addition, when the substrate 100 further includes a peripheral region (not shown), the dummy gate structure is also formed in the peripheral region.

With reference to fig. 11 and 12, fig. 11 is a schematic cross-sectional structure diagram based on fig. 9, and fig. 12 is a schematic cross-sectional structure diagram based on fig. 10, and after the pseudo gate structure (not shown) is formed, the method further includes the steps of: and forming side walls 300 on the side walls and the top of the pseudo gate structure.

The sidewall spacers 300 are used to define the position of the doped epitaxial layer in the subsequent process.

The material of the sidewall 300 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 may be a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 300 has a single-layer structure, and the material of the sidewall spacer 300 is silicon nitride.

In this embodiment, the process for forming the sidewall 300 is an atomic layer deposition process, and correspondingly, the sidewall 300 is further formed on the sidewall and the top of the fin 110 and on the isolation structure 101.

A gate mask layer 210 is formed on the top of the gate layer 122, so that the sidewall spacers 300 are located on the sidewalls of the dummy gate structure and the surface of the gate mask layer 210.

After the side wall 300 is formed, the method further includes the steps of: and forming a source/drain lightly doped region (LDD) (not shown) in the fin 110 at two sides of the dummy gate structure by using the sidewall spacers 300 as masks.

In this embodiment, the substrate 100 includes a PMOS region i and an NMOS region ii, so that the doped ions of the source-drain lightly doped region of the PMOS region i are P-type ions, and the doped ions of the source-drain lightly doped region of the NMOS region ii are N-type ions.

With reference to fig. 13 to fig. 20, fig. 13 is a schematic cross-sectional structure based on fig. 11, fig. 14 is a schematic cross-sectional structure based on fig. 12, fig. 15 is a schematic cross-sectional structure based on fig. 13, fig. 16 is a schematic cross-sectional structure based on fig. 14, fig. 17 is a schematic cross-sectional structure based on fig. 15, fig. 18 is a schematic cross-sectional structure based on fig. 17, which is a cut line (indicated by a cut line D1D2 in fig. 6) along a fin extending direction at a position of a fin in an NMOS region, fig. 19 is a schematic cross-sectional structure based on fig. 17, fig. 20 is a schematic cross-sectional structure based on fig. 18, and it should be noted that after forming the source and drain lightly doped regions (not shown), the method further: a doped epitaxial layer (not shown) is formed in the fin 110 on both sides of the dummy gate structure (not shown).

The doped epitaxial layer is used as a Source region (Source) or a Drain region (Drain) of the formed semiconductor device.

Specifically, the doped epitaxial layer of the PMOS region i is a first doped epitaxial layer 115 (as shown in fig. 15), the first doped epitaxial layer 115 is P-type doped Si or SiGe, the doped epitaxial layer of the NMOS region ii is a second doped epitaxial layer 125 (as shown in fig. 19), and the second doped epitaxial layer 125 is N-type doped Si or SiC.

The steps for forming the first doped epitaxial layer 115 and the second doped epitaxial layer 125 are described in detail below with reference to the accompanying drawings.

In this embodiment, a process sequence of forming the first doped epitaxial layer 115 first and then forming the second doped epitaxial layer 125 is taken as an example for explanation.

With reference to fig. 13 and fig. 14, a first mask layer 310 is formed on the sidewall 300 of the PMOS region I; etching the first mask layer 310 and the side walls 300 on the partial tops of the fins 110 on two sides of the pseudo-gate structure (not labeled) of the PMOS region I to expose partial top surfaces of the fins 110 on two sides of the pseudo-gate structure of the PMOS region I; after the top of the fin 110 is exposed, the fin 110 in the PMOS region I with a partial thickness is continuously etched, and a P-region groove 111 is formed in the etched fin 110 (as shown in fig. 14).

In the process of etching the first mask layer 310 and the sidewall 300 on the top of the fin 110, the first mask layer 310 and the sidewall 300 on the top of the PMOS region I pseudo-gate structure and the isolation structure 101 are also etched.

The process of forming the first mask layer 310 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the first mask layer 310 is formed by an atomic layer deposition process. Therefore, the first mask layer 310 is also located on the sidewall spacers 300 of the NMOS region ii.

The first mask layer 310 is used as an etching mask for forming the P-region groove 111, so that a certain distance is reserved between the P-region groove 111 and the formed source-drain lightly doped region of the PMOS region I, the source-drain lightly doped region of the PMOS region I is prevented from being completely etched and removed, and the subsequent epitaxial growth process on the side walls of the fin portion 110 of the PMOS region I and the NMOS region II is also prevented; in addition, the first mask layer 310 in the NMOS region II will be used as a part of the mask layer in the NMOS region II.

The material of the first mask layer 310 may be silicon nitride, silicon oxide, boron nitride, or silicon oxynitride. The material of the first mask layer 310 is different from that of the fin 110, and the material of the first mask layer 310 is different from that of the isolation structure 101. In this embodiment, the first mask layer 310 is made of silicon nitride.

The material of the first mask layer 310 is the same as that of the sidewall 300, thereby being beneficial to reducing the process difficulty of the etching process.

It should be noted that before etching the first mask layer 310 on the tops of the fins 110 on both sides of the pseudo gate structure in the PMOS region I, a first pattern layer (not shown) is further formed on the first mask layer 310 in the NMOS region II. The first graphic layer plays a role in protecting the first mask layer 310 in the NMOS region II, and the first graphic layer also covers an area which is not desired to be etched in the PMOS region I.

It should be further noted that, as shown in fig. 13, in order to increase the volume of the first doped epitaxial layer 115 (shown in fig. 15) formed in the P-region groove 111 subsequently, the first mask layer 310 and the sidewall 300 on the sidewall of the fin 110 are etched while the PMOS region I-fin 110 is etched, so that after the P-region groove 111 is formed, the tops of the first mask layer 310 and the sidewall 300 on the sidewall of the PMOS region I-fin 110 are flush with the top of the fin 110.

Referring to fig. 15 and 16 in combination, a first doped epitaxial layer 115 is formed within the P region recess 111 (shown in fig. 14).

In this embodiment, a selective Epitaxy (EPI) process is adopted, a stress layer is formed in the P-region groove 111, and in the process of forming the stress layer, P-type ions are in-situ self-doped to form the first doped epitaxial layer 115. The top of the first doped epitaxial layer 115 is higher than the top of the P region groove 111.

The stress layer provides a pressure stress effect for the channel region of the device corresponding to the PMOS region I, so that the carrier mobility of the device in the PMOS region I is improved.

In other embodiments, after a stress layer is formed in the P-region groove, P-type ion doping is performed on the stress layer to form a first doped epitaxial layer.

With reference to fig. 17 and fig. 18, a second mask layer 320 is formed on the first mask layer 310 in the NMOS region ii; etching the second mask layer 320, the first mask layer 310 and the side walls 300 which are positioned on the partial tops of the fins 110 on two sides of the NMOS region II pseudo-gate structure (not marked), and exposing partial top surfaces of the fins 110 on two sides of the NMOS region II pseudo-gate structure; after the top of the fin 110 is exposed, the fin 110 in the NMOS region ii with a partial thickness is continuously etched, and an N-region recess 121 is formed in the etched fin 110 (as shown in fig. 18).

In the process of etching the second mask layer 320, the first mask layer 300 and the sidewall spacers 300 on the top of the fin 110, the second mask layer 320, the first mask layer 300 and the sidewall spacers 300 on the top of the NMOS region ii pseudo gate structure and the isolation structure 101 are also etched.

The process of forming the second mask layer 320 may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the second mask layer 320 is formed by an atomic layer deposition process. Therefore, the second mask layer 320 also covers the isolation structure 101, the first mask layer 310, the first doped epitaxial layer 115 and the dummy gate structure of the PMOS region I.

The materials and the formation process of the second mask layer 320 can refer to the related description of the first mask layer 310, and are not repeated herein.

In this embodiment, the second mask layer 320 is made of silicon nitride, and the second mask layer 320 is made of the same material as the first mask layer 310 and the sidewall spacers 300, so as to facilitate reducing the process difficulty of the etching process.

The second mask layer 320 is used as an etching mask for forming the N-region groove 121, and the second mask layer 320 can increase the distance between the formed N-region groove 121 and a device channel region corresponding to the NMOS region ii, thereby facilitating improvement of a short channel effect.

It should be noted that before etching the second mask layer 320 on the tops of the fins 110 on both sides of the pseudo-gate structure in the NMOS region ii, a second pattern layer (not shown) is further formed on the second mask layer 320 in the PMOS region i. The second graphic layer plays a role in protecting the PMOS region i second mask layer 320, and also covers an area in the NMOS region ii that is not desired to be etched.

It should be further noted that, as shown in fig. 17, in order to increase the volume of the second doped epitaxial layer 125 (shown in fig. 19) formed in the N-region groove 121 subsequently, the second mask layer 320, the first mask layer 310 and the sidewall 300 on the sidewall of the fin 110 are etched while the NMOS region ii fin 110 is etched, so that after the N-region groove 121 is formed, the tops of the second mask layer 320, the first mask layer 310 and the sidewall 300 on the sidewall of the NMOS region ii fin 110 are flush with the top of the fin 110.

Referring collectively to fig. 19 and 20, a second doped epitaxial layer 125 is formed within the N region recess 121 (shown in fig. 18).

In this embodiment, a selective epitaxy process is adopted, a stress layer is formed in the N region groove 121, and in the process of forming the stress layer, N-type ions are in-situ self-doped to form the second doped epitaxial layer 125. The top of the second doped epitaxial layer 125 is higher than the top of the N region recess 121.

The stress layer provides a tensile stress effect for a channel region of a device corresponding to the NMOS region II, so that the carrier mobility of the device in the NMOS region II is improved.

In other embodiments, after a stress layer is formed in the N region groove, N-type ion doping may be performed on the stress layer to form a second doped epitaxial layer.

It should be noted that, in this embodiment, the first doped epitaxial layer 115 is formed first, and then the second doped epitaxial layer 125 is formed. In other embodiments, the second doped epitaxial layer may be formed before the first doped epitaxial layer.

With reference to fig. 21 to 23, fig. 21 is a schematic cross-sectional structure based on fig. 19, fig. 22 is a schematic cross-sectional structure based on fig. 16, fig. 23 is a schematic cross-sectional structure based on fig. 21 along a cut line perpendicular to a fin extending direction (as indicated by a cut line A1a2 in fig. 6) at a position of a pseudo gate structure, and in this embodiment, after forming the first doped epitaxial layer 115 and the second doped epitaxial layer 125, the method further includes: an interlayer dielectric layer 102 is formed on the isolation structure 101 exposed from the dummy gate structure (not labeled), and the interlayer dielectric layer 102 is exposed from the top of the dummy gate structure.

The interlayer dielectric layer 102 is used for realizing electrical isolation between semiconductor devices and also used for defining the size and the position of a metal gate structure.

In this embodiment, the interlayer dielectric layer 102 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like.

Specifically, the step of forming the interlayer dielectric layer 102 includes: forming a dielectric material layer on the isolation structure 101 exposed out of the dummy gate structure, wherein the dielectric material layer covers the dummy gate structure; and removing the dielectric material layer higher than the top of the pseudo gate structure by means of chemical mechanical polishing and the like to expose the top of the pseudo gate structure, and taking the residual dielectric material layer as an interlayer dielectric layer 102.

It should be noted that the second mask layer 320 is formed on the isolation structure 101 exposed by the dummy gate structure, so that the interlayer dielectric layer 102 also covers the second mask layer 320.

It should be further noted that a gate mask layer 210 is formed on the top of the dummy gate structure (as shown in fig. 20), so in the step of forming the interlayer dielectric layer 102, the gate mask layer 210 is also removed. In this embodiment, after the interlayer dielectric layer 102 is formed, the top of the interlayer dielectric layer 102 is flush with the top of the gate layer 122.

In addition, since the forming processes of the interlayer dielectric layer 102 of the PMOS region i and the NMOS region ii are the same, fig. 22 only illustrates the PMOS region i, and a schematic structural diagram of the NMOS region ii is not shown.

With combined reference to fig. 24 to 26, fig. 24 is a schematic cross-sectional structure based on fig. 21, fig. 25 is a schematic cross-sectional structure based on fig. 22, and fig. 26 is a schematic cross-sectional structure based on fig. 23, in which the gate layer 122 (shown in fig. 23) is removed to expose the isolation structure 101.

By removing the gate layer 122, a process basis is provided for the subsequent removal of the gate oxide layer 121.

In this embodiment, the process of removing the gate layer 122 is a wet etching process. The gate layer 122 is made of polysilicon, and correspondingly, the etching solution used by the wet etching tool is a tetramethylammonium hydroxide (TMAH) solution.

In this embodiment, after removing the gate layer 122, an opening 105 (as shown in fig. 25) exposing the gate oxide layer 121 and a part of the isolation structure 101 is formed in the interlayer dielectric layer 102, and the opening 105 is located in the interlayer dielectric layer 102 in the PMOS region I and the NMOS region ii.

It should be noted that, when the substrate 100 further includes a peripheral region (not shown), the step of removing the gate layer 122 further removes the gate layer 122 in the peripheral region, and accordingly, the opening 105 is also located in the interlayer dielectric layer 102 in the peripheral region.

With combined reference to fig. 27 to fig. 32, fig. 27 is a schematic cross-sectional structure based on fig. 24, fig. 28 is a schematic cross-sectional structure based on fig. 25, fig. 29 is a schematic cross-sectional structure based on fig. 26, fig. 30 is a schematic cross-sectional structure based on fig. 27, fig. 31 is a schematic cross-sectional structure based on fig. 28, fig. 32 is a schematic cross-sectional structure based on fig. 29, and after removing the gate layer 122 (as shown in fig. 23), a protection layer 410 (as shown in fig. 32) is formed on the isolation structure 101.

The protective layer 410 covers the isolation structure 101, so that in the subsequent process of removing the gate oxide layer 121, the protective layer 410 can protect the isolation structure 101, avoid etching loss of the isolation structure 101, prevent the problem that part of the fin portion 110 in the isolation structure 101 is exposed, prevent the problem that feet are generated at the corners (shown by dotted circles in fig. 32) of the fin portion 110 and the top of the isolation structure 101, and be beneficial to avoiding deterioration of a short channel effect, thereby improving the electrical performance and yield of a semiconductor device.

Therefore, the material of the protection layer 410 is different from the material of the gate oxide layer 121. In this embodiment, the material of the protection layer 410 is silicon nitride. In other embodiments, the material of the protective layer may also be silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, boron nitride, boron carbonitride, or a high-k gate dielectric material.

It should be noted that the thickness of the protective layer 410 is not too small, nor too large. If the thickness of the protection layer 410 is too small, the subsequent protection effect on the isolation structure 101 is not obvious, and the isolation structure 101 is prone to etching loss; if the thickness of the protection layer 410 is too large, a waste of process costs is caused and a process risk is easily increased. For this purpose, in this embodiment, the thickness of the protection layer 410 is

To

The step of forming the protective layer 410 is described in detail below with reference to the accompanying drawings.

Referring to fig. 27 to 29 in combination, a protective film 400 (shown in fig. 29) is formed on the surface of the gate oxide layer 121 (shown in fig. 29) and the surface of the isolation structure 101.

The protective film 400 provides a process foundation for the formation of the subsequent protective layer 410.

In this embodiment, the material of the protection layer 410 is silicon nitride, and correspondingly, the material of the protection film 400 is silicon nitride.

In this embodiment, the process of forming the protection film 400 is an atomic layer deposition process.

Therefore, in the step of forming the protection film 400, the protection film 400 is located on the sidewall and the bottom of the opening 105 (as shown in fig. 28), and the protection film 400 is also located on the top of the interlayer dielectric layer 102.

In the subsequent step, in order to remove the gate oxide layer 121, the protective film 400 needs to be removed first to expose the gate oxide layer 121, so that in order to expose the gate oxide layer 121 and ensure that the isolation structure 101 has a residual protective film 400 thereon to protect the isolation structure 101, after the protective film 400 is formed, the thickness of the protective film 400 on the surface of the isolation structure 101 is greater than the thickness of the protective film 400 on the sidewall of the fin portion 110.

Due to the process characteristics of the atomic layer deposition process, the process environments of the surface of the isolation structure 101, the top of the fin 110 and the top of the interlayer dielectric layer 102 are the same, and the process environments of the sidewall of the opening 105 and the sidewall of the fin 110 are the same, so the thicknesses of the protection films 400 on the surface of the isolation structure 101, the top of the fin 110 and the top of the interlayer dielectric layer 102 are the same, and the thicknesses of the sidewall of the opening 105 and the protection film 400 on the sidewall of the fin 110 are the same.

The thickness of the protection film 400 on the surface of the isolation structure 101 and the thickness of the protection film 400 on the sidewall of the fin 110 are determined according to the thickness of the subsequent protection layer 410, that is, the difference between the thickness of the protection film 400 on the surface of the isolation structure 101 and the thickness of the protection film 400 on the sidewall of the fin 110 is the thickness of the protection layer 410.

However, the thickness of the protective film 400 is not necessarily too small, nor too large. If the thickness of the protection film 400 is too small, it is difficult to control the thickness of the protection film 400, which increases the difficulty of the process for forming the protection film 400, especially the protection film 400 on the sidewall of the fin portion 110; if the thickness of the protective film 400 is too large, a waste of process costs is caused and a process risk is easily increased. For this reason, in the present embodiment, after the protective film 400 is formed, the thickness of the protective film 400 on the surface of the isolation structure 101 is as follows

To

The thickness of the protective film 400 on the sidewalls of the fin 110 is set to

To

It should be noted that the thicknesses of the surface of the isolation structure 101 and the protective film 400 on the top of the fin portion 110 are the same, and after the gate oxide layer 121 is subsequently exposed, not only the residual protective film 400 is provided on the isolation structure 101, but also the residual protective film 400 is provided on the top of the fin portion 110, so that by reasonably setting the thickness of the protective film 400, the problem that the thickness of the subsequent residual protective film 400 on the top of the fin portion 110 is too large can be avoided, thereby avoiding the problem that the thickness of the gate dielectric layer of the formed semiconductor device is too large, and further avoiding the adverse effects on the electrical performance and yield of the formed semiconductor device.

Correspondingly, the atomic layer deposition process parameters are reasonably set according to the thickness of the protective film 400 on the surface of the isolation structure 101 and the thickness of the protective film 400 on the side wall of the fin portion 110.

Specifically, the parameters of the atomic layer deposition process include: the adopted precursor is a precursor containing silicon and nitrogen, the process temperature is 80-200 ℃, the pressure is 1 mTorr-20 Torr, the gas flow of the precursor is 500-5000 sccm, and the deposition times are 8-100. Wherein the number of depositions is determined according to the thickness of the protective film 400.

The smaller the pressure of the atomic layer deposition process is, the slower the deposition rate is, and under the condition of the smaller pressure, the process effect that the thickness of the protection film 400 on the surface of the isolation structure 101 is larger than the thickness of the protection film 400 on the sidewall of the fin portion 110 can be achieved.

However, the pressure of the atomic layer deposition process should not be too low, nor too high. If the pressure is too small, the formation efficiency of the protective film 400 is easily lowered; if the pressure is too high, the deposition rate of the protection film 400 is too fast, which may cause a problem that the difference between the thickness of the protection film 400 on the surface of the isolation structure 101 and the thickness of the protection film 400 on the sidewall of the fin 110 is not significant. For this reason, in this embodiment, the pressure of the atomic layer deposition process is 1mTorr to 20 Torr.

With reference to fig. 30 to 32, the protective film 400 (shown in fig. 29) on the surface of the gate oxide layer 121 on the sidewall of the fin 110 is removed, and the remaining protective film 400 is used as a protective layer 410 (shown in fig. 2), where the protective layer 410 is also on the surface of the gate oxide layer 121 on the top of the fin 110.

The gate oxide layer 121 is exposed by removing the protective film 400 on the sidewall of the fin portion 110, thereby providing a process foundation for the subsequent removal of the gate oxide layer 121.

In this embodiment, the process of removing the protective film 400 on the surface of the gate oxide layer 121 on the sidewall of the fin portion 110 is a wet etching process.

The material of the protective film 400 is silicon nitride, and correspondingly, the etching solution adopted by the wet etching process is phosphoric acid solution. The specific parameters of the wet etching process are determined according to the thickness of the protective film 400 on the sidewall of the fin 110.

The wet etching process has the characteristic of isotropic etching, so that the wet etching process etches the protective film 400 on the sidewall of the fin portion 110, and also etches the protective film 400 on the surface of the isolation structure 101, the top of the fin portion 110, the top of the interlayer dielectric layer 102 and the sidewall of the opening 105.

Because the thicknesses of the protective films 400 on the surface of the isolation structure 101, the top of the fin portion 110 and the top of the interlayer dielectric layer 102 are the same, and the thicknesses of the protective films 400 on the side walls of the opening 105 and the side walls of the fin portion 110 are the same, after the wet etching process, the protective films 400 on the side walls of the fin portion 110 and the side walls of the opening 105 are removed, and the surface of the isolation structure 101, the top of the fin portion 110 and the top of the interlayer dielectric layer 102 are provided with residual protective films 400; that is, the protection layer 410 is located on the surface of the isolation structure 101, on the top of the fin 110, and on the top of the interlayer dielectric layer 102.

When the substrate 100 further includes a peripheral region (not shown), in the step of forming the protective film 400, the protective film 400 is further formed on the bottom and the sidewall of the peripheral region opening 105 and the interlayer dielectric layer 102 in the peripheral region; in the step of etching the protective film 400, a pattern layer (not shown) is formed in the peripheral region, so that the protective layer 410 is also located on the gate oxide layer 121 exposed by the peripheral region opening 105, on the surface of the isolation structure 101, and on the interlayer dielectric layer 102 in the peripheral region.

With reference to fig. 33 to 35, fig. 33 is a schematic cross-sectional structure based on fig. 30, fig. 34 is a schematic cross-sectional structure based on fig. 31, and fig. 35 is a schematic cross-sectional structure based on fig. 32, after the protective layer 410 is formed, the gate oxide layer 121 is removed (as shown in fig. 32).

And removing the gate oxide layer 121 to provide a process foundation for the subsequent formation of a high-k gate dielectric layer.

In this embodiment, the gate oxide layer 121 is removed by a dry etching process, which is a SiCoNi etching process.

In another embodiment, the gate oxide layer can be removed by adopting a Cartas etching process. The Cartas etching process refers to a process for etching the gate oxide layer by using hydrofluoric acid formed by heat treatment.

The gate oxide layer 121 on the sidewall of the fin 110 is exposed to an etching environment, so that the gate oxide layer 121 on the sidewall of the fin 110 is etched and removed.

In the process of removing the gate oxide layer 121, the protection layer 410 can protect the isolation structure 101, and prevent the isolation structure 101 from being etched and lost, so as to prevent a problem that a portion of the fin 110 located in the isolation structure 101 is exposed, and prevent a problem that a foot is generated at a corner (shown by a dotted circle in fig. 32) of the fin 110 and the top of the isolation structure 101.

Since the protection layer 410 is also formed on the gate oxide layer 121 on the top of the fin 110, the gate oxide layer 121 on the top of the fin 110 is retained after the etching process.

The material of the protection layer 410 may be used as a gate Dielectric material, so that the protection layer 410, the gate oxide layer 121 and a high-k gate Dielectric layer formed subsequently on the top of the fin 110 may be used as a gate Dielectric layer of a stacked structure, and compared with a scheme in which only a high-k gate Dielectric layer is formed on the top of the fin 110, the thickness of the gate Dielectric layer at the top corner of the fin 110 is increased, thereby facilitating improvement of reliability performance of a semiconductor device, such as Time Dependent Dielectric Breakdown (TDDB).

It should be noted that, when the substrate 100 further includes a peripheral region (not shown), since the protective film 400 (as shown in fig. 29) in the peripheral region is retained, that is, the protective layer 410 in the peripheral region covers the gate oxide layer 121, the thickness of the gate dielectric layer of the device corresponding to the peripheral region is correspondingly increased, thereby facilitating to improve the performance of the peripheral device.

Referring to fig. 36-38 in combination, fig. 36 is a schematic cross-sectional structure based on fig. 33, fig. 37 is a schematic cross-sectional structure based on fig. 34, and fig. 38 is a schematic cross-sectional structure based on fig. 35, after removing the gate oxide layer 121 (as shown in fig. 32), a high-k gate dielectric layer 510 crossing the fin 110 is formed, and the high-k gate dielectric layer 510 covers a portion of the sidewall and the top surface of the fin 110.

By adopting the high-k gate dielectric layer 510 material to replace the traditional silicon dioxide gate dielectric material, the leakage current problem caused by the continuous reduction of the characteristic dimension of the fin field effect transistor is overcome.

The high-k gate dielectric layer 510 is made of a gate dielectric material having a relative dielectric constant greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer 510 is HfO₂. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO₂Or Al₂O₃。

The protective layer 410 is formed on the top of the fin 110, so the high-k gate dielectric layer 510 covers the sidewalls of the fin 110 and the surface of the protective layer 410 on the top of the fin 110.

In this embodiment, the process of forming the high-k gate dielectric layer 510 is an atomic layer deposition process, so the high-k gate dielectric layer 120 is also formed on the protective layer 410 on the surface of the isolation structure 101 and on the top of the interlayer dielectric layer 102; that is, the high-k gate dielectric layer 510 is located on the bottom and sidewalls of the opening 105 (shown in fig. 37) and on top of the interlevel dielectric layer 102.

Before forming the high-k gate dielectric layer 510, the method further includes the steps of: an Interfacial Layer (IL) 123 is formed on the surface of the fin 110 (as shown in fig. 38).

The interfacial layer 123 is formed by oxidizing the fin 110, and thus the interfacial layer 123 is formed only on the sidewall surface of the fin 110. Accordingly, the interfacial layer 123 is located between the sidewall of the fin 110 and the high-k gate dielectric layer 510.

In this embodiment, the fin 110 is made of silicon, and thus the interface layer 123 is made of silicon oxide.

On one hand, the interface layer 123 is used as a part of a gate dielectric layer of the formed semiconductor device; on the other hand, the interface layer 123 is used to provide a good interface foundation for forming the high-k gate dielectric layer 510, so as to improve the quality of the formed high-k gate dielectric layer 510, reduce the interface state density between the high-k gate dielectric layer 510 and the fin portion 110, and avoid adverse effects caused by direct contact between the high-k gate dielectric layer 510 and the fin portion 110.

Correspondingly, the invention also provides a semiconductor structure.

With continuing reference to fig. 36-38, fig. 36 is a schematic cross-sectional view taken along a line perpendicular to the extending direction of the fin at the location of the doped epitaxial layer (as indicated by the line B1B2 in fig. 6), fig. 37 is a schematic cross-sectional view taken along a line perpendicular to the extending direction of the fin at the location of the fin in the PMOS region (as indicated by the line C1C2 in fig. 6), and fig. 38 is a schematic cross-sectional view taken along a line perpendicular to the extending direction of the fin at the location of the opening of the interlayer dielectric layer (as indicated by the line A1a2 in fig. 6), the semiconductor structure comprising:

a substrate 100; a fin 110 on the substrate 100; an isolation structure 101 located on the substrate 100, wherein a top of the isolation structure 101 is lower than a top of the fin 110; a protective layer 410 on the isolation structure 101; and a high-k gate dielectric layer 510 crossing the fin 110 and covering a portion of the sidewall and the top surface of the fin 110.

The substrate 100 provides a process operation basis for the formation of the finfet, and the fin 110 is used to provide a channel of the finfet.

In this embodiment, the substrate 100 is a silicon substrate.

The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon.

In this embodiment, taking the fin field effect transistor as a CMOS device as an example, the substrate 100 includes a PMOS region i and an NMOS region ii, and the PMOS region i and the NMOS region ii are core regions for forming a core device. In other embodiments, the substrate may include only NMOS regions or only PMOS regions.

It should be noted that, in the present embodiment, the substrate 100 may further include a peripheral region (not shown) for forming a peripheral device (or referred to as an input/output device).

In addition, the semiconductor structure further includes: an interlayer dielectric layer 102 is located on the isolation structure 101, and an opening 105 (shown in fig. 37) is formed in the interlayer dielectric layer 102 and penetrates through the interlayer dielectric layer 102.

Since the forming processes of the interlayer dielectric layers 102 of the PMOS region i and the NMOS region ii are the same, fig. 37 only illustrates the PMOS region i, and does not show the structural diagram of the NMOS region ii.

In addition, when the substrate 100 further includes a peripheral region (not shown), the opening 105 is also located in the interlayer dielectric layer 102 of the peripheral region.

It should be further noted that, in this embodiment, the semiconductor structure further includes: a gate oxide layer 121 located between the high-k gate dielectric layer 510 and the top of the fin 110.

The PMOS region i and the NMOS region ii are core regions, and in semiconductor manufacturing, a gate oxide layer 121 is usually formed on the surface of the fin 110 in the PMOS region i and the NMOS region ii, and then the gate oxide layer 121 is removed, and then a high-k gate dielectric layer 510 is formed on the exposed fin 110.

The protection layer 410 is used for protecting the isolation structure 101 in the process of removing the gate oxide layer 121, so as to prevent the isolation structure 101 from being etched and lost, thereby preventing the problem that part of the fin portion 110 located in the isolation structure 101 is exposed, and preventing the problem that feet are generated at the fin portion 110 and the corner (shown by a dotted circle in fig. 32) at the top of the isolation structure 101, which is beneficial to avoiding the deterioration of the short channel effect, and further improving the electrical performance and yield of the semiconductor device.

Since the protection layer 410 is formed by a deposition process, and in the step of forming the protection layer 410, the protection layer 410 covers the gate oxide layer 121 on the top of the fin 110 and the top of the interlayer dielectric layer 102, in the step of removing the gate oxide layer 121, the gate oxide layer 121 on the top of the fin 110 is retained under the protection effect of the protection layer 410; correspondingly, the protection layer 410 is also located between the high-k gate dielectric layer 510 and the gate oxide layer 121, and the protection layer 410 is also located on the top of the interlayer dielectric layer 102.

Specifically, the protection layer 410 is located on the surface of the isolation structure 101 exposed by the opening 105, on the top of the fin 110 exposed by the opening 105, and on the top of the interlayer dielectric layer 102. That is, the protection layer 410 is located at the bottom of the opening 105 and on top of the interlayer dielectric layer 102.

The material of the protection layer 410 is different from the material of the gate oxide layer 121. In this embodiment, the material of the protection layer 410 is silicon nitride. In other embodiments, the material of the protective layer may also be silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, boron nitride, boron carbonitride, or a high-k gate dielectric material.

It should be noted that the thickness of the protective layer 410 is not too small, nor too large. If the thickness of the protection layer 410 is too small, the protection effect on the isolation structure 101 is not obvious, and the isolation structure 101 is prone to etching loss; if the thickness of the protection layer 410 is too large, a waste of process costs is caused and a process risk is easily increased. For this purpose, in this embodiment, the thickness of the protection layer 410 is

To

The high-k gate dielectric layer 510 is used to overcome the leakage current problem caused by the shrinking of the finfet transistor feature size.

The protective layer 410 is disposed on top of the fin 110, such that the high-k gate dielectric layer 510 covers the sidewalls of the fin 110 and the surface of the protective layer 410 on top of the fin 110.

In this embodiment, the high-k gate dielectric layer 510 is formed by a deposition process, so that the high-k gate dielectric layer 120 is also located on the protective layer 410 on the surface of the isolation structure 101 and on the protective layer 410 on the top of the interlayer dielectric layer 102.

That is, the high-k gate dielectric layer 510 is located on the protective layer 410 at the bottom of the opening 105 and at the top of the interlayer dielectric layer 102, and on the sidewalls of the opening 105.

The semiconductor structure of the present invention is formed by the foregoing forming method, and for the specific description of the semiconductor structure, please refer to the corresponding description in the foregoing embodiments, which is not repeated herein.

The loss of the isolation structure 101 of the semiconductor structure is less, so that the problem that a part of the fin 110 located in the isolation structure 101 is exposed is prevented, and the problem that a foot (as shown by a dotted circle in fig. 32) is generated at the corner between the fin 110 and the top of the isolation structure 101 can be prevented, which is beneficial to avoiding the deterioration of the short channel effect, and further improving the electrical performance and yield of the semiconductor device.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming a semiconductor structure, comprising:

providing a substrate and discrete fins on the substrate;

forming an isolation structure on the substrate, the top of the isolation structure is lower than the top of the fin;

forming a dummy gate structure across the fin, the dummy gate structure covering part of the sidewall and the top surface of the fin, the dummy gate structure including a gate oxide layer and a gate on the gate oxide layer layer, the gate layer also covers part of the isolation structure;

removing the gate layer to expose the isolation structure;

After the gate layer is removed, a protective layer is formed on the isolation structure, the protective layer covers the isolation structure, and the material of the protective layer is different from the material of the gate oxide layer;

After the protective layer is formed, the gate oxide layer is removed;

After the gate oxide layer is removed, a high-k gate dielectric layer is formed across the fin, and the high-k gate dielectric layer covers part of the sidewalls and the top of the fin.

2 . The method for forming a semiconductor structure according to claim 1 , wherein the protective layer is made of silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and boron nitride. 3 . , carbon boron nitride or high-k gate dielectric materials.

3. The method for forming a semiconductor structure according to claim 1, wherein the protective layer has a thickness of

to

4. The method for forming a semiconductor structure according to claim 1, wherein the step of forming a protective layer on the isolation structure comprises:

forming a protective film on the surface of the gate oxide layer and the surface of the isolation structure;

The protective film on the surface of the gate oxide layer on the sidewall of the fin is removed, and the remaining protective film is used as a protective layer.

5 . The method of claim 4 , wherein after the protective film is formed, the thickness of the protective film on the surface of the isolation structure is greater than the thickness of the protective film on the sidewall of the fin. 6 .

6 . The method for forming a semiconductor structure according to claim 5 , wherein the protective layer is further located on the surface of the gate oxide layer on the top of the fin. 7 .

7 . The method for forming a semiconductor structure according to claim 5 , wherein after the protective film is formed, the thickness of the protective film on the surface of the isolation structure is 7 .

to

The thickness of the protective film on the sidewall of the fin is

to

8 . The method for forming a semiconductor structure according to claim 4 , wherein the process for forming the protective film is an atomic layer deposition process. 9 .

9 . The method for forming a semiconductor structure according to claim 8 , wherein the material of the protective film is silicon nitride, and the parameters of the atomic layer deposition process include: the used precursor is a silicon- and nitrogen-containing precursor. 10 . For the precursor, the process temperature is 80°C to 200°C, the pressure is 1 mTorr to 20 Torr, the gas flow rate of the precursor is 500 sccm to 5000 sccm, and the deposition times are 8 to 100 times.

10 . The method for forming a semiconductor structure according to claim 4 , wherein the process used to remove the protective film on the surface of the gate oxide layer on the sidewall of the fin is a wet etching process. 11 .

11. The method for forming a semiconductor structure according to claim 1, wherein the process for forming the gate oxide layer is a thermal oxidation process.

12. A semiconductor structure, characterized in that it comprises:

substrate;

a fin on the substrate;

a gate oxide layer on part of the sidewalls and the top surface of the fin;

an isolation structure, located on the substrate, the top of the isolation structure is lower than the top of the fin; a protection layer, located on the isolation structure, the protection layer covers the isolation structure, the protection layer The material is different from the material of the gate oxide layer;

A high-k gate dielectric layer spans the fin and covers part of the sidewalls and the top of the fin.

13. The semiconductor structure of claim 12, wherein the protective layer is made of silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, boron nitride, carbon nitride Boronide or high-k gate dielectric material.

14. The semiconductor structure of claim 12, wherein the protective layer has a thickness of

to

15. The semiconductor structure of claim 12, wherein the semiconductor structure further comprises:

a gate oxide layer between the high-k gate dielectric layer and the top of the fin;

The protective layer is also located between the high-k gate dielectric layer and the gate oxide layer.