CN110854194B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: forming a substrate, including a substrate and a plurality of discrete fins located on the substrate; forming a metal gate structure across the fins, and the metal gate structure covers part of the top of the fins. and part of the sidewall; along the extension direction of the fins, an isolation gate structure is formed on the substrate between adjacent fins, and the material of the isolation gate structure is a dielectric material. The present invention forms an isolation gate structure on the substrate between adjacent fins, and the material of the isolation gate structure is a dielectric material; in the semiconductor process, the isolation gate structure is usually in the same process step as the metal gate structure across the fins. Formed in It is beneficial to increase the breakdown voltage of the isolation gate structure, thereby improving the electrical performance of the device.

Description

Semiconductor structures and methods of forming them

Technical field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As one of the basic semiconductor devices, transistors are currently being widely used. Therefore, as the density and integration of semiconductor devices increase, the gate size of planar transistors becomes shorter and shorter. The ability of traditional planar transistors to control channel current becomes weaker, resulting in a short channel effect, causing leakage current to increase, and ultimately Affects the electrical performance of semiconductor devices.

In order to better adapt to the reduction of feature sizes, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field-effect transistors (FinFETs). The structure of a fin field effect transistor usually includes: a fin protruding from a substrate and an isolation structure (for example, a shallow trench isolation structure) located on the substrate. The isolation structure covers part of the side of the fin. wall, and the top of the isolation structure is lower than the top of the fin; a gate structure covering part of the top and part of the sidewall of the fin; source and drain regions located in the fins on both sides of the gate structure .

However, as the size of semiconductor devices continues to shrink, the distance between adjacent fin field effect transistors also shrinks. In order to prevent adjacent fin field effect transistors from merging, the existing technology has introduced a manufacturing technology of a single diffusion break (SDB) isolation structure. The single diffusion partition isolation structure is generally distributed along the extension direction of the fin. By removing part of the fin, one or more trenches are formed in the fin, and the trenches are filled with insulating material. The adjacent remaining fins are isolated, thereby reducing the leakage current between the adjacent remaining fins. The single diffusion partition isolation structure can also avoid the source-drainbridge problem between the source region and the drain region.

However, after the single diffusion barrier isolation structure is introduced into the semiconductor structure, the device still suffers from poor performance.

Contents of the invention

The problem solved by the present invention is to provide a semiconductor structure and a forming method thereof to improve device performance.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, which includes: forming a substrate, including a substrate and a plurality of discrete fins located on the substrate; forming a metal gate structure across the fins, The metal gate structure covers part of the top and part of the sidewall of the fin; along the extension direction of the fin, an isolation gate structure is formed on the substrate between adjacent fins, the isolation gate structure The material is a dielectric material.

Correspondingly, the present invention also provides a semiconductor structure, including: a substrate, including a substrate and a plurality of discrete fins located on the substrate; a metal gate structure spanning the fins, and the metal gate structure covers Part of the top and part of the sidewall of the fin; an isolation gate structure is located on the substrate between adjacent fins along the extension direction of the fin; the material of the isolation gate structure is a dielectric material.

Compared with the existing technology, the technical solution of the present invention has the following advantages:

The present invention forms an isolation gate structure on the substrate between adjacent fins along the extension direction of the fins, and the material of the isolation gate structure is a dielectric material; in the semiconductor process, the isolation gate structure is usually connected across the fins The metal gate structure is formed in the same process step, that is, the material of the isolation gate structure usually includes a metal material. The present invention selects a dielectric material as the material of the isolation gate structure, so that the isolation gate structure has insulating properties, thereby avoiding The isolation gate structure is electrically connected to adjacent fins, thereby increasing the breakdown voltage of the isolation gate structure, which is beneficial to improving the electrical performance of the device.

In an optional solution, before forming the metal gate structure, the forming method further includes: forming a dummy gate structure on the substrate, where the dummy gate structure includes a first dummy gate structure and a second dummy gate structure, The first dummy gate structure spans the fin and covers part of the top and sidewalls of the fin. The second dummy gate structure is located between adjacent fins along the extension direction of the fin. On the substrate, a metal gate structure is subsequently formed at the position of the first dummy gate structure by removing the first dummy gate structure. After removing the first dummy gate structure, the present invention retains the third dummy gate structure. Two dummy gate structures are used as the isolation gate structure. In the semiconductor process, the material of the dummy gate structure is usually a dielectric material (for example, polysilicon). By using the second dummy gate structure as the isolation gate structure, it is also simplified accordingly. The process steps for forming the isolation gate structure are disclosed.

In an optional solution, before forming the metal gate structure, the forming method further includes: forming a dummy gate structure on the substrate, where the dummy gate structure includes a first dummy gate structure and a second dummy gate structure, The first dummy gate structure spans the fin and covers part of the top and sidewalls of the fin. The second dummy gate structure is located between adjacent fins along the extension direction of the fin. On the substrate, before removing the first dummy gate structure, the present invention removes the second dummy gate structure, forms a trench in the interlayer dielectric layer, and then fills the trench with dielectric material. The dielectric material in the trench is used as the isolation gate structure; the isolation gate structure is formed by removing the first dummy gate structure and refilling the dielectric material, which accordingly improves the material of the isolation gate structure. The flexibility of selection means that appropriate materials can be selected according to actual process requirements, which is also conducive to further improving device performance.

Description of drawings

Figure 1 is a schematic structural diagram of a semiconductor structure;

Figure 2 is a cumulative distribution function diagram of the breakdown voltage of the gate structure at different positions in the semiconductor structure shown in Figure 1;

3 to 10 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention;

11 to 14 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure according to another embodiment of the present invention;

15 to 16 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention.

Detailed ways

It can be known from the background art that after the single diffusion barrier isolation structure is introduced into the semiconductor structure, the device still has the problem of poor performance. Now let’s analyze the reasons why its performance needs to be improved based on a semiconductor structure.

Referring to FIG. 1 , a schematic structural diagram of a semiconductor structure is shown.

The semiconductor structure includes: a substrate (not labeled), including a substrate 10 and a plurality of discrete fins 20 located on the substrate 10, and the extending direction of the fins 20 is a first direction (not labeled), The direction parallel to the surface of the substrate 10 and perpendicular to the first direction is a second direction (not labeled), and the fins 20 are arranged in a matrix in the first direction and the second direction; an isolation structure (not labeled) (labeled), located on the substrate 10 where the fins 20 are exposed, the isolation structure includes a first isolation layer (not shown) for isolating the fins 20 in the second direction, and The second isolation layer 11 is isolated between the first direction fins 20. The second isolation layer 11 penetrates the first isolation layer along the second direction, and the second isolation layer is used as an SDB. Isolation structure; a metal gate structure 30 spanning the fin 20 , the metal gate structure 30 covering part of the top and part of the sidewall of the fin 20 ; an isolation gate structure 40 located on the second isolation layer 11 ; Sidewalls 35, covering the sidewalls of the metal gate structure 30 and the sidewalls of the isolation gate structure 40; interlayer dielectric layer 12, located on the substrate 10 exposed by the metal gate structure 30 and the isolation gate structure 40, so The interlayer dielectric layer 12 exposes the top of the metal gate structure 30 and the top of the isolation gate structure 40 .

The metal gate structure 30 is usually formed by forming a high-k gate dielectric layer and then forming a metal gate (high klast metal gate last), and in the semiconductor process, the metal gate structure 30 is usually connected to the isolation gate structure 40 formed in the same process step. Specifically, the step of forming the metal gate structure 30 and the isolation gate structure 40 includes: forming a dummy gate structure on the substrate 10 , the dummy gate structure spans the fin portion 20 and covers the fin portion 20 Part of the top and part of the sidewall, along the extension direction of the fin 20, the dummy gate structure is also located on the second isolation layer 11; an interlayer dielectric is formed on the substrate 10 where the dummy gate structure is exposed Layer 12; remove the dummy gate structure, form a gate opening in the interlayer dielectric layer 12; form a high-k gate dielectric layer 31 on the bottom and side walls of the gate opening, and form the high-k gate dielectric layer 31 on the bottom and side walls of the gate opening. The gate opening of the k-gate dielectric layer 31 is filled with metal material to form the gate electrode layer 32; wherein, the high-k gate dielectric layer 31 and the gate electrode layer 32 across the fin portion 20 constitute the metal gate structure 30, located The high-k gate dielectric layer 31 and the gate electrode layer 32 on the second isolation layer 11 constitute the isolation gate structure 40 .

In addition, in order to improve carrier mobility, the semiconductor process usually uses strained silicon technology. That is, after forming the dummy gate structure, it also includes: etching the fins 20 on both sides of the dummy gate structure. After a groove is formed in the fin portion 20 , a stress layer doped with ions is formed in the groove to serve as a source and drain doping layer. Among them, in order to improve the topography quality of the groove on the side close to the end of the fin 20 (the position shown by the dotted circle a in Figure 1), the dummy area on the second isolation layer 11 is usually increased. The width of the gate structure along the first direction (not labeled) allows the sidewalls 35 to cover part of the top of the end of the fin 20 , thereby allowing the sidewalls 35 to control the shape of the groove. The role of appearance.

After increasing the width of the dummy gate structure on the second isolation layer 11 along the first direction, the distance from the dummy gate structure to the fins 20 decreases accordingly along the first direction. When the dummy gate structure is shifted along the first direction, the dummy gate structure is easily in contact with the end surface of the fin 20 (at the position shown by the dotted frame b in Figure 1); accordingly , after the isolation gate structure 40 is formed, the isolation gate structure 40 is easily bridged with the end surface of the fin 20 . And as the feature size of the device decreases, the probability of bridging between the isolation gate structure 40 and the end surface of the fin 20 becomes higher and higher.

With reference to Figure 2, Figure 2 is a cumulative distribution function (CDF) diagram of the breakdown voltage of the gate structure at different positions in the semiconductor structure shown in Figure 1. The abscissa represents the breakdown voltage (Vbd), and the vertical axis represents the breakdown voltage (Vbd). The coordinates represent the sum of the probabilities of all situations that are less than or equal to the breakdown voltage value under a certain breakdown voltage value. The curve 41 represents the cumulative distribution function diagram of the breakdown voltage of the metal gate structure 30 , and the curve 42 represents Cumulative distribution function diagram of the breakdown voltage of the isolation gate structure 40 . The isolation gate structure 40 is made of a metal material. If the isolation gate structure 40 is bridged with the end surface of the fin 20 , the breakdown voltage of the isolation gate structure 40 will be easily reduced. Specifically, as shown in FIG. 2 , the breakdown voltage of the isolation gate structure 40 is smaller than the breakdown voltage of the metal gate structure 30 .

In order to solve the technical problem, the present invention forms an isolation gate structure on the substrate between adjacent fins along the extension direction of the fins, and the material of the isolation gate structure is a dielectric material; in the semiconductor process, The isolation gate structure is usually formed in the same process step as the metal gate structure across the fin, that is, the material of the isolation gate structure usually includes a metal material. The present invention selects a dielectric material as the material of the isolation gate structure to make the isolation The gate structure has insulating properties, thereby preventing the isolation gate structure from being electrically connected to adjacent fins, thereby increasing the breakdown voltage of the isolation gate structure, which is beneficial to improving the electrical performance of the device.

In order to make the above objects, features and advantages of the present invention more obvious and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

3 to 10 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to Figures 3 and 4 in conjunction, Figure 3 is a perspective view (only two initial fins are shown), Figure 4 is a perspective view based on Figure 3 (only four fins are shown), forming a base (not labeled), including a lining The base 110 and a plurality of discrete fins 120 located on the substrate 110 (as shown in FIG. 4 ).

In this embodiment, the substrate 110 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon substrate on an insulator or an insulator. on germanium substrates and other types of substrates.

In this embodiment, the fin portion 120 and the substrate 110 have an integrated structure. In other embodiments, the fin portion may also be a semiconductor layer grown epitaxially on the substrate, thereby achieving the purpose of accurately controlling the height of the fin portion.

Therefore, in this embodiment, the material of the fin portion 120 is the same as the material of the substrate 110 , and the material of the fin portion 120 is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other semiconductor materials suitable for forming fins. The material of the fins may also be made of The substrates are made of different materials.

Specifically, the steps of forming the fins 120 and the substrate 110 include: providing an initial substrate; forming a fin mask layer 150 on the initial substrate; using the fin mask layer 150 as a mask, etching The initial substrate, the remaining initial substrate after etching is used as the substrate 110, and the protrusions located on the substrate 110 are used as the initial fins 120a (as shown in Figure 3). The extension direction of the initial fins 120a is The first direction (shown as the A1A2 direction in Figure 3), the direction parallel to the surface of the substrate 110 and perpendicular to the first direction is the second direction (shown as the B1B2 direction in Figure 3), the initial The fins 120a are arranged in a matrix in the first direction and the second direction; along the second direction, the fin mask layer 150 and the initial fins 120a are sequentially etched to form the initial fins 120a. Isolation groove 115 (shown in FIG. 4 ), the isolation groove 115 divides the initial fin part 120a into a plurality of fin parts 120.

Correspondingly, the first direction is parallel to the extension direction of the fin portion 120 , the second direction is perpendicular to the extension direction of the fin portion, and the fin portion 120 is aligned between the first direction and the second direction. The directions are arranged in a matrix.

The isolation trench 115 is a single diffusion isolation trench (SDB isolation trench), and the isolation trench 115 is used to provide a spatial location for the subsequent formation of a single diffusion isolation isolation structure. In this embodiment, the isolation groove 115 exposes the top of the substrate 110 . In other embodiments, according to actual process requirements, in the step of forming the fins, a part of the thickness of the substrate is also etched, that is, the bottom of the isolation trench can also be located in the substrate between adjacent fins.

In this embodiment, after the substrate 110 and the fins 120 are formed, the fin mask layer 150 located on top of the fins 120 is retained. The material of the fin mask layer 150 is silicon nitride. When the planarization process is subsequently performed, the top surface of the fin mask layer 150 is used to define the stop position of the planarization process and protect the The function of the top of fin 120.

With reference to FIG. 5 , it should be noted that after forming the substrate 110 and the fins 120 , it also includes: forming an isolation structure (not labeled) on the exposed substrate of the fins 120 , and the isolation structure covers all Part of the sidewall of the fin 120, and the top of the isolation structure is lower than the top of the fin 120, the isolation structure includes a fin for realizing the second direction (shown in the B1B2 direction in Figure 3) The first isolation layer 101 is used to isolate the fins 120 in the first direction (shown in the A1A2 direction in Figure 3), and the second isolation layer 102 is used to isolate the fins 120 in the first direction (shown in the A1A2 direction in Figure 3). 102 penetrates the first isolation layer 101 along the second direction.

The first isolation layer 101 is a shallow trench isolation structure (Shallow Trench Isolation, STI), used to isolate adjacent devices; the second isolation layer 102 is a single diffusion isolation structure, used to reduce The leakage current between adjacent fins 120 is also used to improve the bridging problem between adjacent source and drain doped layers formed subsequently.

Therefore, the materials of the first isolation layer 101 and the second isolation layer 102 are both insulating materials. In this embodiment, the first isolation layer 101 and the second isolation layer 102 are both made of silicon oxide. In other embodiments, the material of the first isolation layer may also be silicon nitride or silicon oxynitride, and the material of the second isolation layer may also be silicon nitride or silicon oxynitride.

Specifically, the step of forming the first isolation layer 101 and the second isolation layer 102 includes: forming an isolation material layer on the substrate 110 where the fin portion 120 is exposed, and the isolation material layer is also filled in the isolation trench. 115 (as shown in Figure 4), and the isolation material layer covers the top of the fin mask layer 150; perform a planarization process on the isolation material layer, and remove the layers higher than the top of the fin mask layer 150. an isolation material layer; after the planarization process, an etch back process is performed on the remaining isolation material layer to remove part of the thickness of the remaining isolation material layer, and the remaining isolation material layer after the etch back process is used as The isolation structure; remove the fin mask layer 150 .

It should be noted that in this embodiment, after the isolation groove 115 (shown in FIG. 4 ) is formed in the initial fin portion 120 a (shown in FIG. 3 ), the first isolation layer 101 and the first isolation layer 101 are formed. The second isolation layer 102 is to first form the first isolation layer on the substrate with the initial fins exposed, then etch the initial fins and the first isolation layer sequentially along the second direction, and then form a layer between adjacent fins. Compared with the solution of forming the second isolation layer between the remaining first isolation layers, this embodiment can form the first isolation layer 101 and the second isolation layer 102 in the same process step, which is beneficial to reducing the formation of the isolation layer. The etching process difficulty of the groove is reduced, the process steps are simplified and the process cost is reduced.

With reference to Figures 6 to 10, Figure 6 is a cross-sectional view based on Figure 5 along the fin extension direction and at the secant line at the top position of the fin (as shown by the C1C2 secant line in Figure 5). Figures 7 to 10 are based on 6 , a metal gate structure 400 is formed across the fin 120 (as shown in FIG. 10 ), and the metal gate structure 400 covers part of the top and part of the sidewall of the fin 120; along the In the first direction (shown in the A1A2 direction in Figure 3), an isolation gate structure 300 (shown in Figure 9) is formed on the substrate 110 between adjacent fins 120. The material of the isolation gate structure 300 It is a dielectric material.

In semiconductor processes, the isolation gate structure is usually formed in the same process step as the metal gate structure, that is, the material of the isolation gate structure usually includes metal materials. In this embodiment, by selecting a dielectric material as the material of the isolation gate structure 300, the isolation gate structure 300 has insulating properties and avoids the end surface of the isolation gate structure 300 and the adjacent fin 120 (as shown in Figure 9 The electrical connection occurs at the position shown in the dotted box D), which is beneficial to increasing the breakdown voltage of the isolation gate structure 300, thereby improving the electrical performance of the device.

The steps of forming the metal gate structure 400 and the isolation gate structure 300 will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 6 , a dummy gate structure (not labeled) is formed on the substrate (not labeled). The dummy gate structure includes a first dummy gate structure 210 and a second dummy gate structure 220 . The first dummy gate structure 210 Across the fin 120 and covering part of the top and sidewalls of the fin 120 , along the first direction (shown in the A1A2 direction in FIG. 3 ), the second dummy gate structure 220 is located adjacent to on the substrate 110 between the fins 120 .

In this embodiment, the metal gate structure of the fin field effect transistor is formed by forming a high k last metal gatelast after forming a high k gate dielectric layer. The first dummy gate structure 210 is used for It occupies a spatial position for the formation of the metal gate structure; the second dummy gate structure 220 is used to provide a process basis for the subsequent formation of the isolation gate structure.

In this embodiment, in order to simplify the process steps of forming the first dummy gate structure 210 and the second dummy gate structure 220 and reduce the process cost, the first dummy gate structure 210 and the second dummy gate structure are formed in the same process step. Structure 220, the first dummy gate structure 210 and the second dummy gate structure 220 have the same material and structure, and the top of the first dummy gate structure 210 and the top of the second dummy gate structure 220 are flush.

In this embodiment, the dummy gate structure is a single-layer structure, and the dummy gate structure includes a dummy gate layer. Specifically, the material of the dummy gate layer is polysilicon, that is, the materials of the first dummy gate structure 210 and the second dummy gate structure 220 are both polysilicon. In other embodiments, the material of the dummy gate layer may also be other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxynitride, or amorphous carbon.

In other embodiments, the dummy gate structure may also be a stacked structure. The dummy gate structure may include a dummy gate oxide layer and a dummy gate layer located on the dummy gate oxide layer. The material can be silicon oxide or silicon oxynitride.

In this embodiment, a first dummy gate structure 210 formed on a fin 120 is used as an example for description. In other embodiments, a plurality of mutually spaced and parallel first dummy gate structures may span the same fin.

Specifically, the first dummy gate structure 210 spans the plurality of fins 120 along the second direction (shown in the B1B2 direction in FIG. 3), and the first dummy gate structure 210 and the second dummy gate structure The lengths of 220 along the second direction are equal, so in the step of forming the second dummy gate structure 220 on the substrate 110 between adjacent fins 120, the second dummy gate structure 220 covers all The second isolation layer 102 spans a plurality of isolation trenches 115 along the second direction (as shown in FIG. 4 ). That is to say, the second dummy gate structure 220 not only covers the second isolation layer 102 between adjacent fins 120 , but also covers the second isolation layer 102 between adjacent first isolation layers 101 .

In this embodiment, mask etching is used to form the dummy gate structure. Specifically, the step of forming the dummy gate structure includes: forming a dummy gate material layer on the first isolation layer 101 (shown in FIG. 5 ) and the second isolation layer 102 exposed by the fin portion 120 ; A gate mask layer 250 is formed on the gate material layer; the dummy gate material layer is etched using the gate mask layer 250 as a mask to expose part of the fins 120, the first isolation layer 101 and the second isolation layer 102. , the remaining dummy gate material layer after etching serves as the dummy gate structure.

After the dummy gate structure is formed, the gate mask layer 250 on top of the dummy gate structure is retained. The gate mask layer 250 is made of silicon nitride, and the gate mask layer 250 is used to protect the top of the dummy gate structure during subsequent processes.

It should be noted that after forming the dummy gate structure, it also includes forming spacers 230 on the sidewalls of the dummy gate structure.

The sidewalls 230 can be used as an etching mask for subsequent etching processes, used to define the formation areas of subsequent source and drain doping layers, and also used to protect the sidewalls of the dummy gate structure during subsequent processes. effect.

In this embodiment, a gate mask layer 250 is formed on the top of the dummy gate structure, so the sidewalls 230 also cover the sidewalls of the gate mask layer 250 .

The sidewall 230 may be made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride and boron carbonitride. The side wall 230 may be a single-layer structure or a stacked structure. In this embodiment, the sidewall 230 has a single-layer structure, and the material of the sidewall 230 is silicon nitride.

It should also be noted that the subsequent process also includes etching the fins 120 on both sides of the first dummy gate structure 210, forming grooves in the fins 120, and then forming source and drain doping in the grooves. layer. Along the first direction (shown as the A1A2 direction in Figure 3), in order to improve the groove topography quality on the side close to the end of the fin 120 (the position shown by the dotted circle K in Figure 5), the The width of the first dummy gate structure 210 along the first direction is greater than the width of the second isolation layer 102 along the first direction, thereby ensuring that the sidewalls 230 can cover the ends of the fins 120 Part of the top and part of the side wall at the position, thereby allowing the side wall 230 to play a role in limiting the shape of the groove.

In this embodiment, after forming the spacers 230, the method further includes: etching the fins 120 on both sides of the first dummy gate structure 210, and forming grooves (not shown) in the fins 120; A source and drain doping layer (not shown) is formed in the groove.

Specifically, when the formed semiconductor structure is an NMOS transistor, the source-drain doping layer includes a stress layer doped with N-type ions, and the material of the stress layer can be Si or SiC; when the formed semiconductor structure is a PMOS In the case of a transistor, the source-drain doped layer includes a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.

Referring to FIG. 7 , an interlayer dielectric layer 103 is formed on the substrate 110 where the first dummy gate structure 210 and the second dummy gate structure 220 are exposed, and the interlayer dielectric layer 103 covers the source-drain doped layer (Fig. (not shown), the interlayer dielectric layer 103 exposes the tops of the first dummy gate structure 210 and the second dummy gate structure 220 .

The interlayer dielectric layer 103 is used to achieve electrical isolation between adjacent devices, and the interlayer dielectric layer 103 is also used to define the size and position of subsequent metal gate structures.

The material of the interlayer dielectric layer 103 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 103 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

Specifically, the step of forming the interlayer dielectric layer 103 includes: forming an interlayer dielectric film on the substrate 110 exposed by the first dummy gate structure 210 and the second dummy gate structure 220, and the interlayer dielectric film covers The top of the gate mask layer 250 (as shown in FIG. 6 ); perform a planarization process on the interlayer dielectric film to remove layers higher than the top of the first dummy gate structure 210 and the second dummy gate structure 220 Interlayer dielectric film, retain the remaining interlayer dielectric film as the interlayer dielectric layer 103; remove the gate mask layer 250.

In this embodiment, after the interlayer dielectric layer 103 is formed, the top of the interlayer dielectric layer 103 is flush with the tops of the first dummy gate structure 210 and the second dummy gate structure 220 .

With reference to FIGS. 8 and 9 , the first dummy gate structure 210 (shown in FIG. 8 ) is removed, and a gate opening 104 (shown in FIG. 9 ) is formed in the interlayer dielectric layer 103 .

The gate opening 104 provides a spatial location for subsequent formation of the metal gate structure.

In this embodiment, the first dummy gate structure 210 spans the plurality of fins 120 and covers part of the top and part of the sidewalls of the fins 120. Therefore, after the gate opening 104 is formed, the gate opening 104 is 104 correspondingly exposes part of the top and part of the sidewall of the fin 120 , and the gate opening 104 also exposes part of the first isolation layer 101 (as shown in FIG. 5 ).

Specifically, the step of removing the first dummy gate structure 210 includes: forming a first graphic layer 270 on the interlayer dielectric layer 103 (as shown in FIG. 8 ), and the first graphic layer 270 covers the first graphic layer 270 . Two dummy gate structures 220; using the first pattern layer 270 as a mask, etching and removing the first dummy gate structure 210; after etching and removing the first dummy gate structure 210, remove the first pattern layer 270.

Since the first pattern layer 270 covers the second dummy gate structure 220, after the first dummy gate structure 210 is removed, the second dummy gate structure 220 is retained as the isolation gate structure 300 (as shown in FIG. 9 shown).

In this embodiment, the material of the second dummy gate structure 220 is polysilicon, and the material of the isolation gate structure 300 is correspondingly polysilicon. In other embodiments, according to the selection of the second dummy gate structure material, the material of the isolation gate structure may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or carbonitride oxynitride. Other dielectric materials such as silicon or amorphous carbon.

It should be noted that polysilicon is a dielectric material, so by retaining the second dummy gate structure 220 as the isolation gate structure 300 , it is also possible to avoid the end surfaces (such as Electrical connection occurs at the position shown in the dotted box D in Figure 9).

Moreover, the second dummy gate structure 220 not only covers the second isolation layer 102 between adjacent fins 120 , but also covers the second isolation layer 102 between adjacent first isolation layers 101 . The two dummy gate structures 220 are also in contact with the end surfaces of the fins 120 in the second direction (shown in the B1B2 direction in FIG. 3). This embodiment can also avoid the isolation gate structure 300 from contacting the adjacent fins 120. There is an electrical connection problem on the end face.

In addition, by retaining the second dummy gate structure 220 as the isolation gate structure 300, there is no need for an additional process of forming the isolation gate structure 300, which accordingly simplifies the process steps of forming the isolation gate structure 300 and also reduces the cost. The process complexity and process cost are reduced.

In this embodiment, the material of the first pattern layer 270 is photoresist. In other embodiments, the material of the first pattern layer may also be a hard mask (HM) material, such as: TiN, SiN or SiO ₂ .

Referring to FIG. 10 , the metal gate structure 400 is formed within the gate opening 104 (shown in FIG. 9 ).

Specifically, the step of forming the metal gate structure 400 includes: forming a gate dielectric layer 410 on the bottom and sidewalls of the gate opening 104 , the gate dielectric layer 410 spanning the fins 120 and covering all the gate openings 104 . Part of the top and part of the sidewall of the fin 120, the gate dielectric layer 410 also covers the first isolation layer 101 exposed by the gate opening 104 (as shown in FIG. 5); formed on the gate dielectric layer 410 The gate electrode layer 420 is filled in the gate opening 104 .

It should be noted that in this embodiment, the second dummy gate structure 220 is retained as the isolation gate structure 300, and the metal gate structure 400 is formed on the first dummy gate structure 210 (as shown in FIG. 8 ) position, therefore after the metal gate structure 400 is formed, the top of the metal gate structure 400 is flush with the top of the isolation gate structure 300 .

The material of the gate dielectric layer 410 is a high-k dielectric material. Among them, high-k dielectric materials refer to dielectric materials whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. In this embodiment, the material of the gate dielectric layer 410 is HfO ₂ . In other embodiments, the material of the gate dielectric layer can also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ , etc.

In this embodiment, the material of the gate electrode layer 420 is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti, etc.

11 to 14 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure according to another embodiment of the present invention.

The similarities between this embodiment and the previous embodiment will not be described again here. The difference between this embodiment and the previous embodiment is that by removing the second dummy gate structure 620 (as shown in FIG. 11 ), an isolation gate structure 700 (such as As shown in Figure 13).

Specifically, the forming method includes:

With reference to FIGS. 11 and 12 , after the interlayer dielectric layer 503 is formed on the exposed substrate 510 of the first dummy gate structure 610 and the second dummy gate structure 620 (shown in FIG. 11 ), the second dummy gate is removed. Structure 620 forms a trench 613 in the interlayer dielectric layer 503 (as shown in FIG. 12 ).

The trench 613 is used to provide a spatial location for subsequent formation of the isolation gate structure.

Specifically, the step of removing the second dummy gate structure 620 includes: forming a second graphic layer 660 on the interlayer dielectric layer 503, the second graphic layer 660 covering the first dummy gate structure 610; The second graphic layer 660 is a mask, and the second dummy gate structure 620 is removed by etching. After the second dummy gate structure 620 is removed by etching, the second graphic layer 660 is removed.

In this embodiment, after the second dummy gate structure 620 is formed, the second dummy gate structure 620 covers the second isolation layer 502. Therefore, after the trench 613 is formed, the trench 613 exposes the second isolation layer 502. Second isolation layer 502.

In this embodiment, a dry etching process is used to remove the second dummy gate structure 620 . By using a dry etching process, it is beneficial to improve the efficiency of etching to remove the second dummy gate structure 620, and the dry etching process has anisotropic etching characteristics, which is also beneficial to reducing the dry etching process. The impact of the etching process on other film layers or structures, such as the first dummy gate structure 610 or the fin portion 520 adjacent to the second dummy gate structure 620 .

In this embodiment, the material of the second pattern layer 660 is photoresist. In other embodiments, the material of the second pattern layer may also be a hard mask material, such as TiN, SiN or SiO ₂ .

Referring to Figure 13, after removing the second dummy gate structure 620 (shown in Figure 11), the trench 613 (shown in Figure 12) is filled with dielectric material. The dielectric material in the trench 613 is as the isolation gate structure 700 .

In this embodiment, the material of the isolation gate structure 700 is silicon nitride. Silicon nitride has good insulation properties, and the etching selectivity of polysilicon and silicon nitride is relatively high. When the first dummy gate structure 610 is subsequently removed, maskless etching can be used, which is conducive to simplifying the removal. Process steps of the first dummy gate structure 610 .

In other embodiments, the material of the isolation gate structure can also be polysilicon, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxynitride, boron silicon nitride, silicon oxycarbon, amorphous Carbon, low-k dielectric materials or ultra-low-k dielectric materials. Among them, low-k dielectric materials refer to dielectric materials with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9, and ultra-low-k dielectric materials refer to dielectric materials with a relative dielectric constant less than 2.6.

Specifically, the steps of forming the isolation gate structure 700 include: filling the trench 613 with dielectric material, and the dielectric material also covers the top of the interlayer dielectric layer 503; performing planarization processing on the dielectric material, The dielectric material higher than the top of the interlayer dielectric layer 503 is removed, and the dielectric material in the trench 613 is retained as the isolation gate structure 700 . The top of the isolation gate structure 700 and the top of the first dummy gate structure 610 are flush with each other.

After removing the dielectric material higher than the top of the interlayer dielectric layer 503, the remaining dielectric material exposes the top of the first dummy gate structure 610, thereby providing a process basis for subsequent removal of the first dummy gate structure 610.

In this embodiment, the process of filling the dielectric material into the trench 613 is a chemical vapor deposition process, so that the dielectric material has a good filling effect in the trench 613 .

It should be noted that in this embodiment, the trench 613 is formed by first removing the second dummy gate structure 620 (as shown in FIG. 11 ), and then forming the isolation gate structure in the trench 613 700 is conducive to improving the flexibility of material selection for the isolation gate structure 700, that is, appropriate materials can be selected according to actual process requirements, so it is also conducive to making the device performance meet actual process requirements.

Referring to Figure 14, after forming the isolation gate structure 700, the first dummy gate structure 610 (shown in Figure 13) is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 503; A metal gate structure 800 is formed in the gate opening.

In this embodiment, the metal gate structure 800 includes a gate dielectric layer 810 and a gate electrode layer 820 located on the gate dielectric layer 810 .

For the specific description of the gate opening and the metal gate structure 800, reference may be made to the corresponding descriptions in the previous embodiments, which will not be described again here.

It should be noted that in this embodiment, the top of the isolation gate structure 700 is flush with the top of the first dummy gate structure 610, and the metal gate structure 800 is formed at the position of the first dummy gate structure 610. , so after the metal gate structure 800 is formed, the top of the metal gate structure 800 is flush with the top of the isolation gate structure 700 .

It should also be noted that in this embodiment, the material of the first dummy gate structure 610 and the material of the isolation gate structure 700 have a high etching selectivity ratio. The process of removing the first dummy gate structure 610 The loss to the isolation gate structure 700 is very small. Therefore, during the process of removing the first dummy gate structure 610, there is no need to form a mask layer (such as a photoresist layer) covering the isolation gate structure 700. Therefore, Additional process costs and time waste can be avoided.

In other embodiments, in order to further protect the isolation gate structure, before removing the first dummy gate structure, a mask layer covering the isolation gate structure may also be formed.

For the specific description of the forming method in this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be described again in this embodiment.

Correspondingly, the present invention also provides a semiconductor structure. With reference to Figures 15 and 16, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 15 is a perspective view (only illustrating the substrate, fins and isolation structure). Figure 16 is based on Figure 15 and extends along the fins. direction and the secant line at the top position of the fin (shown as the E1E2 secant line in Figure 15).

The semiconductor structure includes: a substrate (not labeled), including a substrate 910 and a plurality of discrete fins 920 located on the substrate 910; a metal gate structure 930 spanning the fins 920 (as shown in Figure 16 ), the metal gate structure 930 covers part of the top and part of the sidewall of the fin 920; the isolation gate structure 950 (as shown in FIG. 16) is located adjacent to the fin along the extension direction of the fin 920. On the substrate 910 between the portions 920, the material of the isolation gate structure 950 is a dielectric material.

In this embodiment, the substrate 910 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon substrate on an insulator or an insulator. on germanium substrates and other types of substrates.

In this embodiment, the fin 920 and the substrate 910 have an integrated structure. In other embodiments, the fin portion may also be a semiconductor layer grown epitaxially on the substrate, thereby achieving the purpose of accurately controlling the height of the fin portion.

Therefore, in this embodiment, the material of the fin portion 920 is the same as the material of the substrate 910 , and the material of the fin portion 920 is silicon. In other embodiments, the material of the fins may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other semiconductor materials suitable for forming fins. The material of the fins may also be made of The substrates are made of different materials.

In this embodiment, the extension direction of the fin 920 is the first direction (shown as the F1F2 direction in Figure 15), and the extension direction parallel to the surface of the substrate 910 and perpendicular to the first direction is the second direction ( As shown in the G1G2 direction in Figure 15), the fins 920 are arranged in a matrix in the first direction and the second direction.

It should be noted that the semiconductor structure includes: an isolation structure (not labeled) located on the substrate 910 where the fin 920 is exposed, the isolation structure covers part of the sidewall of the fin 920, and the isolation The top of the structure is lower than the top of the fin 920 .

In this embodiment, the isolation structure includes a first isolation layer 901 (as shown in FIG. 15 ) for realizing isolation between the second direction fins 920, and a first isolation layer 901 for realizing the isolation between the first direction fins 920. There is a second isolation layer 902 (as shown in FIG. 15 ) isolated between them, and the second isolation layer 902 penetrates the first isolation layer 901 along the second direction.

The first isolation layer 901 serves as a shallow trench isolation structure for isolating adjacent devices; the second isolation layer 902 serves as a single diffusion isolation structure for reducing the distance between adjacent fins 920 The leakage current is also used to improve the bridging problem between adjacent source and drain doped layers.

Therefore, the materials of the first isolation layer 901 and the second isolation layer 902 are both insulating materials. In this embodiment, the first isolation layer 901 and the second isolation layer 902 are both made of silicon oxide. In other embodiments, the material of the first isolation layer may also be silicon nitride or silicon oxynitride, and the material of the second isolation layer may also be silicon nitride or silicon oxynitride.

In this embodiment, the metal gate structure 930 includes a gate dielectric layer 931 (as shown in FIG. 16 ) and a gate electrode layer 932 (as shown in FIG. 16 ) located on the gate dielectric layer 931 .

In this embodiment, the metal gate structure 930 spans a plurality of fins 920 along the second direction, and for ease of illustration, an example in which one metal gate structure 930 is formed on one fin 920 will be described. In other embodiments, a plurality of mutually spaced and parallel metal gate structures may span the same fin.

Correspondingly, the gate dielectric layer 931 spans the fin portion 920 and covers part of the top and part of the sidewalls of the fin part 920 . The gate dielectric layer 931 also covers part of the first isolation layer 901 .

The gate dielectric layer 931 is made of a high-k dielectric material. Among them, high-k dielectric materials refer to dielectric materials whose relative dielectric constant is greater than the relative dielectric constant of silicon oxide. In this embodiment, the material of the gate dielectric layer 931 is HfO ₂ . In other embodiments, the material of the gate dielectric layer can also be selected from ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ , etc.

In this embodiment, the material of the gate electrode layer 932 is W. In other embodiments, the material of the gate electrode layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti, etc.

It should be noted that the semiconductor structure also includes: spacers 940, located on the sidewalls of the metal gate structure 930 and also on the sidewalls of the isolation gate structure 950; source and drain doped layers (not shown) , located in the fins 920 on both sides of the metal gate structure 930 .

During the formation process of the semiconductor structure, the sidewalls 940 are used to define the formation area of the source and drain doped layers, and are also used to play a role in the sidewalls of the metal gate structure 930 and the isolation gate structure 950 . Protective effects.

The sidewall 940 may be made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride and boron carbonitride. The side wall 940 may be a single-layer structure or a stacked structure. In this embodiment, the sidewall 940 has a single-layer structure, and the material of the sidewall 940 is silicon nitride.

When the formed semiconductor structure is an NMOS transistor, the source-drain doping layer includes a stress layer doped with N-type ions, and the material of the stress layer may be Si or SiC; when the formed semiconductor structure is a PMOS transistor, The source and drain doped layer includes a stress layer doped with P-type ions, and the material of the stress layer may be Si or SiGe.

Along the first direction, the isolation gate structure 950 is located on the substrate 910 between adjacent fins 920 , and the material of the isolation gate structure 950 is a dielectric material.

In this embodiment, the isolation gate structure 950 covers the second isolation layer 902 and extends along the second direction. That is to say, the isolation gate structure 950 covers the second isolation layer 902 between adjacent fins 920 and also covers the second isolation layer 902 between adjacent first isolation layers 901 .

It should be noted that the source-drain doping layer is usually located in a groove in the fin 920. Along the first direction, in order to increase the area close to the end of the fin 920 (dashed circle L in Figure 15 (the position shown)), the width of the isolation gate structure 950 along the first direction is greater than the width of the second isolation layer 902 along the first direction, thereby ensuring that the The side walls 940 can cover part of the top and part of the side walls at the ends of the fins 920, so that the side walls 940 can limit the shape of the groove.

In this embodiment, by selecting a dielectric material as the material of the isolation gate structure 950, the isolation gate structure 950 has insulating properties, thereby avoiding the end surfaces of the isolation gate structure 950 and adjacent fins 920 (as shown in Figure 16 The electrical connection occurs at the position shown in the middle dotted box H), thereby increasing the breakdown voltage of the isolation gate structure 950, which is beneficial to improving the electrical performance of the device.

It should also be noted that the metal gate structure 930 is formed by forming a high k gate dielectric layer and then forming a gate electrode layer (high k last metal gate last). Therefore, during the formation process of the semiconductor structure, usually including a process of forming a dummy gate structure (dummy gate), and the dummy gate structure includes a first dummy gate structure and a second dummy gate structure, the first dummy gate structure spans the fin portion 920 and covers the fin Part of the top and sidewalls of the fin portion 920, along the first direction, the second dummy gate structure is located on the substrate 910 between adjacent fin portions 920, the top of the first dummy gate structure and the second dummy gate structure The top of the pseudo-gate structure is flush. In this embodiment, during the formation process of the semiconductor structure, the metal gate structure 930 is formed at the position of the first dummy gate structure, and the second dummy gate structure is retained as the isolation gate structure 950 , therefore, the top of the isolation gate structure 950 is flush with the top of the metal gate structure 930 .

By retaining the second dummy gate structure as the isolation gate structure 950, there is no need for an additional process of forming the isolation gate structure 950, which accordingly simplifies the process steps of forming the semiconductor structure, and also reduces process complexity and Process costs.

Since the material of the dummy gate structure is usually polysilicon, in this embodiment, the material of the isolation gate structure 950 is polysilicon. Polysilicon is a dielectric material. By selecting the polysilicon material, electrical connection between the isolation gate structure 950 and the end surface of the adjacent fin 920 can also be avoided.

In other embodiments, according to the selection of the material of the dummy gate structure, the material of the isolation gate structure can also be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon nitride oxycarbon. , silicon boron nitride, silicon oxycarbide or amorphous carbon and other dielectric materials.

In other embodiments, during the formation process of the semiconductor structure, the isolation gate structure may also be formed at the position of the second dummy gate structure by removing the second dummy gate structure, thereby improving the Flexibility in material selection for isolation barrier structures. Correspondingly, the material of the isolation gate structure may also be a low-k dielectric material or an ultra-low-k dielectric material.

The semiconductor structure may be formed by the formation method described in the first embodiment, the formation method described in the second embodiment, or other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, which will not be described again in this embodiment.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims (16)

1. A method for forming a semiconductor structure, characterized by comprising: forming a substrate, including a substrate and a plurality of discrete fins located on the substrate; After the substrate is formed and before the metal gate structure is formed, a dummy gate structure is formed on the substrate. The dummy gate structure includes a first dummy gate structure and a second dummy gate structure. The first dummy gate structure spans the The fins cover part of the top and sidewalls of the fins, and along the extension direction of the fins, the second dummy gate structure is located on the substrate between adjacent fins, and the second dummy gate structure The dummy gate structure is used to provide a process basis for forming the isolation gate structure; Form an interlayer dielectric layer on the substrate where the dummy gate structure is exposed, and the interlayer dielectric layer exposes the top of the dummy gate structure; Forming a metal gate structure across the fin, the metal gate structure covering part of the top and part of the sidewall of the fin, including: removing the first dummy gate structure, forming a a gate opening; forming the metal gate structure within the gate opening; Along the extending direction of the fins, an isolation gate structure is formed on the substrate between adjacent fins, and the material of the isolation gate structure is a dielectric material. 2. The method of forming a semiconductor structure according to claim 1, wherein the step of forming an isolation gate structure on the substrate between adjacent fins includes: after removing the first dummy gate structure, The second dummy gate structure is retained as the isolation gate structure. 3. The method of forming a semiconductor structure according to claim 2, wherein the step of removing the first dummy gate structure includes: forming a first pattern layer on the interlayer dielectric layer, the first pattern layer a layer covering the second dummy gate structure; Using the first pattern layer as a mask, etching and removing the first dummy gate structure; After etching and removing the first dummy gate structure, the first pattern layer is removed. 4. The method of forming a semiconductor structure according to claim 3, wherein the material of the first pattern layer is photoresist or a hard mask material. 5. The method of forming a semiconductor structure according to claim 1, wherein after forming an interlayer dielectric layer on the exposed substrate of the dummy gate structure and before removing the first dummy gate structure, the method further includes: Remove the second dummy gate structure and form a trench in the interlayer dielectric layer; The step of forming an isolation gate structure on the substrate between adjacent fins includes: before removing the first dummy gate structure, filling the trench with dielectric material, the dielectric material in the trench Used as the isolation barrier structure. 6. The method of forming a semiconductor structure according to claim 5, wherein the step of removing the second dummy gate structure includes: forming a second pattern layer on the interlayer dielectric layer, the second pattern layer a layer covering the first dummy gate structure; Using the second pattern layer as a mask, etching to remove the second dummy gate structure; After etching to remove the second dummy gate structure, the second pattern layer is removed. 7. The method of forming a semiconductor structure according to claim 5, wherein the process of filling the trench with dielectric material is a chemical vapor deposition process. 8. The method of forming a semiconductor structure according to claim 6, wherein the material of the second pattern layer is photoresist or a hard mask material. 9. The method of forming a semiconductor structure according to claim 2, wherein the material of the isolation gate structure is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or carbonitride oxide. Silicon or amorphous carbon. 10. The method of forming a semiconductor structure according to claim 5, wherein the material of the isolation gate structure is polysilicon, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, carbonitride. Silicon oxide, silicon boron nitride carbon, silicon oxycarbide, amorphous carbon, low-k dielectric materials or ultra-low-k dielectric materials. 11. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the substrate, the extending direction along the fin is a first direction, parallel to the surface of the substrate and perpendicular to The first direction is a second direction, and the fins are arranged in a matrix in the first direction and the second direction; After forming the substrate and before forming the dummy gate structure, the method further includes: forming an isolation structure on the substrate with the fin exposed, the isolation structure covering part of the sidewall of the fin, and the isolation structure The top of the fin is lower than the top of the fin, and the isolation structure includes a first isolation layer used to achieve isolation between the fins in the second direction, and a third isolation layer used to achieve isolation between the fins in the first direction. Two isolation layers, the second isolation layer penetrates the first isolation layer along the second direction. 12. The method of forming a semiconductor structure according to claim 11, wherein in the step of forming a second dummy gate structure on the substrate between adjacent fins, the second dummy gate structure covers a second isolation layer between the fins and also covering the second isolation layer between the first isolation layers. 13. A semiconductor structure, characterized by comprising: A substrate, including a substrate and a plurality of discrete fins located on the substrate; an interlayer dielectric layer located on the substrate and covering part of the sidewall of the fin; a metal gate structure spanning the fin, the metal gate structure covering part of the top and part of the side of the fin wall, and is located in a gate opening formed in the interlayer dielectric layer, and the gate opening is formed by removing a first dummy gate structure that spans the fin and covers all part of the top and side walls of the fin; The isolation gate structure is a second dummy gate structure, located on the substrate between adjacent fins along the extension direction of the fins, and the material of the isolation gate structure is a dielectric material, wherein the third Two dummy gate structures are located on the substrate between adjacent fins, and the second dummy gate structure is used to provide a process basis for forming an isolation gate structure. 14. The semiconductor structure according to claim 13, wherein the material of the isolation gate structure is polysilicon, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxynitride, Silicon boron nitride carbon, silicon oxycarbide, amorphous carbon, low-k dielectric materials or ultra-low-k dielectric materials. 15. The semiconductor structure of claim 13, wherein the extending direction along the fin is a first direction, and a direction parallel to the substrate surface and perpendicular to the first direction is a second direction, The fins are arranged in a matrix in the first direction and the second direction; The semiconductor structure further includes: an isolation structure located on the substrate where the fin is exposed, the isolation structure covers part of the sidewall of the fin, and the top of the isolation structure is lower than the top of the fin, The isolation structure includes a first isolation layer used to achieve isolation between the second direction fins, and a second isolation layer used to achieve isolation between the first direction fins, and the second isolation layer A layer extends through the first isolation layer in the second direction. 16. The semiconductor structure of claim 15, wherein the isolation gate structure covers a second isolation layer between the fins and also covers a second isolation layer between the first isolation layers. .