CN108461544B - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate and a fin part positioned on the substrate; forming an isolation structure on a substrate; forming a pseudo-gate structure which crosses the fin part and covers the top of the fin part and the surface of the side wall; forming a side wall on the side wall of the pseudo gate structure; forming a first dielectric layer exposing the top of the fin part on the isolation structure after forming the side wall; forming grooves in fin parts on two sides of the pseudo-gate structure after forming the first dielectric layer; forming a doped epitaxial layer in the groove; forming a second dielectric layer on the first dielectric layer after forming the doped epitaxial layer, and forming an interlayer dielectric layer with the first dielectric layer; removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer; and filling a metal layer in the opening to form a metal gate structure. In the process of forming the grooves in the fin parts on the two sides of the pseudo gate structure, the first dielectric layer plays a role in protecting the isolation structure, and a gap generated by loss of the isolation structure is avoided from occurring below the side wall, so that the metal layer is prevented from bridging with the doped epitaxial layer through the gap.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background technique

In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to accommodate the reduction in feature size, the channel length of MOSFETs has also been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to better adapt to the reduction of the feature size, the semiconductor process gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate can control the ultra-thin body (fin) from at least two sides. Compared with the planar MOSFET, the gate has stronger control ability on the channel, which can well suppress the short channel effect; and the FinFET is relatively For other devices, it has better compatibility with existing integrated circuit manufacturing.

However, the electrical performance and yield of semiconductor devices formed in the prior art still need to be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor structure and its forming method to optimize the electrical performance and yield of semiconductor devices.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a base, the base includes a substrate and discrete fins located on the substrate; forming a fin on the substrate where the fins are exposed an isolation structure, the isolation structure covering part of the sidewall of the fin; after forming the isolation structure, forming a dummy gate structure across the fin, the dummy gate structure covering part of the top surface of the fin and sidewall surfaces; forming sidewalls on the sidewalls of the dummy gate structure; after forming the sidewalls, forming a first dielectric layer on the isolation structure exposed by the dummy gate structure, and the first dielectric layer is exposed The top of the fin; after forming the first dielectric layer, forming grooves in the fins on both sides of the dummy gate structure; forming a doped epitaxial layer in the groove; forming the doped epitaxial layer Afterwards, a second dielectric layer is formed on the first dielectric layer exposed by the dummy gate structure, the second dielectric layer covers the dummy gate structure and exposes the top of the dummy gate structure, and the second dielectric layer and The first dielectric layer constitutes an interlayer dielectric layer; the dummy gate structure is removed to form an opening in the interlayer dielectric layer; a metal layer is filled in the opening to form a metal gate structure.

Correspondingly, the present invention also provides a semiconductor structure, comprising: a base, the base includes a substrate and discrete fins located on the substrate; an isolation structure is located on the substrate where the fins are exposed, the an isolation structure covering part of the sidewall of the fin; a metal gate structure spanning the fin, the metal gate structure covering part of the top surface and sidewall surface of the fin, the metal gate structure It includes a metal layer; sidewalls located on the side walls of the metal gate structure; doped epitaxial layers located in the fins on both sides of the metal gate structure; and located on the isolation structure exposed by the metal gate structure. An interlayer dielectric layer, the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, the second dielectric layer covers the metal gate structure and exposes the metal gate structure The top of the gate structure.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the present invention, after forming sidewalls on the sidewalls of the dummy gate structure, a first dielectric layer is formed on the isolation structure exposed by the dummy gate structure, and the first dielectric layer exposes the top of the fin. During the subsequent process of forming grooves in the fins on both sides of the dummy gate structure, the first dielectric layer protects the isolation structure, preventing the isolation structure under the sidewall from forming the groove. loss in the process of slotting, so as to avoid the occurrence of gaps under the sidewalls caused by the loss of the isolation structure; therefore, when the openings in the second dielectric layer and the first dielectric layer are subsequently filled with metal layers, there will be no The problem of bridging between the metal layer and the doped epitaxial layer through the gap occurs, that is, through the solution of the present invention, the bridging between the doped epitaxial layer and the metal gate structure can be avoided, thereby making the The electrical performance and yield of semiconductor devices are improved.

In an optional solution, the second dielectric layer and the first dielectric layer form an interlayer dielectric layer, so through the first dielectric layer, there is no need to introduce an additional film layer to protect the isolation structure, and accordingly there is no need to The extra film layer is removed, so the solution of the present invention can simplify the process steps and reduce the process cost.

The present invention provides a semiconductor structure, the semiconductor structure includes an interlayer dielectric layer on the isolation structure exposed by the metal gate structure, the interlayer dielectric layer includes a first dielectric layer, and is located on the first dielectric layer The second dielectric layer covers the metal gate structure and exposes the top of the metal gate structure. In the semiconductor manufacturing process, generally a dummy gate structure across the fin is formed first, grooves are formed in the fins on both sides of the dummy gate structure, and after a doped epitaxial layer is formed in the groove, the dummy gate is removed. structure and fill a metal layer at the position of the dummy gate structure to form the metal gate structure; the first dielectric layer of the semiconductor structure in the present invention is used to protect the isolation structure during the process of forming the groove It plays a protective role to prevent the isolation structure under the side wall from being etched and lost, thereby avoiding the occurrence of gaps under the side wall caused by the loss of the isolation structure, so the semiconductor structure of the present invention will not appear. The bridge between the gap and the doped epitaxial layer avoids the bridge between the doped epitaxial layer and the metal gate structure, thereby improving the electrical performance and yield of the semiconductor structure .

Description of drawings

FIG. 1 and FIG. 2 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure;

3 to 24 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

It can be seen from the background art that the electrical performance and yield of semiconductor devices still need to be improved. Analyze the reasons for this:

Referring to FIG. 1 and FIG. 2 together, it shows a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure. FIG. 1 is a perspective view, and FIG. 2 is based on FIG. Schematic diagram of the cross-sectional structure as shown by X1X2 secant line in Fig. 1 .

Referring to FIG. 1 , a base is provided, the base includes a substrate 10 and discrete fins 11 located on the substrate 10; an isolation structure 12 is formed on the substrate 10 exposed by the fins 11, and the isolation structure 12 Cover part of the sidewall of the fin 11; after forming the isolation structure 12, form a dummy gate structure 13 across the fin 11, the dummy gate structure 13 covers part of the top surface of the fin 11 and Sidewall surfaces: forming sidewalls 14 on the sidewalls of the dummy gate structure 13 .

Referring to FIG. 2 , after forming the sidewalls 14, the fins 11 on both sides of the dummy gate structure 13 (as shown in FIG. 1 ) are etched to form grooves (not shown) in the fins 11. ; forming a doped epitaxial layer 15 in the groove.

After forming the doped epitaxial layer 15, the subsequent steps further include: forming an interlayer dielectric layer (not shown) on the isolation structure 12 exposed by the dummy gate structure 13; removing the dummy gate structure 13, An opening (not shown) is formed in the interlayer dielectric layer; a metal layer is filled in the opening to form a metal gate structure.

When etching the fins 11 on both sides of the dummy gate structure 13 to form grooves, the isolation structure 12 is exposed to the etching environment, so the etching process is likely to cause etching loss to the isolation structure 12 , it is also easy to cause etching loss to the isolation structure 12 below the sidewall 14 (shown by the dotted circle 50 in FIG. Show). Therefore, when the metal layer is filled in the opening, the metal layer not only fills the opening, but also fills the gap; thus it is easy to cause the metal layer to pass through the gap and the doped epitaxial layer 15. Bridging means that the doped epitaxial layer 15 is likely to be bridged with the formed metal gate structure, thereby resulting in a decrease in the electrical performance and yield of the semiconductor device.

Moreover, when forming the P-type doped epitaxial layer 15, the etching amount of the fins 11 on both sides of the dummy gate structure 13 is relatively large, and the remaining fins 11 protrude from the isolation structure after corresponding etching. 12 has a lower height, and the P-type doped epitaxial layer 15 is closer to the isolation structure 12; therefore, when the substrate 10 is used to form a P-type device, the P-type doped epitaxial layer 15 and the metal gate The problem of bridging in polar structures is more pronounced.

In order to solve the above technical problem, the present invention forms a first dielectric layer on the isolation structure exposed by the dummy gate structure after forming sidewalls on the sidewall of the dummy gate structure, and the first dielectric layer exposes the fins the top of. During the subsequent process of forming grooves in the fins on both sides of the dummy gate structure, the first dielectric layer protects the isolation structure, preventing the isolation structure under the sidewall from forming the groove. loss in the process of slotting, so as to avoid the occurrence of gaps under the sidewalls caused by the loss of the isolation structure; therefore, when the openings in the second dielectric layer and the first dielectric layer are subsequently filled with metal layers, there will be no The problem of bridging between the metal layer and the doped epitaxial layer through the gap occurs, that is, through the solution of the present invention, the bridging between the doped epitaxial layer and the metal gate structure can be avoided, thereby making the The electrical performance and yield of semiconductor devices are improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

3 to 24 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIG. 3 , which is a perspective view (only two fins are shown), a base (not labeled) is provided, and the base includes a substrate 100 and discrete fins 110 on the substrate 100 .

The base is used to form a FinFET, the substrate 100 provides a process platform for forming a FinFET, and the fin portion is used to provide a channel of the formed FinFET. In this embodiment, taking the formed fin field effect transistor as a CMOS device as an example, the substrate 100 is used to form a P-type device. In other embodiments, the substrate is used to form an N-type device; or, the substrate is used to form a P-type device and an N-type device.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-on-insulator substrate. substrate or glass substrate. The material of the substrate 100 can be selected suitable for process requirements or easily integrated.

The material of the fin portion 110 is the same as that of the substrate 100 . In this embodiment, the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

Specifically, the steps of forming the substrate 100 and the fins 110 include: providing an initial substrate; forming a patterned fin mask layer 200 on the surface of the initial substrate; using the fin mask layer 200 as The initial substrate is etched with a mask to form a substrate 100 and fins 110 on the substrate 100 .

In this embodiment, after the substrate 100 and the fin 110 are formed, the fin mask layer 200 on the top of the fin 110 remains. The material of the fin mask layer 200 is silicon nitride. When the subsequent planarization process is performed, the top surface of the fin mask layer 200 is used to define the stop position of the planarization process, and to protect the The function of the top of the fin portion 110 is described.

Referring to FIG. 4 , an isolation structure 101 is formed on the substrate 100 exposed by the fin portion 110 , and the isolation structure 101 covers part of the sidewall of the fin portion 110 .

The isolation structure 101 is used as an isolation structure of a semiconductor device, and is used for isolating adjacent devices, and is also used for isolating adjacent fins 110 . In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

Specifically, the step of forming the isolation structure 101 includes: filling an isolation film on the substrate 100 exposed by the fin 110, and the top of the isolation film is higher than the fin mask layer 200 (as shown in FIG. 3 ) top; grinding and removing the isolation film higher than the top of the fin mask layer 200; etching back part of the thickness of the remaining isolation film to expose the top and part of the sidewall of the fin 110 to form the isolation structure 101; The fin mask layer 200 .

Referring to Figure 5 to Figure 7, Figure 5 is a perspective view, Figure 6 is a schematic cross-sectional structure diagram of Figure 5 along the vertical fin extension direction secant (as shown by B1B2 secant in Figure 5), and Figure 7 is a schematic diagram of Figure 5 along the fin Schematic diagram of the cross-sectional structure of the secant line in the extension direction (as shown by the A1A2 secant line in FIG. 5 ), after the isolation structure 101 is formed, a dummy gate structure 120 across the fin 110 is formed, and the dummy gate structure 120 covers all Part of the top surface and the sidewall surface of the fin portion 110.

In this embodiment, the metal gate structure is formed by forming a high k last metal gate layer after forming a high k gate dielectric layer, and the dummy gate structure 120 occupies a spatial position for subsequent formation of a metal gate structure.

The dummy gate structure 120 is a stack structure, and the dummy gate structure 120 includes a dummy oxide layer 121 and a dummy gate layer 122 on the dummy oxide layer 121 . Wherein, the material of the dummy gate layer 122 is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon, and the material of the dummy oxide layer 121 is Silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy oxide layer 121 is silicon oxide, and the material of the dummy gate layer 122 is polysilicon. In other embodiments, the dummy gate structure may also be a single-layer structure, and the dummy gate structure includes a dummy gate layer.

Specifically, the step of forming the dummy gate structure 120 includes: forming a dummy oxide layer 121 on the isolation structure 101, the dummy oxide layer 121 spans the fin portion 110 and covers the top surface of the fin portion 110 and sidewall surfaces; form a dummy gate film on the dummy oxide layer 121; form a gate mask 210 on the dummy gate film; use the gate mask 210 as a mask to pattern the dummy gate film, forming a dummy gate structure 120 on the isolation structure 101 .

It should be noted that after the dummy gate structure 120 is formed, the gate mask 210 on the top of the dummy gate structure 120 remains. The material of the gate mask 210 is silicon nitride, and the gate mask 210 is used to protect the top of the dummy gate structure 120 in the subsequent process. In other embodiments, the material of the gate mask may also be silicon oxynitride, silicon carbide or boron nitride.

With reference to Figures 8 to 12, Figure 8 is a schematic cross-sectional structure based on Figure 6, Figure 9 is a schematic cross-sectional structure based on Figure 7, Figure 10 is a schematic cross-sectional structure based on Figure 8, and Figure 11 is a schematic cross-sectional structure based on Figure 9 Schematic diagram, FIG. 12 is a schematic cross-sectional structure diagram at the position of the sidewall along the secant line perpendicular to the extending direction of the fin (as shown by the C1C2 secant line in FIG. 5 ), and a sidewall 300 is formed on the sidewall of the dummy gate structure 120 (as shown in Figure 11).

The sidewall 300 is used to define the position of the doped epitaxial layer in subsequent processes. The material of the sidewall 300 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 can be a single Layer structure or laminated structure. In this embodiment, the sidewall 300 is a single-layer structure, and the material of the sidewall 300 is silicon nitride.

Specifically, the step of forming the spacer 300 includes: forming a spacer film 125 conformally covering the dummy gate structure 120 (as shown in FIG. 9 ); removing the top of the dummy gate structure 120 and the dummy oxide layer The sidewall film 125 on 121 retains the sidewall film 125 on the sidewall of the dummy gate structure 120 , and the sidewall film 125 remains as the spacer 300 .

As shown in FIG. 10 and FIG. 11 , in this embodiment, after the spacer 300 is formed, the dummy oxide layer 121 exposed by the sidewall 300 is removed, and the dummy oxide layer 121 covered by the sidewall 300 and the dummy gate layer 122 remains. Pseudo oxide layer 121.

It should be noted that, after the spacer 300 is formed, the forming method further includes: using the spacer 300 as a mask, forming lightly doped source and drain in the fins 110 on both sides of the dummy gate structure 120 District (LDD) (not shown). In this embodiment, the substrate 100 is used to form a P-type device, so the dopant ions in the lightly doped source and drain regions are P-type ions. In other embodiments, for example, when the substrate is used to form an N-type device, the dopant ions in the lightly doped source and drain regions are N-type ions.

13 to FIG. 15 in combination, FIG. 13 is a schematic cross-sectional structure based on FIG. 10, FIG. 14 is a schematic cross-sectional structure based on FIG. 11, and FIG. 15 is a schematic cross-sectional structure based on FIG. 14), a first dielectric layer 102 (as shown in FIG. 13 ) is formed on the isolation structure 101 exposed by the dummy gate structure 120 (as shown in FIG. 14 ), and the first dielectric layer 102 exposes the the top of the fin 110 .

The first dielectric layer 102 is used to protect the isolation structure 101 during subsequent etching of the fins 110 on both sides of the dummy gate structure 120 to form grooves, so as to prevent the isolation structure 101 from being etched, thereby The occurrence of gaps caused by the loss of the isolation structure 101 under the sidewall 300 is avoided. In addition, the first dielectric layer 102 is also used as a part of the interlayer dielectric layer (ILD) of the subsequently formed semiconductor structure; correspondingly, through the first dielectric layer 102, there is no need to introduce an additional film layer to protect the isolation structure 101, correspondingly, there is no need to remove an additional film layer after etching the fin portion 110, so the process steps can be simplified and the process cost can be reduced.

The material of the first dielectric layer 102 is an insulating material, such as a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbonitride. In this embodiment, the material of the first dielectric layer 102 is silicon oxide.

It should be noted that the thickness of the first dielectric layer 102 should neither be too small nor too large. If the thickness of the first dielectric layer 102 is too small, it will be difficult to protect the isolation structure 101 in the subsequent etching process; if the thickness of the first dielectric layer 102 is too large, the subsequent The process of etching the fins 110 has adverse effects. Therefore, in this embodiment, the thickness of the first dielectric layer 102 is 5 nm to 50 nm. That is to say, the top of the first dielectric layer 102 is lower than the top of the fin portion 110 ; or, the top of the first dielectric layer 102 is flush with the top of the fin portion 110 .

In this embodiment, in order to increase the volume of the subsequently formed doped epitaxial layer, the top of the first dielectric layer 102 is lower than the top of the remaining fin 110 after subsequent etching. Specifically, the step of forming the first dielectric layer 102 includes: forming a dielectric film on the isolation structure 101, the top of the dielectric film is higher than the top of the fin portion 110; The remaining dielectric film is used as the first dielectric layer 102 , and the top of the first dielectric layer 102 is lower than the top of the fin portion 110 .

The process of etching back part of the thickness of the dielectric film may be a dry etching process, a wet etching process, or a combination of wet etching and dry etching. In this embodiment, the process of etching back part of the thickness of the dielectric film is a dry etching process, so that a better anisotropic etching effect can be ensured, and the etching amount can be better controlled.

It should be noted that, for subsequent formation of the doped epitaxial layer, in this embodiment, before forming the first dielectric layer 102 on the isolation structure 101, the forming method further includes: A mask layer 310 (as shown in FIG. 13 ) is formed thereon. Correspondingly, in the direction along the normal to the surface of the substrate 100 , the first dielectric layer 102 covers part of the sidewall of the mask layer 310 .

The function of the mask layer 310 includes: when subsequently etching the fins 110 of partial thickness on both sides of the dummy gate structure 120, the mask layer 310 is used as an etching mask, so that the subsequently formed grooves and There is a certain distance between the source and drain lightly doped regions formed above to prevent the source and drain lightly doped regions from being completely etched away; and, the mask layer 310 located on the sidewall of the fin 110 can It plays a role of protecting the sidewall of the fin portion 110 and avoids epitaxial growth process on the sidewall of the fin portion 110 when the doped epitaxial layer is subsequently formed.

Specifically, the step of forming the mask layer 310 includes: forming a mask material (not shown) on the top and sidewalls of the fin 110; removing the mask at the groove position on the top of the fin; material, the masking material on the sidewall of the fin portion 110 is retained, and the remaining masking material is used as the masking layer 310 . That is to say, after the mask layer 310 is formed, the top of the mask layer 310 on the sidewall of the fin 110 is flush with the top of the fin 110 .

The process for forming the mask material may be a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the mask material is formed by an atomic layer deposition process. In the step of forming the mask material, the mask material also covers the dummy gate structure 120 and the sidewall 300 , and is also located on the isolation structure 101 . Therefore, in the step of removing the mask material at the groove position on the top of the fin portion 110, the mask material on the top of the dummy gate structure 120 and the isolation structure 101 is also removed, exposing the gate mask 210 and isolation structure 101. Correspondingly, the mask layer 310 is also located on the sidewall surface of the sidewall 300 .

The material of the mask layer 310 may be silicon nitride (SiN), silicon nitride carbide (SiCN), silicon boride nitride (SiBN), silicon oxycarbide oxynitride (SiOCN) or silicon oxynitride (SiON). The material of the mask layer 310 is different from that of the fin portion 110 , and the material of the mask layer 310 is also different from that of the isolation structure 101 . In this embodiment, the material of the mask layer 310 is silicon nitride.

Referring to FIG. 16 and FIG. 17 in conjunction, FIG. 16 is a schematic cross-sectional structure based on FIG. 13, and FIG. 17 is a schematic cross-sectional structure based on FIG. 14. After the first dielectric layer 102 (as shown in FIG. 16) is formed, the Grooves 111 are formed in the fins 110 on both sides of the dummy gate structure 120 .

The groove 111 provides a spatial location for subsequent formation of a doped epitaxial layer.

Specifically, a dry etching process is used to etch the fin portion 110 at a partial thickness on both sides of the dummy gate structure 120 to form a groove 111 in the fin portion 110 .

In this embodiment, anisotropic etching process is used to etch part of the thickness of the fin portion 110, the anisotropic etching process is a reactive ion etching process, and the parameters of the reactive ion etching process include: reaction The gas includes CF ₄ , SF ₆ and Ar, the flow rate of CF ₄ is 50sccm to 100sccm, the flow rate of SF ₆ is 10sccm to 100sccm, the flow rate of Ar is 100sccm to 300sccm, the source power is 50W to 1000W, the bias power is 50W to 250W, the chamber The pressure is 50mTorr to 200mTorr, and the chamber temperature is 20°C to 90°C.

It should be noted that, as shown in FIG. 16 , in this embodiment, in order to increase the volume of the doped epitaxial layer subsequently formed in the groove 111 , while etching the fin portion 110 , the fin portion 110 is also etched. The mask layer 310 on the side wall of the fin 110 is such that after the groove 111 is formed, the remaining mask layer 310 on the side wall of the remaining fin 110 is flush with the top of the fin 110 .

It should also be noted that when etching the fin portion 110, since the first dielectric layer 102 is formed on the isolation structure 101, the first dielectric layer 102 can be used for all the fins during the etching process. The isolation structure 101 plays a protective role, so the isolation structure 101 is not subject to etching loss.

In addition, in order to provide a good interface foundation for the subsequent process of forming the doped epitaxial layer, so as to improve the formation quality of the doped epitaxial layer, after the grooves 111 are formed in the fins 110 on both sides of the dummy gate structure 120, Before forming the doped epitaxial layer, the forming method further includes: performing a cleaning process on the groove 111 . The cleaning process is used not only to remove impurities in the groove 111 , but also to remove a natural oxide layer (not shown) on the surface of the fin 110 .

The first dielectric layer 102 is exposed to the environment of the cleaning process, and the first dielectric layer 102 is used as a part of the subsequent interlayer dielectric layer, so in order to reduce the impact of the cleaning process on the first dielectric layer 102 In this embodiment, the cleaning process is a SiCoNi process, and the main etching gas used in the SiCoNi process is gaseous hydrofluoric acid.

Referring to FIG. 18 and FIG. 19 together, FIG. 18 is a schematic cross-sectional structure based on FIG. 16 , and FIG. 19 is a schematic cross-sectional structure based on FIG. 17 , forming a doped epitaxial layer 130 in the groove 111 (as shown in FIG. 17 ). .

In this embodiment, a selective epitaxial process is used to form a stress layer in the groove 111, and during the process of forming the stress layer, in-situ self-doping of P-type ions is used to form the doped epitaxial layer 130. In other embodiments, after the stress layer is formed in the groove, the stress layer may be doped with P-type ions to form the doped epitaxial layer.

Specifically, the material of the stress layer is Si or SiGe, and the material of the doped epitaxial layer 130 is P-type doped Si or SiGe. The stress layer provides compressive stress for the channel region of the P-type device, thereby improving the carrier mobility of the P-type device. In this embodiment, the material of the doped epitaxial layer 130 is SiGe.

In this embodiment, the top of the doped epitaxial layer 130 is higher than the top of the groove 111 . And due to the characteristics of the selective epitaxial process, the sidewall surface of the doped epitaxial layer 130 higher than the groove 111 has a vertex protruding away from the fin portion 110 . In other embodiments, the top of the doped epitaxial layer may also be flush with the top of the groove.

It should be noted that, in this embodiment, it is described by taking the substrate as an example for forming a P-type device. In another embodiment, for example, when the substrate is used to form an N-type device, in the step of forming a stress layer in the groove, the material of the stress layer is Si or SiC, and the stress layer is N-type The channel region of the device provides tensile stress, thereby improving the carrier mobility of the N-type device; during the process of forming the stress layer, in-situ self-doping of N-type ions to form the doped epitaxial layer, so The material of the doped epitaxial layer is N-type doped Si or SiC; for example, the material of the doped epitaxial layer is SiP.

In other embodiments, when the substrate is used to form P-type devices and N-type devices, that is, when the substrate includes an N-type region and a P-type region, the doped epitaxial layer formed in the aforementioned groove is defined as P type doped epitaxial layer as an example, after forming the P-type doped epitaxial layer, the forming method further includes: on the top and sidewall of the fin portion of the N-type region, the top and sidewall of the dummy gate structure, and the isolation structure An N-region mask layer is formed on the N-region mask layer, and the N-region mask layer is also located on the P-type doped epitaxial layer, the top and sidewall of the fin portion of the P-type region, the top and sidewall of the dummy gate structure of the P-type region, And on the isolation structure of the P-type region; etching the N-region mask layer on the top of the fins on both sides of the dummy gate structure in the N-type region, exposing the tops of the fins on both sides of the dummy gate structure in the N-type region, And also etch the fin part with partial thickness, and form N-region grooves in the fins on both sides of the dummy gate structure in the N-type region; form an N-region stress layer in the N-region groove, and form the N-region stress layer after forming the During the process of the N-region stress layer, in-situ self-doping of N-type ions is used to form the N-type doped epitaxial layer. The material of the N-region stress layer is Si or SiC; the material of the N-type doped epitaxial layer is N-type doped Si or SiC.

Referring to FIG. 20 and FIG. 21 in conjunction, FIG. 20 is a schematic cross-sectional structure based on FIG. 18, and FIG. 21 is a schematic cross-sectional structure based on FIG. 21) to form a second dielectric layer 103 (as shown in FIG. 20 ) on the exposed first dielectric layer 102 (as shown in FIG. 20 ), the second dielectric layer 103 covers the dummy gate structure 120 and exposes the The top of the dummy gate structure 120, and the second dielectric layer 103 and the first dielectric layer 102 form an interlayer dielectric layer (not shown).

In this embodiment, the second dielectric layer 103 and the first dielectric layer 102 are used to form an interlayer dielectric layer (not shown), and the interlayer dielectric layer is used to realize electrical isolation between semiconductor structures, also It is used to define the size and position of the subsequently formed metal gate structure.

Therefore, the material of the second dielectric layer 103 is an insulating material, such as a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbonitride. In this embodiment, in order to improve process compatibility, the material of the second dielectric layer 103 is the same as that of the first dielectric layer 102 , that is, the material of the second dielectric layer 103 is silicon oxide.

Specifically, the step of forming the second dielectric layer 103 includes: forming a dielectric material layer on the first dielectric layer 102 exposed by the dummy gate structure 120, the dielectric material layer covering the dummy gate structure 120; The dielectric material layer higher than the top of the dummy gate structure 120 is removed by mechanical grinding or the like to expose the top of the dummy gate structure 120 , and the remaining dielectric material layer is used as the second dielectric layer 103 .

It should be noted that, the gate mask 210 is formed on the top of the dummy gate structure 120 , so in the step of forming the second dielectric layer 103 , the dielectric material layer higher than the top of the gate mask 210 is removed. In this embodiment, after the second dielectric layer 103 is formed, the top of the second dielectric layer 103 is flush with the top of the gate mask 210 .

Referring to FIGS. 22 to 24 in conjunction, FIG. 22 is a schematic cross-sectional structure based on FIG. 20 , FIG. 23 is a schematic cross-sectional structure based on FIG. 21 , and FIG. 24 is a secant line ( In the schematic cross-sectional structure shown by the C1C2 secant in FIG. 5 ), the dummy gate structure 120 (as shown in FIG. 21 ) is removed, and an opening (not shown) is formed in the interlayer dielectric layer (not shown); A metal layer 222 (as shown in FIG. 23 ) is filled in the opening to form a metal gate junction (not shown).

The metal gate junction is used to control the conduction and disconnection of the channel of the formed semiconductor device.

In this embodiment, in the step of removing the dummy gate structure 120, the dummy oxide layer 121 and the dummy gate layer 122 are removed, and the opening penetrates through the second dielectric layer 103 (as shown in FIG. 22 ) and the first The dielectric layer 102 (as shown in FIG. 22 ) exposes the fins 110 .

It should be noted that a gate mask 210 is formed on the top of the dummy gate structure 120 , so before removing the dummy gate structure 120 , the forming method further includes: removing the gate mask 210 .

It should also be noted that, after removing the dummy gate structure 120, before filling the opening with the metal layer 222, the forming method further includes: forming a gate dielectric layer (not shown in the figure) on the bottom and side walls of the opening. ), the gate dielectric layer is also located on the top of the second dielectric layer 103 . Specifically, the gate dielectric layer includes an interfacial layer (IL, Interfacial Layer) (not shown in the figure) and a high-k gate dielectric layer (not shown in the figure) located on the surface of the interface layer.

The interface layer is formed at the bottom of the opening, and the interface layer provides a good interface basis for forming the high-k gate dielectric layer, thereby improving the quality of the high-k gate dielectric layer and reducing the The interface state density between the layer and the fin portion 110 is avoided, and the adverse effect caused by the direct contact between the high-k gate dielectric layer and the fin portion 110 is avoided. The material of the interface layer is silicon oxide or silicon oxynitride.

The material of the high-k gate dielectric layer is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

Therefore, the step of forming the metal gate junction includes: forming a metal layer 222 on the gate dielectric layer; removing the metal layer 222 higher than the top of the second dielectric layer 103, and also removing The gate dielectric layer on the top of layer 103, the remaining gate dielectric layer and metal layer 222 in the opening are used to form the metal gate junction, and the top of the metal gate junction is connected to the top of the second dielectric layer 103 flush.

In this embodiment, during the process of forming the groove 111 (as shown in FIG. 17 ), the first dielectric layer 102 (as shown in FIG. 16 ) is opposed to the isolation structure 101 (as shown in FIG. 16 ). ) to protect the isolation structure 101 below the side wall 300 (as shown in the dotted line box in FIG. There is a gap generated by the loss of the isolation structure 101; therefore, when the metal layer 222 is filled in the openings in the second dielectric layer 103 and the first dielectric layer 102 (as shown in FIG. 23 ), the metal layer will not appear 222 bridges the doped epitaxial layer 130 (as shown in FIG. 23 ) through the gap, that is, through the solution of the present invention, the doped epitaxial layer 130 and the metal gate structure can be avoided (not shown) bridging occurs, thereby improving the electrical performance and yield of the semiconductor device.

Continuing to refer to Fig. 22 to Fig. 24, Fig. 22 is a schematic cross-sectional structural diagram of a secant line perpendicular to the extending direction of the fin (as shown by the B1B2 secant line in Fig. 5), and Fig. 23 is a secant line along the extending direction of the fin portion (as shown in Fig. 5 24 is a schematic cross-sectional structure diagram along the secant line perpendicular to the fin extension direction (shown by the C1C2 secant line in FIG. 5 ) at the position of the side wall. Correspondingly, the present invention also provides a semiconductor structure, including:

a base, the base includes a substrate 100 and a discrete fin 110 located on the substrate 100; an isolation structure 101, located on the substrate 100 exposed by the fin 110, and the isolation structure 101 covers the fin Part of the sidewall of 110; a metal gate structure (not shown) across the fin 110, the metal gate structure covers part of the top surface and sidewall surface of the fin 110, the metal gate structure Including a metal layer 222 (as shown in FIG. 23 ); sidewalls 300 located on the side walls of the metal gate structure; doped epitaxial layers 130 located in the fins 110 on both sides of the metal gate structure; The interlayer dielectric layer (not shown) on the isolation structure 101 exposed by the metal gate structure, the interlayer dielectric layer includes a first dielectric layer 102 (as shown in FIG. 22 ), and a 102 on the second dielectric layer 103 (as shown in FIG. 22 ), the second dielectric layer 103 covers the metal gate structure and exposes the top of the metal gate structure.

The substrate has a fin field effect transistor, the substrate 100 provides a process platform for forming the fin field effect transistor, and the fin portion is used to provide a channel of the fin field effect transistor. In this embodiment, taking the FinFET as an example as a CMOS device, the substrate has a P-type device. In other embodiments, the substrate has N-type devices; or, the substrate has P-type devices and N-type devices.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-on-insulator substrate. substrate or glass substrate. The material of the substrate 100 can be selected suitable for process requirements or easily integrated.

The material of the fin portion 110 is the same as that of the substrate 100 . In this embodiment, the material of the fin portion 110 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

The isolation structure 101 is used as an isolation structure of a semiconductor device, and is used for isolating adjacent devices, and is also used for isolating adjacent fins 110 . In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

The metal gate junction is used to control the conduction and disconnection of the channel of the semiconductor device.

The metal gate structure includes a metal layer 222 . In this embodiment, the metal gate structure further includes: a gate dielectric layer (not shown) across the fin 110 , the gate dielectric layer covers part of the top surface and sidewall surface of the fin 110 . Correspondingly, the metal layer 222 is located on the gate dielectric layer.

Specifically, the gate dielectric layer includes an interfacial layer (IL, Interfacial Layer) (not shown in the figure) and a high-k gate dielectric layer (not shown in the figure) located on the surface of the interface layer.

The interface layer provides a good interface foundation for forming the high-k gate dielectric layer, thereby improving the quality of the high-k gate dielectric layer and reducing the interface between the high-k gate dielectric layer and the fin portion 110 density of states, and avoid adverse effects caused by direct contact between the high-k gate dielectric layer and the fin portion 110 . The material of the interface layer is silicon oxide or silicon oxynitride.

The material of the high-k gate dielectric layer is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

The sidewall 300 is used to define the position of the doped epitaxial layer 130 . The material of the sidewall 300 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 can be a single Layer structure or laminated structure. In this embodiment, the sidewall 300 is a single-layer structure, and the material of the sidewall 300 is silicon nitride.

The doped epitaxial layer 130 serves as a source region or a drain region of a channel of the semiconductor structure. In this embodiment, the formation process of the doped epitaxial layer 130 is a selective epitaxial process, so the material of the doped epitaxial layer 130 is P-type doped Si or SiGe. In this embodiment, the material of the doped epitaxial layer 130 is SiGe.

In this embodiment, the top of the doped epitaxial layer 130 is higher than the top of the fin portion 110 . And due to the characteristics of the selective epitaxy process, the sidewall surface of the doped epitaxial layer 130 higher than the top of the fin portion 110 has an apex protruding away from the fin portion 110 . In other embodiments, the top of the doped epitaxial layer may also be flush with the top of the fin.

It should be noted that, in this embodiment, the description is made by taking the substrate having a P-type device as an example. In another embodiment, when the substrate has an N-type device, the material of the doped epitaxial layer is N-type doped Si or SiC; for example, the material of the doped epitaxial layer is SiP.

It should also be noted that the semiconductor structure further includes: a mask layer 310 located on the sidewall of the fin 110 (as shown in FIG. 22 ).

During the semiconductor manufacturing process, generally, a dummy gate structure across the fin portion 110 is first formed; the fin portion 110 with a partial thickness on both sides of the dummy gate structure is etched, and the fin portion 110 on both sides of the dummy gate structure is Form a groove in the groove; form the doped epitaxial layer 130 in the groove; after forming the doped epitaxial layer 130, remove the dummy gate structure and fill the metal layer 222 at the position of the dummy gate structure to forming the metal gate structure.

The function of the mask layer 310 includes: when etching the fins 110 of partial thickness on both sides of the dummy gate structure, the mask layer 310 is used as an etching mask for etching the fins 110; The mask layer 310 on the sidewall of the fin 110 can also protect the sidewall of the fin 110 and avoid epitaxial growth on the sidewall of the fin 110 when the doped epitaxial layer 130 is formed. craft. In this embodiment, the mask layer 310 is also located on the sidewall surface of the sidewall 300 .

The material of the mask layer 310 may be silicon nitride (SiN), silicon nitride carbide (SiCN), silicon boride nitride (SiBN), silicon oxycarbide oxynitride (SiOCN) or silicon oxynitride (SiON). The material of the mask layer 310 is different from that of the fin portion 110 , and the material of the mask layer 310 is also different from that of the isolation structure 101 . In this embodiment, the material of the mask layer 310 is silicon nitride.

The interlayer dielectric layer is used to realize electrical isolation between semiconductor structures, and is also used to define the size and position of the metal gate structure. Therefore, the material of the interlayer dielectric layer is an insulating material, such as a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbonitride.

In this embodiment, the material of the first dielectric layer 102 is silicon oxide, and in order to improve process compatibility, the material of the second dielectric layer 103 is the same as that of the first dielectric layer 102, that is, the second dielectric layer 103 The material of the second dielectric layer 103 is also silicon oxide.

According to the above analysis, in the semiconductor manufacturing process, before forming the doped epitaxial layer 130, the fins 110 of the partial thickness on both sides of the dummy gate structure are etched, and the fins on both sides of the dummy gate structure Grooves are formed in 110. The first dielectric layer 102 is used to protect the isolation structure 101 during the process of forming the groove, so as to avoid the isolation under the sidewall 300 (as shown by the dashed box in FIG. 24 ). The structure 101 is subjected to etching loss, so as to avoid gaps under the spacer 300 caused by the loss of the isolation structure 101, thereby preventing the metal layer 222 from bridging with the doped epitaxial layer 130 through the gaps. The problem of bridging between the doped epitaxial layer 130 and the metal gate structure is correspondingly avoided, so that the electrical performance and yield of the semiconductor structure are improved. In addition, through the first dielectric layer 102 , there is no need to introduce an additional film layer to protect the isolation structure 101 , and accordingly there is no need to remove the additional film layer after forming the groove, so the process steps can be simplified and the process cost can be reduced.

It should be noted that the thickness of the first dielectric layer 102 should neither be too small nor too large. If the thickness of the first dielectric layer 102 is too small, it is difficult to protect the isolation structure 101 in the process of etching the fin portion 110; if the thickness of the first dielectric layer 102 is too large, Correspondingly, the process of etching the fin portion 110 will be adversely affected. Therefore, in this embodiment, the thickness of the first dielectric layer 102 is 5 nm to 50 nm.

In this embodiment, the top of the first dielectric layer 102 is lower than the top of the fin portion 110 . In other embodiments, the top of the first dielectric layer may be flush with the top of the fin; or, the top of the first dielectric layer may be higher than the top of the fin.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:

providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate;

forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers part of the side wall of the fin portion;

after the isolation structure is formed, forming a pseudo-gate structure crossing the fin part, wherein the pseudo-gate structure covers part of the top surface and the side wall surface of the fin part;

forming a side wall on the side wall of the pseudo gate structure;

after the side wall is formed, forming a first dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the first dielectric layer is exposed out of the top of the fin part;

after the first dielectric layer is formed, forming grooves in the fin parts on two sides of the pseudo gate structure;

forming a doped epitaxial layer in the groove;

after the doped epitaxial layer is formed, forming a second dielectric layer on the first dielectric layer exposed out of the pseudo gate structure, wherein the second dielectric layer covers the pseudo gate structure and exposes out of the top of the pseudo gate structure, and the second dielectric layer and the first dielectric layer form an interlayer dielectric layer;

removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer;

and filling a metal layer in the opening to form a metal gate structure.

2. The method of claim 1, wherein the first dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

3. The method of claim 1, wherein a top of the first dielectric layer is lower than a top of the fin; or the top of the first dielectric layer is flush with the top of the fin portion.

4. The method of forming a semiconductor structure of claim 1, wherein the first dielectric layer has a thickness of 5nm to 50 nm.

5. The method of forming a semiconductor structure of claim 1, wherein forming the first dielectric layer comprises: forming a dielectric film on the isolation structure, wherein the top of the dielectric film is higher than the top of the fin part;

and etching back the dielectric film with partial thickness, wherein the residual dielectric film is used as the first dielectric layer, and the top of the first dielectric layer is lower than the top of the fin part.

6. The method for forming a semiconductor structure according to claim 5, wherein the step of etching back the dielectric film with a partial thickness is a dry etching step.

7. The method of claim 1, wherein the step of forming the recess in the fin on both sides of the dummy gate structure comprises: and etching the fin parts with partial thickness at two sides of the pseudo-gate structure by adopting a dry etching process, and forming grooves in the fin parts.

8. The method of forming a semiconductor structure of claim 7, wherein the dry etching process is a reactive ion etching process, and the parameters of the reactive ion etching process comprise: the reaction gas comprises CF₄、SF₆And Ar, CF₄The gas flow rate of (1) is 50sccm to 100sccm, SF₆The gas flow of the gas is 10sccm to 100sccm, the gas flow of Ar is 100sccm to 300sccm, the source power is 50W to 1000W, the bias power is 50W to 250W, the chamber pressure is 50mTorr to 200mTorr, and the process temperature is 20 ℃ to 90 ℃.

9. The method of forming a semiconductor structure of claim 1, wherein after forming a recess in the fin on both sides of the dummy gate structure, before forming a doped epitaxial layer in the recess, the method further comprises: and carrying out a cleaning process on the groove.

10. The method of claim 9, wherein the cleaning process is a SiCoNi process, and wherein a main etching gas used in the SiCoNi process is gaseous hydrofluoric acid.

11. The method of claim 1, wherein the substrate is used to form a P-type device, and the step of forming a doped epitaxial layer in the recess is performed by using P-type doped Si or SiGe as the material of the doped epitaxial layer;

or,

the substrate is used for forming an N-type device, and in the step of forming the doped epitaxial layer in the groove, the doped epitaxial layer is made of N-type doped Si or SiC.

12. The method for forming a semiconductor structure according to claim 1, wherein after forming the sidewall spacers on the sidewalls of the dummy gate structure, before forming the first dielectric layer on the isolation structure, the method further comprises: forming a mask layer on the side wall of the fin part;

and in the step of forming grooves in the fin parts at two sides of the pseudo-gate structure, etching the fin parts with partial thicknesses at two sides of the pseudo-gate structure by taking the mask layer as a mask.

13. The method of claim 12, wherein the mask layer is made of silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.

14. A semiconductor structure, comprising:

the base comprises a substrate and a discrete fin part positioned on the substrate;

the isolation structure is positioned on the substrate exposed out of the fin part and covers partial side walls of the fin part;

the metal gate structure stretches across the fin part, covers part of the top surface and the side wall surface of the fin part, and comprises a metal layer;

the side wall is positioned on the side wall of the metal grid structure;

the doped epitaxial layer is positioned in the fin parts at two sides of the metal grid structure;

and the interlayer dielectric layer is positioned on the isolation structure exposed out of the metal grid structure and comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, and the second dielectric layer covers the metal grid structure and exposes out of the top of the metal grid structure.

15. The semiconductor structure of claim 14, wherein the first dielectric layer is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

16. The semiconductor structure of claim 14, wherein the first dielectric layer has a thickness of 5nm to 50 nm.

17. The semiconductor structure of claim 14, wherein the substrate has a P-type device, and the material of the doped epitaxial layer is P-type doped Si or SiGe;

or,

the substrate is provided with an N-type device, and the material of the doped epitaxial layer is N-type doped Si or SiC.

18. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises: and the mask layer is positioned on the side wall of the fin part.

19. The semiconductor structure of claim 18, wherein the mask layer is made of silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.