CN112635324B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate; forming a dummy gate structure on the substrate; forming a first dielectric layer on the substrate, wherein the first dielectric layer exposes the pseudo gate structure, and the surface of the first dielectric layer is lower than or flush with the top surface of the pseudo gate structure; removing the pseudo gate structure, forming a gate opening in the first dielectric layer, and forming a gate structure in the gate opening; removing the first dielectric layer to expose the substrate surfaces at two sides of the gate structure; after the first dielectric layer is removed, forming a stop layer on the substrate, the top surface of the gate structure and the side wall surface; forming a second dielectric layer on the stop layer; and forming plugs in the second dielectric layer, wherein the plugs are positioned between adjacent gate structures. The performance of the formed semiconductor structure is improved.

Description

Semiconductor structure and method of forming the same

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof.

Background Art

Fin FET is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewalls of the fin, and source and drain doping regions in the fin on both sides of the gate structure. Compared with planar metal-oxide semiconductor field effect transistors, fin field effect transistors have stronger short channel suppression capabilities and higher operating currents.

With the further development of semiconductor technology, the size of integrated circuit devices is getting smaller and smaller, and the manufacturing process of traditional fin field effect transistors is also challenged.

Therefore, the performance of the FinFET in the prior art needs to be improved.

Summary of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.

In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a pseudo gate structure on the substrate; forming a first dielectric layer on the substrate, the first dielectric layer exposing the pseudo gate structure, and the surface of the first dielectric layer is lower than or flush with the top surface of the pseudo gate structure; removing the pseudo gate structure, forming a gate opening in the first dielectric layer, and forming a gate structure in the gate opening; removing the first dielectric layer to expose the substrate surface on both sides of the gate structure; after removing the first dielectric layer, forming a stop layer on the substrate, the top surface and the side wall surface of the gate structure; forming a second dielectric layer on the stop layer; forming a plug in the second dielectric layer, the plug is located between adjacent gate structures.

Optionally, the process of removing the first dielectric layer includes an etch-back process.

Optionally, the back etching process includes a reactive ion etching process, a SiCoNi etching process or a Certas etching process.

Optionally, the process of forming the stop layer includes a chemical vapor deposition process or an atomic layer deposition process.

Optionally, the material of the stop layer includes silicon nitride or silicon nitride oxide.

Optionally, the method for forming the plug includes: forming a patterned mask layer on the surface of the second dielectric layer; etching the second dielectric layer using the patterned mask layer as a mask to form an initial plug opening in the second dielectric layer, wherein the initial plug opening exposes a stop layer on the surface of the substrate; removing the stop layer on the surface of the substrate to form a plug opening; and forming a plug in the plug opening.

Optionally, the process of etching the second dielectric layer includes a dry etching process.

Optionally, the process of removing the stop layer includes a dry etching process or a wet etching process.

Optionally, the substrate includes a base and a fin located on the base, the base has a third dielectric layer, the third dielectric layer is located on the side wall of the fin and is lower than the top surface of the fin; the first dielectric layer is located on the surface of the third dielectric layer, and the gate structure spans the fin and is located in the first dielectric layer.

Optionally, the method of removing the first dielectric layer until the substrate surface on both sides of the gate structure is exposed includes: etching a portion of the first dielectric layer until the top surface of the fin on both sides of the gate structure is exposed, and forming a fourth dielectric layer on the third dielectric layer, a portion of the side wall surface of the gate structure, and the side wall surface of the fin.

Optionally, the stop layer is located on the exposed fin surface, the fourth dielectric layer surface, and the top surface and sidewall surface of the gate structure.

Optionally, the gate structure includes a gate dielectric layer, a work function layer located on the gate dielectric layer, and a gate layer located on the work function layer.

Optionally, the method for forming the gate structure includes: forming a gate dielectric material layer, a work function material layer on the gate dielectric material layer, and a gate material layer on the work function material layer in the gate opening; and planarizing the gate material layer, the work function material layer, and the gate dielectric material layer until the surface of the first dielectric layer is exposed to form the gate structure.

Optionally, before removing the dummy gate structure, the method further includes: cutting a portion of the dummy gate structure.

Optionally, the process of removing the dummy gate structure includes a dry etching process or a wet etching process.

Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by any of the above methods.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

In the method for forming a semiconductor structure of the technical solution of the present invention, the first dielectric layer is first removed until the substrate surfaces on both sides of the gate structure are exposed, and then a stop layer is formed on the substrate, the top surface and the side wall surface of the gate structure, a second dielectric layer is formed on the stop layer, and a plug is formed in the second dielectric layer. On the one hand, the stop layer on the top surface and the side wall surface of the gate structure protects the gate structure, so that in the process of forming the plug, the etching of the second dielectric layer can automatically stop on the surface of the stop layer, so that the position of the plug formed subsequently can be self-aligned, and will not cause damage to the gate structure, which is beneficial to the improvement of the performance of the semiconductor structure. On the other hand, after the gate structure is formed, the first dielectric layer is removed, and then a stop layer is formed on the top surface and the side wall surface of the gate structure and the substrate, so that the height of the pseudo gate structure formed first is reduced, so that the depth and width of the gate opening formed when the pseudo gate structure is removed is relatively small, thereby reducing the process difficulty of forming the gate structure in the gate opening.

Furthermore, the stop layer is located on the fin surface and the fourth dielectric layer surface, so that the formed plug is located on the fin surface and the fourth dielectric layer surface flush with the fin surface, thereby reducing the capacitance between the plug and the gate structure, thereby improving the performance of the semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 6 are schematic cross-sectional views of a semiconductor structure forming process in one embodiment;

7 to 18 are schematic cross-sectional views of the formation process of the semiconductor structure according to the embodiment of the present invention.

DETAILED DESCRIPTION

As described in the background art, the performance of FinFETs in the prior art needs to be improved.

1 to 6 are schematic cross-sectional views of a semiconductor structure forming process according to an embodiment.

Please refer to Figure 1, a substrate 100 is provided, the substrate 100 has a fin (not shown), the substrate has a dummy gate structure 101, and the dummy gate structure 101 spans the fin; source and drain doping regions (not shown) are formed in the fins on both sides of the dummy gate structure 101; a stop layer 102 is formed on the sidewall of the dummy gate structure 101 and the surface of the substrate 100; an isolation layer 103 is formed on the stop layer 102 and the substrate 100, and the dummy gate structure 101 is located in the isolation layer 103.

Please refer to FIG. 2 , the dummy gate structure 101 is cut; after cutting the dummy gate structure 101 , the dummy gate structure 101 is removed, a gate opening (not shown) is formed in the isolation layer 103 ; and an initial gate structure 104 is formed in the gate opening.

3 , a portion of the initial gate structure 104 is removed to form a gate structure 108 , a groove (not shown) is formed on the top of the gate structure 108 and in the isolation layer 103 ; and a protection layer 105 is formed in the groove.

Please refer to Figures 4, 5 and 6, Figure 4 is a schematic diagram of the structure of Figure 6 along the section line AA', and Figure 5 is a schematic diagram of the structure of Figure 6 along the section line BB'. A source plug 106 and a drain plug 107 are formed in the isolation layer 103, and the source plug 106 is electrically connected to the source doping region, and the drain plug 107 is electrically connected to the drain doping region.

During the formation of the semiconductor structure, on the one hand, in order to prevent the lateral etching when forming the openings of the source plug 106 and the drain plug 107 in the isolation layer 103 from damaging the gate structure 108, a stop layer 102 is formed on the sidewall of the gate structure 108 and a protective layer 105 is formed on the top of the gate structure 108 to protect the gate structure 108. The protective layer 105 is located on the top of the gate structure 108, and a portion of the initial gate structure 104 needs to be etched. In order to ensure the performance of the formed semiconductor structure, the gate structure 108 needs a certain height, so it is necessary to increase the preset height of the initial gate structure 104. The preset height of the initial gate structure 104 is the height of the dummy gate structure 101. If the height of the dummy gate structure 101 is high, it is more difficult to cut the dummy gate structure 101, and it is easy to cause the dummy gate structure 101 at the cutting position to be not removed cleanly, resulting in a short circuit of the semiconductor structure. At the same time, it is difficult to cut, resulting in poor uniformity of the size of the formed device, which affects the performance of the semiconductor structure.

On the other hand, if the protection layer 105 and the stop layer 102 are not formed, the accuracy required when forming the source plug 106 and the drain plug 107 is very high. If the positions of the source plug 106 and the drain plug 107 are offset, the source plug 106 and the drain plug 107 are prone to leakage and short circuit with the gate structure 108, thereby affecting the performance of the semiconductor structure.

On the other hand, the source plug 106 and the drain plug 107 also span the fin (as shown in FIG. 6 ), a portion of the plugs is located on the fin (as shown in FIG. 4 ), and a portion of the plugs is located on the isolation layer 103 on the sidewall of the fin. During the formation of the source plug 106 and the drain plug 107, it is necessary to first form a plug opening in the isolation layer 103. In order to ensure that the plug opening can completely expose the surface of the source and drain doped regions, the process of etching the isolation layer 103 will over-etch to ensure that the isolation layer 103 and the protective layer 102 on the surface of the source and drain doped regions are completely removed. Therefore, when the surface of the source and drain doped regions is completely exposed, the etching depth of the isolation layer 103 on the sidewall of the fin is greater than the etching depth of the isolation layer 103 on the surface of the source and drain doped regions. Therefore, a portion of the plug located on the fin has a smaller height, and a portion of the plug located on the isolation layer 103 on the sidewall of the fin has a higher height, so that parasitic capacitance is generated between the plug and the gate structure 104, resulting in greater power consumption of the semiconductor structure, which affects the performance of the semiconductor structure.

In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein the first dielectric layer is first removed, and then a stop layer is formed on the top surface and side wall surface of the gate structure and the substrate, a second dielectric layer is formed on the stop layer, and a plug is formed in the second dielectric layer. The stop layer on the top surface and side wall surface of the gate structure protects the gate structure, so that in the process of forming the plug, the etching of the second dielectric layer can automatically stop on the surface of the stop layer, so that the position of the plug formed subsequently can be self-aligned, and the gate structure will not be damaged, which is beneficial to the improvement of the performance of the semiconductor structure.

In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

7 to 18 are schematic cross-sectional views of the formation process of the semiconductor structure according to the embodiment of the present invention.

Please refer to Figures 7 and 8, Figure 8 is a schematic diagram of the structure of Figure 7 in the direction of section line DD', and Figure 7 is a schematic diagram of the structure of Figure 8 in the direction of section line CC', and a substrate is provided.

The substrate includes a base 200 and a fin 300 located on the base 200 .

The material of the substrate includes silicon, silicon germanium, germanium, silicon on insulator or germanium on insulator. In this embodiment, the material of the substrate includes silicon.

In other embodiments, the substrate is a planar substrate.

A third dielectric layer 201 is formed on the substrate. The third dielectric layer 201 is located on the sidewall of the fin 300 and is lower than the top surface of the fin 300 .

The method for forming the third dielectric layer 201 includes: forming an initial third dielectric material layer on the substrate; planarizing the initial third dielectric material layer until the top surface of the fin 300 is exposed to form a third dielectric material layer; and etching back the third dielectric material layer so that the third dielectric layer 201 is lower than the top surface of the fin 300.

The material of the third dielectric layer 201 includes silicon oxide or silicon nitride; the process of forming the third dielectric layer 201 includes a chemical vapor deposition process or an atomic layer deposition process; the process of planarizing the initial third dielectric material layer includes a chemical mechanical polishing process or an etching process.

In this embodiment, the material of the third dielectric layer 201 includes silicon oxide; the process of forming the third dielectric layer 201 includes a chemical vapor deposition process; and the process of planarizing the initial third dielectric material layer includes a chemical mechanical polishing process.

In other embodiments, the third dielectric layer 201 may not be formed.

Please refer to FIG. 9 , which is a schematic cross-sectional structure diagram based on FIG. 8 , in which a dummy gate structure is formed on the substrate.

In this embodiment, the dummy gate structure spans over the fin 300 , and the dummy gate structure is located on a portion of the sidewall surface and a portion of the bottom surface of the fin 300 .

In this embodiment, the dummy gate structure includes a dummy gate dielectric layer (not shown) and a dummy gate layer 202 located on the dummy gate dielectric layer.

The method for forming the pseudo gate structure includes: forming a pseudo gate dielectric material layer (not shown) on the substrate; forming a pseudo gate material layer (not shown) on the pseudo gate dielectric material layer; forming a first mask layer (not shown) on the pseudo gate material layer, wherein the first mask layer exposes the surface of the pseudo gate material layer; etching the pseudo gate material layer and the pseudo gate dielectric material layer using the first mask layer as a mask until the substrate surface is exposed, thereby forming the pseudo gate structure on the substrate.

The material of the pseudo gate dielectric layer includes a low-K (K less than 3.9) material; the material of the pseudo gate layer 202 includes polysilicon; the process of forming the pseudo gate dielectric material layer includes an atomic layer deposition process or a chemical vapor deposition process; the process of forming the pseudo gate material layer includes a physical vapor deposition process or an epitaxial growth process; the material of the first mask layer includes a photoresist or a hard mask material, and the hard mask material includes silicon oxide or silicon nitride.

In this embodiment, the material of the pseudo gate dielectric layer includes silicon oxide; the material of the pseudo gate layer 202 includes polysilicon; the process of forming the pseudo gate dielectric material layer includes an atomic layer deposition process; the process of forming the pseudo gate material layer includes a physical vapor deposition process; and the material of the first mask layer includes photoresist.

After the dummy gate structure is formed, a spacer 203 is formed on the sidewall of the dummy gate structure.

The method for forming the sidewall 203 includes: forming a sidewall material layer (not shown) on the substrate, the sidewall surface and the top surface of the dummy gate structure; etching back the sidewall material layer until the top surface of the dummy gate structure is exposed, and forming a sidewall 203 on the sidewall of the dummy gate structure.

The material of the sidewall spacer 203 includes silicon nitride, silicon oxide or silicon oxynitride; the process of forming the sidewall material layer includes atomic layer deposition process or chemical vapor deposition process.

In this embodiment, the material of the sidewall 203 includes silicon nitride, which has a dense structure and can effectively electrically isolate the gate structure; the process of forming the sidewall material layer includes a chemical vapor deposition process, which can quickly form a dense sidewall material layer.

Please continue to refer to FIG. 9 . After the spacer 203 is formed, a first dielectric layer 204 is formed on the substrate. The first dielectric layer 204 exposes the dummy gate structure, and the surface of the first dielectric layer 204 is lower than or flush with the top surface of the dummy gate structure.

In this embodiment, the surface of the first dielectric layer 204 is flush with the top surface of the dummy gate structure.

The method for forming the first dielectric layer 204 includes: forming a dielectric material layer (not shown) on the substrate; and planarizing the dielectric material layer until the top surface of the dummy gate structure is exposed to form the first dielectric layer 204 .

The first dielectric layer 204 is used to electrically isolate the gate structure to be formed subsequently from other structures. The material of the first dielectric layer 204 includes a low-K material, and the low-K material includes silicon oxide or silicon nitride; the process of forming the dielectric material layer includes an atomic layer deposition process or a chemical vapor deposition process; and the process of planarizing the dielectric material layer includes a chemical mechanical polishing process or an etching process.

In this embodiment, the material of the first dielectric layer 204 includes silicon oxide; the process of forming the dielectric material layer includes a chemical vapor deposition process; and the process of planarizing the dielectric material layer includes a chemical mechanical polishing process.

Please refer to Figures 10 and 11. Figure 11 is a top view of Figure 10, and Figure 10 is a structural schematic diagram of Figure 11 in the direction of section line HH'. After the first dielectric layer 204 is formed, part of the pseudo gate structure is cut to form a groove (not shown) in the first dielectric layer 204, and an isolation structure 205 is formed in the groove.

Part of the dummy gate structure is cut to separate the dummy gate structure, so that the gate structure formed subsequently can form a semiconductor structure with different functions, so that the functional diversity of the semiconductor device on the same substrate is met.

After the gate structure is formed, it is necessary to remove the first dielectric layer first, and then form a stop layer on the top surface and side wall surface of the gate structure. The process of cutting part of the dummy gate structure is before the process of forming the stop layer, so the dummy gate structure does not need a high height. Therefore, when cutting part of the dummy gate structure, the removal process is less difficult and the dummy gate structure is easy to remove.

The method for cutting part of the dummy gate structure includes: forming a second mask layer (not shown) on the first dielectric layer 204, the second mask layer exposing part of the surface of the dummy gate structure; using the second mask layer as a mask, etching the dummy gate structure until the substrate surface is exposed, and forming a groove (not shown) in the first dielectric layer 204; forming an isolation material layer (not shown) in the groove and on the substrate; flattening the isolation material layer until the top surface of the dummy gate structure is exposed, and forming an isolation structure 205 in the groove.

The isolation structure 205 is used to electrically isolate the pseudo gate structure after cutting, so that the functions of the gate structure formed subsequently can be independent of each other without interference. The material of the isolation structure 205 includes silicon oxide or silicon nitride; the process of forming the isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process; the process of etching the pseudo gate structure includes a dry etching process or a wet etching process; the process of flattening the isolation material layer includes a chemical mechanical polishing process or a back etching process.

In this embodiment, the material of the isolation structure 205 includes silicon oxide; the process of forming the isolation material layer includes a chemical vapor deposition process, and the chemical vapor deposition process can quickly form an isolation material layer with a thicker thickness and a dense structure; the process of etching the pseudo gate structure includes a dry etching process, and the dry etching process can form a groove sidewall with good morphology to avoid affecting the dimensional accuracy of the subsequently formed gate structure; the process of flattening the isolation material layer includes a chemical mechanical polishing process.

Please refer to FIG. 12 , which is a schematic diagram of the structure based on FIG. 10 . After cutting part of the dummy gate structure, the dummy gate structure is removed, and a gate opening (not shown) is formed in the first dielectric layer 204 ; a gate structure is formed in the gate opening.

The gate structure includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate layer 206 located on the work function layer.

The method for forming the gate structure includes: forming a gate dielectric material layer (not shown) in the gate opening, a work function material layer (not shown) located on the gate dielectric material layer, and a gate material layer (not shown) located on the work function material layer; and planarizing the gate material layer, the work function material layer, and the gate dielectric material layer until the surface of the first dielectric layer 204 is exposed to form the gate structure.

The material of the gate dielectric layer includes a high-K (greater than 3.9) material, and the high-K material includes hafnium oxide or aluminum oxide; the process for forming the gate dielectric material layer includes a chemical deposition process, an atomic layer deposition process or an in-situ water vapor generation process; the material of the work function layer includes tantalum nitride, titanium aluminum or titanium nitride; the process for forming the work function material layer includes a chemical vapor deposition process or an atomic layer deposition process; the material of the gate layer 205 includes a metal, and the metal includes copper or tungsten; the process for forming the gate material layer includes a physical vapor deposition process or an electroplating process; the process for planarizing the gate material layer, the work function material layer and the gate dielectric material layer includes a chemical mechanical polishing process or an etching back process.

In this embodiment, the material of the gate dielectric layer includes hafnium oxide, and the process of forming the gate dielectric material layer includes an atomic layer deposition process, which can form a gate dielectric material layer with a dense structure and a thin thickness; the process of forming the work function material layer includes an atomic layer deposition process; the process of forming the gate material layer includes a physical vapor deposition process; and the process of planarizing the gate material layer, the work function material layer and the gate dielectric material layer includes a chemical mechanical polishing process.

Please refer to Figures 13 and 14, Figure 13 is a schematic diagram of the structure of Figure 14 in the direction of section line EE', and Figure 14 is a schematic diagram of the structure of Figure 13 in the direction of section line FF'. A portion of the first dielectric layer 204 is removed until the fin surfaces on both sides of the gate structure are exposed, and a fourth dielectric layer 207 is formed on the third dielectric layer 201, the side wall surfaces of the gate structure, and the side wall surfaces of the fins.

The difference between the surface of the fourth dielectric layer 207 and the top surface of the fin 300 ranges from 0 to 100 angstroms. If the surface of the fourth dielectric layer 207 is lower than the top surface of the fin 300, the etching process may damage the surface of the fin, which is not conducive to improving the performance of the semiconductor structure; if the surface of the fourth dielectric layer 207 is too much higher than the top surface of the fin 300, the etching process cannot expose the surface of the fin, and a stop layer cannot be formed on the surface of the fin.

In this embodiment, the surface of the fourth dielectric layer 207 is flush with the top surface of the fin 300. In other embodiments, the surface of the fourth dielectric layer is slightly higher than the top surface of the fin.

A portion of the first dielectric layer 204 is removed until the fin surfaces on both sides of the gate structure are exposed, so as to provide structural support for the subsequent formation of a stop layer on the substrate, the fourth dielectric layer 207, and the top surface and side wall surface of the gate structure, so as to form a second dielectric layer on the stop layer, and the etching process when forming a plug in the second dielectric layer can automatically stop on the stop layer surface, so that the position of the plug formed subsequently can be self-aligned, and the stop layer on the top surface and side wall surface of the gate structure protects the gate structure and does not cause damage to the gate structure, which is beneficial to the improvement of the performance of the semiconductor structure; at the same time, the formed stop layer is located on the fin surface and the fourth dielectric layer surface, so that the formed plug is located on the fin surface and the fourth dielectric layer surface flush with the fin surface, thereby reducing the capacitance between the plug and the gate structure, thereby improving the performance of the semiconductor structure.

In this embodiment, the process of removing part of the first dielectric layer 204 includes an etch-back process. The etch-back process includes a reactive ion etching process, a SiCoNi etching process or a Certas etching process. The etch-back process has a relatively large etching selectivity for the fin and the gate structure, so that the fin and the gate structure can be less damaged while removing part of the first dielectric layer 204, and at the same time, the surface of the formed fourth dielectric layer is ensured to be flat, which is conducive to the formation of a subsequent stop layer.

The Certas etching process includes remote dry etching and a first in-situ annealing after the remote dry etching; the parameters of the remote dry etching include: the gases used include _NH3 and HF, the flow rate of _NH3 is 200sccm~500sccm, the gas flow rate of HF is 20sccm~200sccm, the chamber pressure is 0.1torr~760torr, and the temperature is -40 degrees Celsius to 25 degrees Celsius; the parameters of the first in-situ annealing include: the temperature is 60 degrees Celsius to 100 degrees Celsius, and the chamber pressure is 0.1torr~760torr.

The SiCoNi etching process includes remote plasma etching and a second in-situ annealing performed after the remote plasma etching; the parameters of the remote plasma etching include: the gases used include _NH3 and _NF3 , the flow rate of _NH3 is 200sccm~500sccm, the gas flow rate of _NF3 is 20sccm~200sccm, the source RF power is 50 watts~2000 watts, the bias voltage is 30 volts~500 volts, the chamber pressure is 0.1torr~760torr, and the temperature is -40 degrees Celsius to 25 degrees Celsius; the parameters of the second in-situ annealing include: the temperature is 60 degrees Celsius~100 degrees Celsius, and the chamber pressure is 0.1torr~760torr.

The parameters of the reactive ion etching process include: the gases used include C ₄ F ₆ and O ₂ or C ₄ F ₈ and O ₂ , the flow rate of C ₄ F ₆ or C ₄ F ₈ is 10 sccm to 20 sccm, the flow rate of O ₂ is 8 sccm to 15 sccm, the source RF power is 0 watt to 100 watts, the bias voltage is 800 volts to 1200 volts, and the chamber pressure is 10 mtorr to 20 mtorr.

In other embodiments, the entire first dielectric layer is removed.

Please refer to Figures 15 and 16, Figure 15 is a schematic diagram of the structure of Figure 16 in the direction of section line KK', and Figure 16 is a schematic diagram of the structure of Figure 15 in the direction of section line JJ'. A stop layer 208 is formed on the surface of the exposed fin 300, the surface of the fourth dielectric layer 207, and the top surface and side wall surface of the gate structure.

The stop layer 208 protects the gate structure, so that in the subsequent process of forming the plug, when etching the formed second dielectric layer, it can stop on the surface of the stop layer 208, so that the formed plug position can be self-aligned and will not cause damage to the gate structure; at the same time, first remove a portion of the first dielectric layer 204, and then form a stop layer on the top surface and side wall surface of the gate structure and the fourth dielectric layer 207, so that no additional barrier layer is required to be formed on the top of the pseudo gate structure to protect the top of the pseudo gate structure, so that the height of the initially formed pseudo gate structure does not need to be too high, and the thickness of the first dielectric layer formed based on the pseudo gate structure does not need to be too thick, so that the gate opening formed in the first dielectric layer when removing the pseudo gate structure The depth-width ratio of the opening is relatively small, which reduces the process difficulty of forming a gate structure in the gate opening; at the same time, the stop layer 208 is located on the surface of the fourth dielectric layer 207, and when the initial plug opening is subsequently formed on the surface of the fin and the surface of the fourth dielectric layer, the initial plug opening located on the surface of the fourth dielectric layer 207 stops on the stop layer 208, so that the depth-width ratio of the plug opening located on the fourth dielectric layer 207 is relatively small, which is conducive to the subsequent formation of the plug; on the other hand, the stop layer 208 is located on the surface of the fin and the surface of the fourth dielectric layer 207, so that the formed plug is located on the surface of the fin and the surface of the fourth dielectric layer 207, thereby reducing the parasitic capacitance between the plug and the gate structure, thereby improving the performance of the semiconductor structure.

The material of the stop layer 208 is different from the material of the fourth dielectric layer 207, and the material of the stop layer 208 is different from the material of the second dielectric layer formed subsequently, so that when the plug is formed subsequently, the process of etching the second dielectric layer can stop at the surface of the stop layer 208. The material of the stop layer 208 includes silicon nitride or silicon oxynitride; the process of forming the stop layer 208 includes a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, the material of the stop layer 208 includes silicon nitride, and the silicon nitride has a high etching selectivity ratio with the subsequently formed second dielectric layer, so that the etching process for forming the plug can stop precisely on the surface of the stop layer 208; the process for forming the stop layer 208 includes an atomic layer deposition process, and the atomic layer deposition process can form a stop layer 208 with a dense structure and uniform thickness.

In this embodiment, the thickness of the stop layer 208 ranges from 100 angstroms to 300 angstroms. If the thickness of the stop layer 208 is too small, the stop layer 208 serves to stop the etching in the process of forming the plug; if the thickness of the stop layer 208 is too thick, when the plug is subsequently formed on the surface of the fin, part of the stop layer on the surface of the fin needs to be removed, and the process of removing the stop layer needs to increase the conditions. At the same time, the depth and width of the formed plug opening will be relatively large, which is not conducive to the filling of the plug material.

Please refer to Figures 17 and 18, Figure 17 is a schematic diagram of the structure of Figure 18 in the direction of section line GG', and Figure 18 is a schematic diagram of the structure of Figure 17 in the direction of section line II'. A second dielectric layer 209 is formed on the stop layer 208.

The method for forming the second dielectric layer 209 includes: forming a dielectric material layer (not shown) on the stop layer 208 ; and planarizing the dielectric material layer to form the second dielectric layer 209 .

The second dielectric layer 209 is used to provide structural support for the plugs subsequently formed in the second dielectric layer 209, and to electrically isolate the gate structure, the plugs and other semiconductor structures. The material of the second dielectric layer 209 includes silicon oxide or silicon nitride; the process of forming the second dielectric layer 209 includes an atomic layer deposition process or a chemical vapor deposition process; the process of planarizing the second dielectric material layer includes a chemical mechanical polishing process or an etch-back process.

In this embodiment, the material of the second dielectric layer 209 includes silicon oxide; the process of forming the second dielectric layer 209 includes a chemical vapor deposition process, and the chemical vapor deposition process can quickly form a second dielectric layer 209 with a relatively thick thickness and a dense structure; the process of planarizing the second dielectric material layer includes a chemical mechanical polishing process.

Continuing to refer to FIG. 17 and FIG. 18 , a plug 210 is formed in the second dielectric layer 209 , and the plug 210 is located between adjacent gate structures.

The plug 210 is used to make electrical connections between semiconductor structures.

The method for forming the plug 210 includes: forming a patterned mask layer (not shown) on the surface of the second dielectric layer 209; etching the second dielectric layer 209 using the patterned mask layer as a mask to form an initial plug opening (not shown) in the second dielectric layer 209, wherein the initial plug opening exposes the stop layer 208 on the surface of the fin; removing the stop layer 208 on the surface of the fin to form a plug opening (not shown); and forming the plug 210 in the plug opening.

The stop layer 208 on the top surface and the sidewall surface of the gate structure protects the gate structure, so that in the process of forming the plug, the process of etching the second dielectric layer 209 can be stopped on the surface of the stop layer 208, so that the position of the formed plug 210 can be self-aligned and will not cause damage to the gate structure; at the same time, the stop layer 208 is located on the surface of the fourth dielectric layer 207, and when the plug opening is formed on the surface of the fin and the surface of the fourth dielectric layer 207, the plug opening located on the surface of the fourth dielectric layer 207 stops on the stop layer 208, so that the depth and width of the plug opening located on the fourth dielectric layer 207 are relatively small, which is conducive to the filling of the plug material; on the other hand, the stop layer 208 is located on the surface of the fin and the surface of the fourth dielectric layer 207, so that the formed plug 210 is located on the surface of the fin and the surface of the fourth dielectric layer 207 flush with the fin surface, so that the parasitic capacitance between the plug 210 and the gate structure is reduced, thereby improving the performance of the semiconductor structure.

The process of etching the second dielectric layer 209 includes a dry etching process or a wet etching process; the process of removing the stop layer 208 includes a dry etching process or a wet etching process; the material of the plug 210 includes metal, and the metal includes copper or tungsten.

In this embodiment, the process of etching the second dielectric layer 209 includes a dry etching process, and the dry etching process can prevent lateral etching from damaging the gate structure; the process of removing the stop layer 208 includes a dry etching process; and the material of the plug 210 includes tungsten.

At this point, a semiconductor structure is formed, and the performance of the semiconductor structure is improved.

Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to FIG. 17 and FIG. 18, including:

A substrate, the substrate comprising a base 200 and a fin 300 located on the base 200;

A gate structure 206 located on the substrate, wherein the gate structure 206 spans over the fin 300;

A third dielectric layer 201 and a fourth dielectric layer 207 located on the sidewalls of the fin, wherein the fourth dielectric layer 207 is flush with the top surface of the fin 300;

a stop layer 208 located on the fourth dielectric layer 207;

A second dielectric layer 209 located on the stop layer 208;

The plug 210 is located on the surface of the fin 300 and in the second dielectric layer 209 .

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate, wherein the substrate comprises a base and a fin part positioned on the base;

forming a dummy gate structure on the substrate;

Forming a first dielectric layer on the substrate, wherein the first dielectric layer exposes the pseudo gate structure, and the surface of the first dielectric layer is lower than or flush with the top surface of the pseudo gate structure;

Removing the pseudo gate structure, forming a gate opening in the first dielectric layer, and forming a gate structure in the gate opening, wherein the gate structure spans across the fin portion;

Removing part of the first dielectric layer until the top surfaces of the fin parts on two sides of the gate structure are exposed, and forming a fourth dielectric layer on the substrate, the side wall surfaces of the gate structure and the side wall surfaces of the fin parts, wherein the fourth dielectric layer is flush with the top surfaces of the fin parts;

after the first dielectric layer is removed, forming a stop layer on the substrate, the top surface of the gate structure and the surface of the side wall, wherein the stop layer is also positioned on the exposed surface of the fin part and the surface of the fourth dielectric layer;

Forming a second dielectric layer on the stop layer;

and forming plugs in the second dielectric layer, wherein the plugs are positioned between adjacent gate structures.

2. The method of forming a semiconductor structure of claim 1, wherein removing the first dielectric layer comprises an etch back process.

3. The method of forming a semiconductor structure of claim 2, wherein the etch-back process comprises a reactive ion etching process, a SiCoNi etching process, or a Certas etching process.

4. The method of forming a semiconductor structure of claim 1, wherein the process of forming the stop layer comprises a chemical vapor deposition process or an atomic layer deposition process.

5. The method of forming a semiconductor structure of claim 1, wherein the material of the stop layer comprises silicon nitride or silicon oxynitride.

6. The method of forming a semiconductor structure of claim 1, wherein the method of forming a plug comprises: forming a patterned mask layer on the surface of the second dielectric layer; etching the second dielectric layer by taking the patterned mask layer as a mask, and forming an initial plug opening in the second dielectric layer, wherein the initial plug opening exposes the stop layer on the surface of the substrate; removing the stop layer on the surface of the substrate to form a plug opening; a plug is formed within the plug opening.

7. The method of forming a semiconductor structure of claim 6, wherein the process of etching the second dielectric layer comprises a dry etching process.

8. The method of forming a semiconductor structure of claim 6, wherein the process of removing the stop layer comprises a dry etching process or a wet etching process.

9. The method of claim 1, wherein a third dielectric layer is provided on the substrate, the third dielectric layer being located on the fin sidewall and below the fin top surface; the first dielectric layer is positioned on the surface of the third dielectric layer.

10. The method of forming a semiconductor structure of claim 9, wherein removing the first dielectric layer until substrate surfaces on both sides of the gate structure are exposed comprises: etching part of the first dielectric layer until the top surfaces of the fin parts on two sides of the gate structure are exposed, and forming a fourth dielectric layer on the third dielectric layer, the side wall surfaces of the gate structure and the side wall surfaces of the fin parts.

11. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer, a work function layer on the gate dielectric layer, and a gate layer on the work function layer.

12. The method of forming a semiconductor structure of claim 11, wherein the method of forming a gate structure comprises: forming a gate dielectric material layer, a work function material layer positioned on the gate dielectric material layer and a gate material layer positioned on the work function material layer in the gate opening; and flattening the gate material layer, the work function material layer and the gate dielectric material layer until the surface of the first dielectric layer is exposed, so as to form the gate structure.

13. The method of forming a semiconductor structure of claim 12, further comprising, prior to removing the dummy gate structure: and cutting part of the pseudo gate structure.

14. The method of forming a semiconductor structure of claim 1, wherein the process of removing the dummy gate structure comprises a dry etching process or a wet etching process.

15. A semiconductor structure formed by the method of any one of claims 1 to 14.