CN107170685B - Method for forming fin type transistor - Google Patents

Abstract

A method for forming a fin transistor, comprising: providing a substrate including an N-type core region and a P-type core region, the surface of the substrate having a fin and an isolation layer; on the fin side of the N-type core region and the P-type core region A first gate oxide layer is formed on the wall and the top surface; a dummy gate layer is formed on the surface of the isolation layer and the first gate oxide layer respectively across the fins of the N-type core region and the P-type core region; a dielectric is formed on the isolation layer and the fins layer, the dielectric layer exposes the top of the dummy gate layer; the dummy gate layer is removed, a first trench is formed in the dielectric layer of the N-type core region, and a second trench is formed in the dielectric layer of the P-type core region; the first trench is removed A first gate oxide layer at the bottom of the trench; a second gate oxide layer is formed on the sidewalls and top surface of the fin exposed in the N-type core region; a first gate oxide layer that fills the first trench is formed on the surface of the second gate oxide layer structure; a second gate structure filled with the second trench is formed on the surface of the first gate oxide layer. The formed fin transistor has improved performance.

Description

Method of forming a fin transistor

technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a fin transistor.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase in the component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter, and the traditional planar transistors have the ability to control the channel current. become weaker, resulting in short channel effect and leakage current, which ultimately affects the electrical performance of semiconductor devices.

In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fin field effect transistor (Fin FET), which is a common multi-gate device. The structure of the fin field effect transistor includes: a fin and a dielectric layer located on the surface of the semiconductor substrate, the dielectric layer covers part of the sidewall of the fin, and the surface of the dielectric layer is lower than the top of the fin; and gate structures on the top and sidewall surfaces of the fins; source and drain regions within the fins on both sides of the gate structures.

However, as the density and size of semiconductor devices are increased, the performance and reliability of the formed fin field effect transistors are degraded.

SUMMARY OF THE INVENTION

The problem to be solved by the present invention is to provide a method for forming a fin transistor with improved performance of the formed fin transistor.

In order to solve the above problems, the present invention provides a method for forming a fin transistor, including: providing a substrate, the substrate includes an N-type core region and a P-type core region, and the N-type core region and the P-type core region have The surfaces of the substrates respectively have fins, the surfaces of the substrates have isolation layers, the isolation layers cover part of the sidewalls of the fins, and the surfaces of the isolation layers are lower than the top surfaces of the fins; using the first The oxidation process forms a first gate oxide layer on the sidewalls and top surfaces of the fins of the N-type core region and the P-type core region; and forms a first gate oxide layer on the surface of the isolation layer and the first gate oxide layer respectively across the N-type core region A dummy gate layer of the fins in the core region and the P-type core region, the dummy gate layer covers part of the sidewalls and the top of the fins; a dielectric layer is formed on the isolation layer and the fins, and the dielectric layer covers the dummy the sidewall of the gate layer, and the dielectric layer exposes the top of the dummy gate layer; the dummy gate layer is removed, a first trench is formed in the dielectric layer of the N-type core region, and a first trench is formed in the P-type core region A second trench is formed in the dielectric layer of the region, and the first trench and the second trench expose the first gate oxide layer; the first gate oxide layer at the bottom of the first trench is removed, and the N-type oxide layer is exposed the sidewalls and top surface of the fins of the core region; a second gate oxide layer is formed on the sidewalls and top surfaces of the fins exposed in the N-type core region by a second oxidation process, and the equivalent of the second gate oxide layer is The thickness of the oxide layer is less than the equivalent thickness of the oxide layer of the first gate oxide layer; a first gate structure filled with the first trench is formed on the surface of the first gate oxide layer; on the surface of the second gate oxide layer forming a second gate structure filling the second trench.

Optionally, the first oxidation process is an in-situ steam generation process.

Optionally, the thickness of the first gate oxide layer is 5 angstroms to 15 angstroms.

Optionally, the second oxidation process is a chemical oxidation process.

Optionally, the thickness of the second gate oxide layer is 5 angstroms to 15 angstroms.

Optionally, the substrate further includes: an N-type peripheral region and a P-type peripheral region, the substrate surfaces of the N-type peripheral region and the P-type peripheral region respectively have fins; before forming the first gate oxide layer, A third gate oxide layer is formed on the sidewalls and top surfaces of the fins of the N-type peripheral region and the P-type peripheral region by a third oxidation process.

Optionally, the dummy gate layer also spans the fins of the N-type peripheral region and the P-type peripheral region.

Optionally, after removing the dummy gate layer, a third trench is formed in the dielectric layer of the N-type peripheral region, and a fourth trench is formed in the dielectric layer of the P-type peripheral region. A trench and a second trench expose the third gate oxide layer.

Optionally, the method further includes: forming a third gate structure filling the third trench and a fourth gate structure filling the fourth trench on the surface of the third gate oxide layer.

Optionally, the formation process of the third gate oxide layer includes an in-situ steam generation process; the thickness of the third gate oxide layer is 15 angstroms to 25 angstroms.

Optionally, the step of removing the first gate oxide layer at the bottom of the first trench includes: forming a first patterned layer on the surface of the first gate oxide layer, and the first patterned layer exposes the bottom of the first trench the first gate oxide layer; using the first patterned layer as a mask, etching the first gate oxide layer until the sidewalls and the top surface of the fin of the N-type core region are exposed.

Optionally, the process of etching the first gate oxide layer is a wet etching process or an isotropic dry etching process.

Optionally, after forming the second gate oxide layer and before forming the first gate structure and the second gate structure, a first annealing process is performed.

Optionally, the first annealing process is spike annealing or laser annealing.

Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, and the first gate layer fills the first trench; The second gate structure includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer, and the second gate layer fills the second trench.

Optionally, the step of forming the first gate structure and the second gate structure includes: forming a gate dielectric film on the surface of the dielectric layer, the inner wall surface of the first trench and the inner wall surface of the second trench; After the gate dielectric film is formed, a gate film is formed that fills the first trench and the second trench; the gate film and the gate dielectric film are planarized until the surface of the dielectric layer is exposed. A first gate dielectric layer and a first gate electrode layer are formed in the trench, and a second gate dielectric layer and a second gate electrode layer are formed in the second trench.

Optionally, the method further includes: after forming the gate dielectric film, performing a second annealing process.

Optionally, the top surface of the fin portion further has a mask layer.

Optionally, the step of forming the isolation layer includes: forming an isolation film on the surfaces of the substrate and the fin; planarizing the isolation film; after planarizing the isolation film, etch back the isolation film until until part of the sidewalls of the fins are exposed; while or after the isolation film is etched back, the mask layer is removed.

Optionally, before forming the isolation layer, a pad oxide layer is formed on the surfaces of the substrate and the fin; after the isolation layer is formed, the exposed pad oxide layer is removed.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the formation method of the present invention, after removing the dummy gate layer, a first trench exposing the first gate oxide layer is formed in the N-type core region, and a second trench exposing the first gate oxide layer is formed in the P-type core region groove. Wherein, before forming the dummy gate layer, the first gate oxide layer is formed on the sidewall and top surface of the fin by a first oxidation process. After the dummy gate layer is removed, the first gate oxide layer at the bottom of the first trench is removed, and a second oxide layer is formed on the exposed sidewalls and top surfaces of the fin portion of the first trench by a second oxidation process. The second oxide layer is located in the first trench, the first trench is located in the N-type core region, and the first trench is used to form a fin transistor in the N-type core region. Since the equivalent oxide thickness of the formed second oxide layer is smaller than that of the first gate oxide layer, when the second gate oxide layer is used as the gate oxide layer in the fin transistor in the N-type core region, it can improve the At the same time, defects or impurities in the second gate oxide layer have less influence on the bias temperature instability effect of the fin transistor in the N-type core region. Therefore, the performance of the fin transistor formed in the N-type core region is improved. At the same time, the first gate oxide layer formed by the first oxidation process is used as the gate oxide layer of the fin transistor formed by the P-type core region, and the defects or impurities in the first gate oxide layer formed by the first oxidation process are less, The bias temperature instability effect of the fin transistor in the P-type core region can be improved, thereby improving the performance of the fin transistor in the P-type core region.

Description of drawings

FIG. 1 to FIG. 9 are schematic cross-sectional structural diagrams of a formation process of a fin transistor according to an embodiment of the present invention.

Detailed ways

As described in the background art, as the density and size of semiconductor devices are increased, the performance and reliability of the formed fin field effect transistors are deteriorated.

After research, it was found that in order to further reduce the size of the device and improve the density of the device, a high-K metal gate transistor was introduced on the basis of the fin field effect transistor, that is, a high-K dielectric material was used as the gate dielectric layer, and metal material was used as the gate. Moreover, in order to improve the bonding state between the gate dielectric layer of the high-K dielectric material and the fins, a gate oxide layer needs to be formed between the gate dielectric layer of the high-K dielectric material and the fins for bonding. The high-K metal gate transistor is formed by a gate-last (GateLast) process. In one gate-last process, after the dummy gate layer of polysilicon is removed and a gate trench is formed, a high-K metal gate is formed on the inner wall surface of the gate trench. A gate dielectric layer of K dielectric material.

For the fin field effect transistor in the peripheral region, since the quality requirements of the gate oxide layer are low and the thickness of the gate oxide layer is required to be high, the gate oxide layer in the peripheral region can be formed before the dummy gate layer is formed. However, the damage to the gate oxide layer caused by the process of removing the dummy gate layer has little effect on the performance of the transistor in the peripheral region.

For the fin field effect transistor in the core area, the quality of the gate oxide layer is relatively high, and the damaged gate oxide layer not only easily causes Time Dependent Dielectric Breakdown (TDDB), but also causes short channel effect. , reduce the driving current, increase the power consumption, and easily cause the bias temperature instability effect (Bias Temperature Instability, BTI for short), and the performance of the formed fin field effect transistor deteriorates.

In order to avoid damage to the gate oxide layer in the core region caused by the etching process for removing the dummy gate layer, the gate oxide layer in the core region needs to be formed after the dummy gate layer is removed. In addition, after removing the dummy gate layer, an oxidation process is used to form a gate oxide layer of the core region on the exposed top and sidewall surfaces of the fin, and the process of forming the gate oxide layer of the core region can be in-situ steam generation. (In-Situ Steam Generation, referred to as ISSG) process.

The gate oxide layer in the core region formed by the in-situ steam generation process has fewer defects or impurities and has a uniform density distribution. However, the gate oxide layer in the core region formed by the in-situ vapor generation process has a relatively thick Equivalent Oxide Thickness (EOT), which is prone to adversely affect the fin field effect transistor. For the P-type fin field effect transistor in the core region, the bias temperature instability effect is mainly caused by defects or impurities in the gate oxide layer, so it is necessary to use the in-situ steam generation process to form the P-type fin field effect. The gate oxide layer in the core region of the transistor.

However, for the N-type fin field effect transistor in the core region, the bias temperature instability effect is mainly determined by the quality of the gate dielectric layer of the high-K dielectric material, while the quality of the gate oxide layer in the core region is less affected. . Using the in-situ steam generation process to form the gate oxide layer of the core region of the N-type fin field effect transistor will easily increase the equivalent oxide thickness of the gate oxide layer, which not only cannot improve the bias temperature instability effect, but also easily As a result, the performance of the formed N-type fin field effect transistor is deteriorated.

In order to solve the above problems, the present invention provides a method for forming a fin transistor, including: providing a substrate, the substrate includes an N-type core region and a P-type core region, and the N-type core region and the P-type core region have The surfaces of the substrates respectively have fins, the surfaces of the substrates have isolation layers, the isolation layers cover part of the sidewalls of the fins, and the surfaces of the isolation layers are lower than the top surfaces of the fins; using the first The oxidation process forms a first gate oxide layer on the sidewalls and top surfaces of the fins of the N-type core region and the P-type core region; and forms a first gate oxide layer on the surface of the isolation layer and the first gate oxide layer respectively across the N-type core region A dummy gate layer of the fins in the core region and the P-type core region, the dummy gate layer covers part of the sidewalls and the top of the fins; a dielectric layer is formed on the isolation layer and the fins, and the dielectric layer covers the dummy the sidewall of the gate layer, and the dielectric layer exposes the top of the dummy gate layer; the dummy gate layer is removed, a first trench is formed in the dielectric layer of the N-type core region, and a first trench is formed in the P-type core region A second trench is formed in the dielectric layer of the region, and the first trench and the second trench expose the first gate oxide layer; the first gate oxide layer at the bottom of the first trench is removed, and the N-type oxide layer is exposed the sidewalls and top surface of the fins of the core region; a second gate oxide layer is formed on the sidewalls and top surfaces of the fins exposed in the N-type core region by a second oxidation process, and the equivalent of the second gate oxide layer is The thickness of the oxide layer is less than the equivalent thickness of the oxide layer of the first gate oxide layer; a first gate structure filled with the first trench is formed on the surface of the first gate oxide layer; on the surface of the second gate oxide layer forming a second gate structure filling the second trench.

Wherein, after removing the dummy gate layer, a first trench exposing the first gate oxide layer is formed in the N-type core region, and a second trench exposing the first gate oxide layer is formed in the P-type core region. Wherein, before forming the dummy gate layer, the first gate oxide layer is formed on the sidewall and top surface of the fin by a first oxidation process. After the dummy gate layer is removed, the first gate oxide layer at the bottom of the first trench is removed, and a second oxide layer is formed on the exposed sidewalls and top surfaces of the fin portion of the first trench by a second oxidation process. The second oxide layer is located in the first trench, the first trench is located in the N-type core region, and the first trench is used to form a fin transistor in the N-type core region. Since the equivalent oxide thickness of the formed second oxide layer is smaller than that of the first gate oxide layer, when the second gate oxide layer is used as the gate oxide layer in the fin transistor in the N-type core region, it can improve the At the same time, defects or impurities in the second gate oxide layer have less influence on the bias temperature instability effect of the fin transistor in the N-type core region. Therefore, the performance of the fin transistor formed in the N-type core region is improved. At the same time, the first gate oxide layer formed by the first oxidation process is used as the gate oxide layer of the fin transistor formed by the P-type core region, and the defects or impurities in the first gate oxide layer formed by the first oxidation process are less, The bias temperature instability effect of the fin transistor in the P-type core region can be improved, thereby improving the performance of the fin transistor in the P-type core region.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 to FIG. 9 are schematic cross-sectional structural diagrams of a formation process of a fin transistor according to an embodiment of the present invention.

Referring to FIG. 1, a substrate 200 is provided, the substrate 200 includes an N-type core region 210 and a P-type core region 220, and the surfaces of the substrate 200 of the N-type core region 210 and the P-type core region 220 respectively have fins 201 , an isolation layer 202 is formed on the surface of the substrate 200 , the isolation layer 202 covers part of the sidewall of the fin 201 , and the surface of the isolation layer 202 is lower than the top surface of the fin 201 .

In this embodiment, the substrate 200 further includes: an N-type peripheral region 230 and a P-type peripheral region 240 , and the surfaces of the substrate 200 of the N-type peripheral region 230 and the P-type peripheral region 240 respectively have fins 201 .

The N-type core region 210 is used to form an N-type core device; the P-type core region 220 is used to form a P-type core device; the N-type peripheral region 230 is used to form an N-type peripheral device; the P-type peripheral region Region 240 is used to form P-type peripheral devices.

The density of the core device is greater than the density of the peripheral device, and the characteristic dimension (CriticalDimension, CD for short) of the core device is smaller than the characteristic dimension of the peripheral device. The working current or working voltage of the core device is smaller than the working current or working voltage of the peripheral device.

The top surface of the fins 201 can also have a mask layer. The mask layer serves as a mask for forming the fins 201 by etching, and the mask layer can also be used to protect the top surfaces of the fins 201 in subsequent processes.

In this embodiment, the steps of forming the substrate 200 and the fins 201 include: providing a semiconductor substrate; forming a mask layer on a part of the surface of the semiconductor substrate, and the mask layer covers the corresponding parts where the fins 201 need to be formed. position and shape; using the mask layer as a mask, the semiconductor substrate is etched to form the substrate 200 and the fins 201 .

The semiconductor substrates are silicon substrates, germanium substrates and silicon germanium substrates. In this embodiment, the semiconductor substrate is a single crystal silicon substrate, that is, the materials of the fins 201 and the substrate 200 are single crystal silicon.

The forming step of the mask layer includes: forming a mask material film on the surface of the semiconductor substrate; forming a second patterned layer on the surface of the mask material film; etching the second patterned layer as a mask The mask layer is formed by the mask material film until the surface of the semiconductor substrate is exposed.

In one embodiment, the second patterned layer is a patterned photoresist layer, and the second patterned layer is formed by a coating process and a photolithography process. In another embodiment, in order to reduce the feature size of the fins 201 and the distance between adjacent fins 201 , the second patterned layer is formed by a multiple patterning mask process. The multiple patterning mask process includes: a self-aligned double patterned (SaDP) process, a self-aligned triple patterned (Self-aligned triple patterned) process, or a self-aligned quadruple patterning (Self-aligned Double Double Patterned, SaDDP) process.

The process of etching the semiconductor substrate is an anisotropic dry etching process. The sidewalls of the fins 201 are perpendicular or inclined with respect to the surface of the substrate 200 , and when the sidewalls of the fins 201 are inclined with respect to the surface of the substrate 200 , the bottom dimension of the fins 201 is larger than the top dimension. In this embodiment, the sidewalls of the fins 201 are inclined relative to the surface of the substrate 200 .

The substrate 200 and the fin 201 of the N-type peripheral region 230 and the N-type core region 210 also have a first well region, and the substrate 200 and the fin 201 of the P-type peripheral region 240 and the P-type core region 220 There is also a second well region therein. The first well region and the second well region are formed by an ion implantation process; the first well region and the second well region can be formed before etching the semiconductor substrate to form the fin portion 201; or, the first well region and the second well region can be formed after the fins 201 are formed.

In another embodiment, the fin is formed by etching a semiconductor layer formed on the surface of the substrate; the semiconductor layer is formed on the surface of the substrate by a selective epitaxial deposition process. The substrate is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or GaAs substrates, etc. The material of the semiconductor layer is silicon, germanium, silicon carbide or silicon germanium.

The steps of forming the isolation layer 202 include: forming an isolation film on the surfaces of the substrate 200 and the fins 201; planarizing the isolation film; after planarizing the isolation film, etch back the isolation film until exposed until part of the sidewall of the fins 201 is removed; while or after the isolation film is etched back, the mask layer is removed.

In this embodiment, before forming the isolation layer 202, a pad oxide layer is formed on the surfaces of the substrate 200 and the fins 201; after the isolation layer 202 is formed, the exposed pad oxide layer is removed.

In this embodiment, the material of the isolation layer 202 is silicon oxide; the thickness of the isolation layer 202 is 1/4˜1/2 of the height of the fin portion 201 . The formation process of the isolation film is a fluid chemical vapor deposition process (FCVD, Flowable Chemical Vapor Deposition). In other embodiments, the isolation film can also be formed by other chemical vapor deposition processes or physical vapor deposition processes; the other chemical vapor deposition processes include plasma enhanced chemical vapor deposition (PECVD) or high aspect ratio chemical vapor deposition Process (HARP).

In this embodiment, the steps of the fluid chemical vapor deposition process include: forming a precursor dielectric film on the surfaces of the substrate 200, the fins 201 and the mask layer; performing an annealing process to solidify the precursor dielectric film to form the isolation film.

The planarization process is a chemical mechanical polishing process (CMP); in this embodiment, the chemical mechanical polishing process uses the mask layer as a stop layer. The process of etching back the isolation film is an isotropic dry etching process, an anisotropic dry etching process or a wet etching process.

In this embodiment, the mask layer is removed while or after the isolation film is etched back. After the isolation layer 202 is formed, the exposed pad oxide layer is removed; since the exposed pad oxide layer will be damaged in the process of etching back the isolation film, the pad oxide layer 203 is not suitable for As a subsequent gate oxide layer, the pad oxide layer therefore needs to be removed.

The formation process of the pad oxide layer is an in-situ steam generation (In-Situ Steam Generation, ISSG for short) process. The parameters of the in-situ steam generation process include: the temperature is 700°C to 1200°C, the gas includes hydrogen and oxygen, the oxygen flow is 1 slm to 50 slm, the hydrogen flow is 1 slm to 10 slm, and the time is 20 seconds to 10 minutes. The pad oxide layer formed by the in-situ steam generation process has good step coverage capability, so that the formed pad oxide layer can tightly cover the sidewall surface of the fin portion 201, and the formed pad oxide layer has a good step coverage. Uniform thickness.

By forming the pad oxide layer, damages on the surfaces of the substrate 200 and the fins 201 during the pre-etching process and the ion implantation process can be repaired. Moreover, the pad oxide layer can also protect the surfaces of the fins 201 and the substrate 200 in subsequent processes.

Referring to FIG. 2 , a third gate oxide layer 203 is formed on the sidewalls and top surfaces of the fins 201 of the N-type peripheral region 230 and the P-type peripheral region 240 by a third oxidation process.

The third gate oxide layer 203 is used to form the gate oxide layer in the fin transistor of the N-type peripheral region 230 and the P-type peripheral region 240, and is used to enhance the fin portion 201 in the N-type peripheral region 230 and the P-type peripheral region 240 The bonding strength with the gate dielectric layer formed subsequently, the material of the gate dielectric layer is a high-K dielectric material (dielectric coefficient is greater than 3.9).

The forming step of the third gate oxide layer 203 includes: adopting a third oxidation process to form a third oxidation process on the surfaces of the fins 201 of the N-type core region 210 , the N-type peripheral region 230 , the P-type core region 220 and the P-type peripheral region 240 respectively. Three gate oxide films; forming a first patterned layer on the surface of the third gate oxide film of the N-type core region 210 and the P-type core region 220; using the first patterned layer as a mask, etching the first patterned layer The third gate oxide layer 203 is formed until the sidewalls and top surfaces of the fins 201 of the N-type peripheral region 230 and the P-type peripheral region 240 are exposed by the triple gate oxide film.

The material of the third gate oxide layer 203 is silicon oxide; the thickness of the third gate oxide layer 203 is 15 angstroms to 25 angstroms. In this embodiment, the thickness of the third gate oxide layer 203 is 20 angstroms; the formation process of the third gate oxide film includes an in-situ steam generation process; the in-situ steam generation process for forming the third gate oxide film The parameters of the process include: the temperature is 700°C to 1200°C, the gas includes hydrogen and oxygen, the oxygen flow is 1slm to 50slm, the hydrogen flow is 1slm to 10slm, and the time is 10 seconds to 5 minutes.

Referring to FIG. 3 , a first gate oxide layer 204 is formed on the sidewalls and top surfaces of the fins 201 of the N-type core region 210 and the P-type core region 220 by a first oxidation process.

The first gate oxide layer 204 is used for the gate oxide layer in the fin transistor in the core region 210 . Since the core region 210 is used to form a core device, and the core device has a high device density and a low operating voltage, it is necessary to make the physical thickness of the first gate oxide layer 204 smaller to meet the requirement of reducing the size of the device , and at the same time, the thickness of the equivalent oxide layer in the first gate oxide layer 204 needs to be smaller, so as to meet the requirement of reducing the operating voltage.

In this embodiment, the material of the first gate oxide layer 204 is silicon oxide; the first oxidation process is an in-situ steam generation process. In the first gate oxide layer 204 formed by the in-situ vapor generation process, there are few defects or impurities, and the density of the first gate oxide layer 204 is high, which is beneficial to reduce the bias voltage instability effect in the P-type fin transistor . However, the equivalent oxide layer thickness of the first gate oxide layer 204 formed by the in-situ vapor generation process is relatively large, which tends to increase the threshold voltage of the formed fin transistor. Therefore, the first gate oxide layer 204 formed by the in-situ vapor generation process is used to form the first gate oxide layer. The performance improvement of the fin transistor by the oxygen layer 204 is limited.

The thickness of the first gate oxide layer 204 is 5 angstroms to 15 angstroms; in this embodiment, the thickness of the first gate oxide layer 204 is 10 angstroms. The thickness of the first gate oxide layer 204 is smaller than the thickness of the third gate oxide layer 203, so that the first gate oxide layer 204 can reduce the operating voltage of the core device.

The parameters of the in-situ steam generation process for forming the first gate oxide layer 204 include: the temperature is 700°C to 1200°C, the gas includes hydrogen and oxygen, the oxygen flow is 1slm to 50slm, the hydrogen flow is 1slm to 10slm, and the time is 10 seconds to 5 minutes. Since the thickness of the first gate oxide layer 204 is smaller than the thickness of the third gate oxide layer 203, the process time for forming the first gate oxide layer 204 is shorter than the process time for forming the third gate oxide film.

Referring to FIG. 4 , a dummy gate layer 205 is formed on the surface of the isolation layer 202 and the first gate oxide layer 204 respectively across the fins 201 of the N-type core region 210 and the P-type core region 220 . The dummy gate layer 205 covers part of the sidewall and top of the fins 201 .

In this embodiment, the dummy gate layer 205 also spans the fins 201 of the N-type peripheral region 230 and the P-type peripheral region 240 . The dummy gate layers 205 located in the N-type core region 210 , the N-type peripheral region 230 , the P-type core region 220 or the P-type peripheral region 240 can be the same dummy gate layer 205 or different dummy gate layers 205 .

The material of the dummy gate layer 205 is polysilicon. The steps of forming the dummy gate layer 205 include: forming a dummy gate film on the surface of the isolation layer 202 , the surface of the third gate oxide layer 203 and the surface of the first gate oxide layer 204 ; and planarizing the dummy gate film ; After the planarization process, a third patterned layer is formed on the surface of the dummy gate film, and the third patterned layer covers the position and shape where the dummy gate layer 205 needs to be formed; with the third patterned layer The layer is a mask, and the dummy gate film is etched until the surfaces of the isolation layer 202 and the fins 201 are exposed, and a dummy gate layer 205 is formed.

In this embodiment, the method further includes: forming spacers on the sidewall surfaces of the dummy gate layer 205 ; forming source regions and drain regions in the fins 201 on both sides of the dummy gate layer 205 and the spacers.

The material of the spacer includes one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. The steps of forming the spacers include: forming a spacer film on the surface of the dummy gate layer 205 by a deposition process; and etching back the spacer film until the surface of the fins 201 is exposed to form a spacer.

In one embodiment, the source and drain regions are formed by an ion implantation process. In another embodiment, the step of forming the source region and the drain region further includes: forming grooves in the dummy gate layer 205 and the fins 201 on both sides of the sidewall spacer; adopting a selective epitaxial deposition process in the A stress layer is formed in the groove; ions are doped in the stress layer to form a source region and a drain region. The doping process is one or a combination of an ion implantation process and an in-situ doping process.

When the formed fin transistor is a P-type fin transistor, the material of the stressor layer is silicon germanium, the ions doped in the stressor layer are P-type ions, and the stressor layer is a Σ-type stressor layer. When the formed fin transistor is an N-type fin transistor, the material of the stressor layer is silicon carbide, and the ions doped in the stressor layer are N-type ions.

Referring to FIG. 5 , a dielectric layer 206 is formed on the isolation layer 202 and the fins 201 , the dielectric layer 206 covers the sidewalls of the dummy gate layer 205 , and the dielectric layer 206 exposes the dummy gate layer 205 top.

The steps of forming the dielectric layer 206 include: forming a dielectric film on the surfaces of the isolation layer 202 , the fins 201 and the dummy gate layer 205 ; and planarizing the dielectric film until the top surface of the dummy gate layer 205 is exposed , forming the dielectric layer 206 .

The formation process of the dielectric film is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The material of the dielectric layer 206 is silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (dielectric coefficient is greater than or equal to 2.5, less than 3.9, such as porous silicon oxide or porous silicon nitride) or ultra-low k-dielectric material (dielectric coefficient less than 2.5, such as porous SiCOH).

In this embodiment, the material of the dielectric layer 206 is silicon oxide; the forming process of the dielectric film is a fluid chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD for short) process, High Density Plasma (High Density Plasma, for short). One or more of HDP) process, plasma enhanced deposition process.

Referring to FIG. 6 , the dummy gate layer 205 (as shown in FIG. 5 ) is removed, a first trench 211 is formed in the dielectric layer 206 of the N-type core region 210 , and the dielectric layer of the P-type core region 220 is formed. A second trench 221 is formed in the layer 206 , and the first gate oxide layer 204 is exposed from the first trench 211 and the second trench 221 .

In this embodiment, the method further includes: after removing the dummy gate layer 205 , forming a third trench 231 in the dielectric layer 206 of the N-type peripheral region 230 , and forming a third trench 231 in the dielectric layer of the P-type peripheral region 240 A fourth trench 241 is formed in 206 , and the third gate oxide layer 203 is exposed from the first trench 231 and the second trench 221 .

The process of removing the dummy gate layer 205 is one or a combination of a dry etching process and a wet etching process; wherein, the dry etching process is an isotropic dry etching process.

In this embodiment, the material of the dummy gate layer 205 is polysilicon, and the process of removing the dummy gate layer 205 is a plasma dry etching process; the parameters of the plasma dry etching process include: the gas includes _A fluorocarbon gas, one or more _{of HBr} and Cl2, and a carrier gas, the fluorocarbon gas including CF4, _CHF3 , _CH2F2 or _CH3F , the carrier gas being an inert gas such as He, the gas flow is 50 sccm to 400 sccm, and the pressure is 3 mtorr to 8 mtorr.

In another embodiment, the process of removing the dummy gate layer 205 is a wet etching process, and the etching solution of the wet etching process is a mixed solution of hydrofluoric acid and hydrogen peroxide.

Referring to FIG. 7 , the first gate oxide layer 204 at the bottom of the first trench 211 is removed (as shown in FIG. 6 ), and the sidewalls and the top surface of the fin portion 201 of the N-type core region 210 are exposed.

The impurities or defects inside the first gate oxide layer 204 are less and denser, which is beneficial to improve the bias voltage instability of the P-type fin transistor. However, the thickness of the equivalent oxide layer of the first gate oxide layer 204 is relatively large, which is easy to increase the threshold voltage of the fin transistor, and still easily affects the performance of the fin transistor as the core device. Especially for the N-type fin transistor as the core device, its bias temperature instability effect needs to be suppressed by improving the quality of the gate dielectric layer of the high-K dielectric material. Therefore, even if the first gate oxide layer 204 is used as a The gate oxide layer of the N-type fin transistor will deteriorate the performance of the N-type fin transistor as a core device.

Therefore, in this embodiment, the N-type core region 210 is improved by removing the first gate oxide layer 204 and forming a second gate oxide layer with a smaller equivalent oxide thickness on the surface of the fin portion 201 of the N-type core region 210 . The performance of the formed fin transistors.

The step of removing the first gate oxide layer 204 at the bottom of the first trench 211 includes: forming a first patterned layer 207 on the surface of the first gate oxide layer 204, and the first patterned layer 207 exposes the first trench 211 The first gate oxide layer 204 at the bottom; using the first patterned layer 207 as a mask, the first gate oxide layer 204 is etched until the sidewalls and tops of the fins 201 of the N-type core region 210 are exposed to the surface; remove the first patterned layer 207 .

The first patterned layer 207 includes a photoresist layer, and the photoresist layer is formed by a coating process and a photolithography process. Before forming the photoresist layer, the second trench 221 (as shown in FIG. 6 ), the third trench 231 (as shown in FIG. 6 ) and the fourth trench 241 (as shown in FIG. 6 ) shown) and on the surface of the dielectric layer 206 to form an anti-reflection layer, the surface of the anti-reflection layer is flat; the photoresist layer is formed on the surface of the anti-reflection layer; the anti-reflection layer is used to inhibit the photolithography process Diffuse reflection of light in the photoresist layer to improve the pattern accuracy of the photoresist layer.

The process of etching the first gate oxide layer 204 is a wet etching process or an isotropic dry etching process. In this embodiment, the material of the first gate oxide layer 204 is silicon oxide; when the first gate oxide layer 204 is removed by a wet etching process, the etching solution of the wet etching process is Hydrofluoric acid solution. When the first gate oxide layer 204 is removed by an isotropic dry etching process, the isotropic dry etching process can be a SICONI process.

In this embodiment, the first gate oxide layer 204 at the bottom of the first trench 211 is removed by etching using the SICONI process. The parameters of the SICONI process include: a power of 10W to 100W, a frequency of less than 100kHz, an etching temperature of 40 to 80 degrees Celsius, a pressure of 0.5 Torr to 50 Torr, and the etching gas includes NH ₃ , NF ₃ , and He, where NH 3 , NF 3 , and He. The flow rate of ₃ is 0sccm~500sccm, the flow rate of NF3 is _20sccm ~200sccm, the flow rate of He is 400sccm~1200sccm, and the flow rate ratio of NF3 to _NH3 is ₁ :20~5:1.

Referring to FIG. 8 , a second gate oxide layer 208 is formed on the sidewalls and the top surface of the fins 201 exposed by the N-type core region 210 by a second oxidation process. The equivalent oxide layer of the second gate oxide layer 208 is formed. The thickness is less than the equivalent oxide thickness of the first gate oxide layer 204 (shown in FIG. 6 ).

The second gate oxide layer 208 is used as the gate oxide layer of the fin transistor formed by the N-type core region 210 . The material of the second gate oxide layer 208 is silicon oxide; the formation process of the second gate oxide layer 208 is a chemical oxidation process.

The equivalent thickness of the second gate oxide layer 208 formed by the chemical oxidation process is smaller than that of the first gate oxide layer 204 . Therefore, the second gate oxide layer 208 is beneficial to reduce the size of the fin transistor formed by the N-type core region 210 threshold voltage, thereby improving the performance of the N-type fin transistor as the core device.

The steps of the chemical oxidation process include: oxidizing the exposed sidewalls and top surfaces of the fins 201 with an aqueous solution of ozone, and forming a second gate oxide layer on the sidewalls and top surfaces of the fins 201 223. Wherein, in the ozone-infused aqueous solution, the concentration of ozone in the water is 1% to 15%.

The thickness of the second gate oxide layer 208 is 5 angstroms˜15 angstroms. In this embodiment, the thickness of the second gate oxide layer 208 is 10 angstroms. The thickness of the second gate oxide layer 208 should not be too thin, otherwise the second gate oxide layer 208 may undergo tunneling, which will deteriorate the performance of the fin transistor; the thickness of the second gate oxide layer 208 should not be too thick. Otherwise, it is easy to increase the thickness of the equivalent oxide layer and increase the threshold voltage of the fin transistor, so the formed fin transistor is not suitable as a core device.

Referring to FIG. 9 , a first gate structure 212 filled with the first trench 211 (as shown in FIG. 8 ) is formed on the surface of the second gate oxide layer 208 ; A second gate structure 222 that fills the second trench 221 (as shown in FIG. 8 ) is formed.

In this embodiment, after forming the second gate oxide layer 208 and before forming the first gate structure 212 and the second gate structure 222, a first annealing process is performed. The first annealing process is spike annealing or laser annealing. The first annealing process is used to remove defects or impurities inside and on the surface of the fin portion 201 , as well as in the second gate oxide layer 208 and the third gate oxide layer 203 .

In this embodiment, the method further includes: forming a third gate structure 232 filling the third trench 231 (as shown in FIG. 8 ) on the surface of the third gate oxide layer 203 and filling the fourth trench 241 The fourth gate structure 242 (shown in FIG. 8 ).

The first gate structure 212 includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, and the first gate layer fills the first trench 211; The two-gate structure 222 includes a second gate dielectric layer and a second gate layer on the second gate dielectric layer, and the second gate layer fills the second trench 221 .

The third gate structure 232 includes a third gate dielectric layer and a third gate layer located on the third gate dielectric layer, and the third gate layer fills the third trench 231; The quad-gate structure 242 includes a fourth gate dielectric layer, and a fourth gate layer on the fourth gate dielectric layer, and the fourth gate layer fills the fourth trench 241 .

The steps of forming the first gate structure 212 , the second gate structure 222 , the third gate structure 232 and the fourth gate structure 242 include: on the surface of the dielectric layer 206 , a first trench 211 , a second gate A gate dielectric film is formed on the inner wall surfaces of the trench 221, the third trench 231 and the fourth trench 241; after the gate dielectric film is formed, the first trench 211, the second trench 221 and the third trench are formed to fill the The gate film of the trench 231 and the fourth trench 241; the gate film and the gate dielectric film are planarized until the surface of the dielectric layer 206 is exposed, and the first gate dielectric layer and the first gate dielectric layer are formed in the first trench 211. a gate layer, a second gate dielectric layer and a second gate layer are formed in the second trench 221, a third gate dielectric layer and a third gate layer are formed in the third trench 231, and a fourth trench is formed A fourth gate dielectric layer and a fourth gate layer are formed in 241 .

The materials of the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are high-k dielectric materials (the dielectric coefficient is greater than 3.9); the high-k dielectric materials include hafnium oxide, Zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide silicon, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide. The formation process of the gate dielectric film is an atomic layer deposition process.

The materials of the first gate layer, the second gate layer, the third gate layer and the fourth gate layer include copper, tungsten, aluminum or silver; the formation process of the gate film includes a chemical vapor deposition process, Physical vapor deposition process, atomic layer deposition process, electroplating process or electroless plating process. The process of planarizing the gate film and the gate dielectric film is a chemical mechanical polishing process (CMP).

In one embodiment, before forming the gate film, it further includes forming a work function film on the surface of the gate dielectric film; forming a gate film on the surface of the work function film; after planarizing the gate film , planarizing the work function film until the surface of the dielectric layer 206 is exposed to form a work function layer. The material of the work function layer formed in the first trench 211 and the third trench 231 includes N-type work function material; the material of the work function layer formed in the second trench 221 and the fourth trench 241 includes P-type work function material.

In this embodiment, after the gate dielectric film is formed, a second annealing process is performed. The second annealing process is used to remove defects or impurities in the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer. Furthermore, the annealing process can also be used to activate impurity ions in the source and drain regions within the fin 201 .

To sum up, in this embodiment, after the dummy gate layer is removed, a first trench exposing the first gate oxide layer is formed in the N-type core region, and a second trench exposing the first gate oxide layer is formed in the P-type core region groove. Wherein, before forming the dummy gate layer, the first gate oxide layer is formed on the sidewall and top surface of the fin by a first oxidation process. After the dummy gate layer is removed, the first gate oxide layer at the bottom of the first trench is removed, and a second oxide layer is formed on the exposed sidewalls and top surfaces of the fin portion of the first trench by a second oxidation process. The second oxide layer is located in the first trench, the first trench is located in the N-type core region, and the first trench is used to form a fin transistor in the N-type core region. Since the equivalent thickness of the formed second oxide layer is larger than that of the first gate oxide layer, when the second gate oxide layer is used as the gate oxide layer in the fin transistor in the N-type core region, the At the same time, defects or impurities in the second gate oxide layer have less influence on the bias temperature instability effect of the fin transistor in the N-type core region. Therefore, the performance of the fin transistor formed in the N-type core region is improved. Meanwhile, the first gate oxide layer formed by the first oxidation process is used as the gate oxide layer of the fin transistor formed by the P-type core region, and the defects or impurities in the first gate oxide layer formed by the first oxidation process are less, The bias temperature instability effect of the fin transistor in the P-type core region can be improved, thereby improving the performance of the fin transistor in the P-type core region.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. A method for forming a fin transistor, comprising: A substrate is provided, the substrate includes an N-type core region and a P-type core region, the substrate surfaces of the N-type core region and the P-type core region respectively have fins, the substrate surface has an isolation layer, the The isolation layer covers part of the sidewall of the fin, and the surface of the isolation layer is lower than the top surface of the fin; A first gate oxide layer is formed on the sidewalls and top surfaces of the fins of the N-type core region and the P-type core region by a first oxidation process; A dummy gate layer is formed on the surface of the isolation layer and the first gate oxide layer respectively across the fins of the N-type core region and the P-type core region, and the dummy gate layer covers part of the sidewalls and the top of the fins; forming a dielectric layer on the isolation layer and the fin, the dielectric layer covering the sidewalls of the dummy gate layer, and the dielectric layer exposing the top of the dummy gate layer; removing the dummy gate layer, forming a first trench in the dielectric layer of the N-type core region, forming a second trench in the dielectric layer of the P-type core region, the first trench and the second trench a trench exposes the first gate oxide layer; removing the first gate oxide layer at the bottom of the first trench, and exposing the fin sidewalls and the top surface of the N-type core region; A second gate oxide layer is formed on the sidewalls and top surfaces of the fins exposed in the N-type core region by a second oxidation process, and the equivalent oxide thickness of the second gate oxide layer is smaller than that of the first gate oxide layer. Effective oxide layer thickness; forming a first gate structure filling the first trench on the surface of the second gate oxide layer; A second gate structure filling the second trench is formed on the surface of the first gate oxide layer. 2 . The method for forming a fin transistor according to claim 1 , wherein the first oxidation process is an in-situ steam generation process. 3 . 3 . The method for forming a fin transistor according to claim 1 , wherein the thickness of the first gate oxide layer is 5 angstroms˜15 angstroms. 4 . 4 . The method for forming a fin transistor according to claim 1 , wherein the second oxidation process is a chemical oxidation process. 5 . 5 . The method for forming a fin transistor according to claim 1 , wherein the thickness of the second gate oxide layer is 5 angstroms˜15 angstroms. 6 . 6 . The method for forming a fin transistor according to claim 1 , wherein the substrate further comprises: an N-type peripheral region and a P-type peripheral region, linings of the N-type peripheral region and the P-type peripheral region. 7 . The bottom surfaces respectively have fins; before forming the first gate oxide layer, a third gate oxide layer is formed on the sidewalls and top surfaces of the fins of the N-type peripheral region and the P-type peripheral region by using a third oxidation process. 7 . The method for forming a fin transistor according to claim 6 , wherein the dummy gate layer further spans the fins of the N-type peripheral region and the P-type peripheral region. 8 . 8 . The method for forming a fin transistor according to claim 7 , wherein after removing the dummy gate layer, a third trench is formed in the dielectric layer of the N-type peripheral region, and a third trench is formed in the P-type peripheral region. 9 . A fourth trench is formed in the dielectric layer of the peripheral region, and the third gate oxide layer is exposed from the first trench and the second trench. 9 . The method for forming a fin transistor according to claim 8 , further comprising: forming a third gate structure filling the third trench on the surface of the third gate oxide layer, and filling the third gate Fourth gate structure with four trenches. 10 . The method for forming a fin transistor according to claim 6 , wherein the formation process of the third gate oxide layer comprises an in-situ steam generation process; and the thickness of the third gate oxide layer is 15 angstroms to 15 angstroms. 11 . 25 angstroms. 11 . The method for forming a fin transistor according to claim 1 , wherein the step of removing the first gate oxide layer at the bottom of the first trench comprises: forming a first pattern on the surface of the first gate oxide layer. 12 . layer, the first patterned layer exposes the first gate oxide layer at the bottom of the first trench; using the first patterned layer as a mask, the first gate oxide layer is etched until the N-type layer is exposed the fin sidewalls and top surface of the core region. 12 . The method for forming a fin transistor according to claim 11 , wherein the process of etching the first gate oxide layer is a wet etching process or an isotropic dry etching process. 13 . 13 . The method for forming a fin transistor according to claim 1 , wherein a first annealing process is performed after the second gate oxide layer is formed and before the first gate structure and the second gate structure are formed. 14 . 14. The method for forming a fin transistor according to claim 13, wherein the first annealing process is spike annealing or laser annealing. 15. The method for forming a fin transistor according to claim 1, wherein the first gate structure comprises a first gate dielectric layer and a first gate layer on the first gate dielectric layer, wherein the first gate layer fills the first trench; the second gate structure includes a second gate dielectric layer and a second gate layer on the second gate dielectric layer, the second gate layer fills the second trench. 16 . The method for forming a fin transistor according to claim 15 , wherein the forming step of the first gate structure and the second gate structure comprises: on the surface of the dielectric layer, at the surface of the first trench. 17 . forming a gate dielectric film on the inner wall surface and the inner wall surface of the second trench; after forming the gate dielectric film, forming a gate film filling the first trench and the second trench; planarizing the gate film and the gate Until the dielectric film is exposed on the surface of the dielectric layer, a first gate dielectric layer and a first gate electrode layer are formed in the first trench, and a second gate dielectric layer and a second gate electrode layer are formed in the second trench. 17 . The method for forming a fin transistor according to claim 16 , further comprising: performing a second annealing process after forming the gate dielectric film. 18 . 18 . The method for forming a fin transistor according to claim 1 , wherein the top surface of the fin further has a mask layer. 19 . 19 . The method for forming a fin transistor according to claim 18 , wherein the step of forming the isolation layer comprises: forming an isolation film on the surfaces of the substrate and the fin; planarizing the isolation film; After planarizing the isolation film, the isolation film is etched back until part of the sidewall of the fin is exposed; while or after the isolation film is etched back, the mask layer is removed. 20. The method for forming a fin transistor according to claim 1, wherein before forming the isolation layer, a pad oxide layer is formed on the surfaces of the substrate and the fin; after the isolation layer is formed , to remove the exposed pad oxide.

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