CN106952815A - Method for forming fin transistors - Google Patents

Abstract

A kind of forming method of fin transistor, including：There is provided includes the substrate of core space and external zones, and the substrate surface of core space and external zones has fin respectively；In substrate surface formation separation layer, separation layer covers the partial sidewall of fin, and insulation surface is less than the top surface of fin；In fin side wall and top surface the first grid oxide layer of formation of external zones and the protective layer positioned at the first grid oxide layer surface, the dielectric coefficient of protective layer is more than the dielectric coefficient of the first grid oxide layer；In the formation of separation layer, fin and protective layer respectively across the pseudo- gate layer of core space and external zones fin；In separation layer and fin portion surface formation dielectric layer, dielectric layer is exposed at the top of pseudo- gate layer；Pseudo- gate layer is removed, first groove is formed in the dielectric layer of external zones, second groove is formed in the dielectric layer of core space；Fin side wall and top surface the second grid oxide layer of formation gone out in second groove bottom-exposed.The leakage current of the fin transistor formed is controlled, and reliability is improved.

Description

Method for forming fin transistors

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin transistor.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices.

In order to overcome the short-channel effect of the transistor and suppress the leakage current, a Fin Field Effect Transistor (Fin FET) is proposed in the prior art, and the Fin Field Effect Transistor is a common multi-gate device. The structure of the fin field effect transistor includes: a fin located on the surface of the semiconductor substrate and a dielectric layer, the dielectric layer covers part of the sidewall of the fin, and the surface of the dielectric layer is lower than the top of the fin; located on the surface of the dielectric layer, and a gate structure on the top and sidewall surfaces of the fin; a source region and a drain region in the fin on both sides of the gate structure.

However, as the density of semiconductor devices increases and the size shrinks, the manufacturing process of fin field effect transistors becomes more difficult, and the performance and reliability of the formed fin field effect transistors deteriorate.

Contents of the invention

The problem solved by the present invention is to provide a method for forming a fin transistor, the leakage current of the formed fin transistor is controlled, the driving current is increased, the power consumption is reduced, and the stability is improved.

In order to solve the above problems, the present invention provides a method for forming a fin transistor, comprising: providing a substrate, the substrate includes a core region and a peripheral region, and the substrate surfaces of the core region and the peripheral region respectively have fins; An isolation layer is formed on the surface of the substrate, the isolation layer covers part of the sidewall of the fin, and the surface of the isolation layer is lower than the top surface of the fin; on the sidewall and top of the fin in the peripheral region A first gate oxide layer and a protection layer located on the surface of the first gate oxide layer are formed on the surface, and the dielectric coefficient of the protection layer is greater than that of the first gate oxide layer; Form a dummy gate layer across the fins of the core region and the peripheral region respectively on the surface of the protective layer and the surface of the protective layer, and the dummy gate layer covers part of the sidewalls and tops of the fins; forming a dielectric layer, the dielectric layer covers the sidewall of the dummy gate layer, and the dielectric layer exposes the top of the dummy gate layer; removes the dummy gate layer, and forms a second dummy gate layer in the dielectric layer of the peripheral region A trench, forming a second trench in the dielectric layer of the core region; forming a second gate oxide layer on the exposed fin sidewall and top surface at the bottom of the second trench; forming a second gate oxide layer on the surface of the protective layer forming a first gate structure filling the first trench; forming a second gate structure filling the second trench on the surface of the second gate oxide layer.

Optionally, the step of forming the first gate oxide layer and the protective layer includes: forming a first gate oxide film on the sidewall and top surface of the exposed fin; Form a protective film on the surface of the layer; form a first patterned layer on the surface of the protective film in the peripheral area; use the first patterned layer as a mask to etch the protective film and the first gate oxide film in the core area to expose A first gate oxide layer and a protection layer are formed on the side walls and top surfaces of the fins in the core area; after etching the protection film and the first gate oxide film in the core area, the first patterned layer is removed.

Optionally, the formation process of the protective film is an atomic layer deposition process.

Optionally, it also includes: before forming the dummy gate layer, forming a dummy gate dielectric layer on the surface of the isolation layer, the fin and the protection layer; after removing the dummy gate layer, removing the first trench and the second trench The dummy gate dielectric layer at the bottom of the trench.

Optionally, the formation process of the dummy gate dielectric layer is an atomic layer deposition process.

Optionally, the material of the protection layer includes a high-K dielectric material.

Optionally, the material of the protective layer includes: Al ₂ O ₃ , ZrO ₂ , HfO ₂ ; Al2O3, ZrO ₂ or HfO ₂ doped with nitrogen; or silicon oxide doped with aluminum, yttrium, hafnium or nitrogen.

Optionally, the dielectric coefficient of the protective layer is 6-20.

Optionally, the protective layer has a thickness of 5 angstroms to 25 angstroms.

Optionally, the formation process of the first gate oxide layer is an in-situ steam generation process.

Optionally, the thickness of the first gate oxide layer is 10 angstroms to 35 angstroms.

Optionally, the formation process of the second gate oxide layer is a thermal oxidation process or a wet oxidation process.

Optionally, the process for removing the dummy gate layer is one or a combination of wet etching process and dry etching process.

Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, and the first gate layer fills the first trench; The second gate structure includes a second gate dielectric layer and a second gate layer on the second gate dielectric layer, and the second gate layer fills the second trench.

Optionally, the step of forming the first gate structure and the second gate structure includes: forming a gate dielectric film on the surface of the dielectric layer, the inner wall surface of the first trench, and the inner wall surface of the second trench; After forming the gate dielectric film, form a gate film that fills the first trench and the second trench; planarize the gate film and the gate dielectric film until the surface of the dielectric layer is exposed, and in the first trench A first gate dielectric layer and a first gate layer are formed in the groove, and a second gate dielectric layer and a second gate layer are formed in the second trench.

Optionally, the top surface of the fin further has a mask layer.

Optionally, the step of forming the substrate and the fins includes: providing a semiconductor base; forming a mask layer on a part of the surface of the semiconductor base, the mask layer covering the corresponding position and shape of the fins to be formed; The mask layer is a mask, and the semiconductor base is etched to form the substrate and fins.

Optionally, the step of forming the isolation layer includes: forming an isolation film on the surface of the substrate and the fin; planarizing the isolation film; after planarizing the isolation film, etching back the isolation film until until part of the fin sidewall is exposed.

Optionally, the mask layer is removed while or after etching back the isolation film.

Optionally, before forming the isolation layer, a pad oxide layer is formed on the surface of the substrate and the fin; after the isolation layer is formed, the exposed pad oxide layer is removed.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the forming method of the present invention, a first gate oxide layer is formed on the sidewall and top surface of the fin in the peripheral region, and a protective layer is formed on the surface of the first gate oxide layer, and the dummy gate layer is formed on the protective layer. layer surface. When the dielectric layer is subsequently formed and the dummy gate layer is removed, the protection layer can be used to protect the first gate oxide layer from damage, avoiding the breakdown effect of the first gate oxide layer over time, thereby improving the formed The ability of the fin transistor to suppress the short channel effect increases the driving current, reduces the power consumption of the transistor, and suppresses the influence of the bias temperature instability effect. Moreover, since the dielectric coefficient of the protective layer is greater than that of the first gate oxide layer, the gap between the subsequently formed first gate structure and the fin can be reduced without increasing the threshold voltage of the fin transistor. carrier tunneling phenomenon. Therefore, the performance and reliability of the formed FinFET are improved.

Description of drawings

1 to 4 are schematic cross-sectional structure diagrams of the formation process of a fin field effect transistor;

5 to 15 are schematic cross-sectional structure diagrams of the formation process of the fin transistor according to the embodiment of the present invention.

detailed description

As mentioned in the background, as the density of semiconductor devices increases and the size shrinks, the performance and reliability of the formed fin field effect transistors deteriorate.

In order to further reduce the size of the device and increase the density of the device, a high-k metal gate transistor is introduced on the basis of the fin field effect transistor, that is, a high-k dielectric material is used as the gate dielectric layer, and a metal material is used as the gate. Moreover, in order to improve the bonding state between the gate dielectric layer of high-K dielectric material and the fin, a gate oxide layer needs to be formed between the gate dielectric layer of high-K dielectric material and the fin for adhesion. The high-K metal gate transistor is formed using a Gate Last process, in which a gate last process is to remove the dummy gate layer of polysilicon and form a gate trench, and then form a gate on the inner wall surface of the gate trench. Gate dielectric layer of high-K dielectric material.

However, for the FinFET in the peripheral region, since the gate oxide layer is formed before forming the dummy gate layer, the process of removing the dummy gate layer will damage the gate oxide layer. As the size of the FinFET becomes smaller, the damage of the gate oxide layer has a more obvious impact on the performance of the device. It will be described below in conjunction with the accompanying drawings.

1 to 4 are schematic cross-sectional structure diagrams of the formation process of a fin field effect transistor.

Please refer to FIG. 1 , a substrate 100 is provided, the substrate 100 includes a core area 110 and a peripheral area 120, the surfaces of the substrate 100 of the core area 110 and the peripheral area 120 have fins 101 respectively, and the surface of the substrate 100 An isolation layer 102 is formed, the isolation layer 102 covers part of the sidewall surface of the fin portion 101 , and the surface of the isolation layer 102 is lower than the top surface of the fin portion 101 .

Referring to FIG. 2, a first gate oxide layer 103 is formed on the exposed sidewall and top surface of the fin portion 101; 120 dummy gate layer 104 of the fin portion 101 , the dummy gate layer 104 covers part of the sidewall and top of the fin portion 101 .

Referring to FIG. 3 , a dielectric layer 105 is formed on the surface of the first gate oxide layer 103 , the dielectric layer 105 covers the sidewall of the dummy gate layer 104 , and the dielectric layer 105 exposes the dummy gate layer 104 top.

Referring to FIG. 4 , the dummy gate layer 104 is removed, a first trench 121 is formed in the dielectric layer 105 of the peripheral region 120 , and a second trench 111 is formed in the dielectric layer 105 of the core region 110 .

Wherein, the formation process of the first gate oxide layer 103 is an atomic layer deposition process, and the material is silicon oxide. The first gate oxide layer 103 is used to protect the sidewall and top surface of the fin 101 of the core region 110 and the peripheral region 120 when the dummy gate layer 104 is removed. Since the density of silicon oxide formed by the atomic layer deposition process is low, defects are easily formed inside. Therefore, the first gate oxide layer 103 is not suitable as the gate oxide layer of the fin field effect transistor in the core region 110, and the core needs to be removed later. The first gate oxide layer 103 of the region 110.

Secondly, since the fin field effect transistor in the peripheral region 120 has lower requirements on the density of the gate oxide layer and the number of internal defects, the first oxide layer 103 in the peripheral region 120 can be retained as the fin field effect transistor formed in the peripheral region 120 inner gate oxide layer. After removing the dummy gate layer 104 , the first gate oxide layer 103 of the core region 110 needs to be removed subsequently, and a second gate oxide layer is formed on the exposed fin portion 101 and bottom surface of the core region 110 by a thermal oxidation process.

However, although the first gate oxide layer 103 can protect the side walls and top surfaces of the fins 101 of the core region 110 and the peripheral region 120 when the dummy gate layer 104 is removed, the etching process for removing the dummy gate layer 104 It is also easy to cause damage to the first gate oxide layer 103, and the damaged first gate oxide layer 103 is not only likely to cause Time Dependent Dielectric Breakdown (TDDB for short), cause short channel effect, reduce Drive current, increase power consumption, and easily cause bias temperature instability (Bias Temperature Instability, referred to as BTI), resulting in poor performance of the formed transistor.

In order to solve the above problems, the present invention provides a method for forming a fin transistor, comprising: providing a substrate, the substrate includes a core region and a peripheral region, the substrate surfaces of the core region and the peripheral region respectively have fins; An isolation layer is formed on the surface of the substrate, the isolation layer covers part of the sidewall of the fin, and the surface of the isolation layer is lower than the top surface of the fin; on the sidewall and top of the fin in the peripheral region A first gate oxide layer and a protection layer located on the surface of the first gate oxide layer are formed on the surface, and the dielectric coefficient of the protection layer is greater than that of the first gate oxide layer; Form a dummy gate layer across the fins of the core region and the peripheral region respectively on the surface of the protective layer and the surface of the protective layer, and the dummy gate layer covers part of the sidewalls and tops of the fins; forming a dielectric layer, the dielectric layer covers the sidewall of the dummy gate layer, and the dielectric layer exposes the top of the dummy gate layer; removes the dummy gate layer, and forms a second dummy gate layer in the dielectric layer of the peripheral region A trench, forming a second trench in the dielectric layer of the core region; forming a second gate oxide layer on the exposed fin sidewall and top surface at the bottom of the second trench; forming a second gate oxide layer on the surface of the protective layer forming a first gate structure filling the first trench; forming a second gate structure filling the second trench on the surface of the second gate oxide layer.

Wherein, a first gate oxide layer is formed on the sidewall and top surface of the fin in the peripheral region, and a protection layer is formed on the surface of the first gate oxide layer, and the dummy gate layer is formed on the surface of the protection layer. When the dielectric layer is subsequently formed and the dummy gate layer is removed, the protection layer can be used to protect the first gate oxide layer from damage, avoiding the breakdown effect of the first gate oxide layer over time, thereby improving the formed The ability of the fin transistor to suppress the short channel effect increases the driving current, reduces the power consumption of the transistor, and suppresses the influence of the bias temperature instability effect. Moreover, since the dielectric coefficient of the protective layer is greater than that of the first gate oxide layer, the gap between the subsequently formed first gate structure and the fin can be reduced without increasing the threshold voltage of the fin transistor. carrier tunneling phenomenon. Therefore, the performance and reliability of the formed FinFET are improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

5 to 15 are schematic cross-sectional structure diagrams of the formation process of the fin transistor according to the embodiment of the present invention.

Referring to FIG. 5 , a substrate 200 is provided. The substrate 200 includes a core region 220 and a peripheral region 210 , and the surfaces of the substrate 200 of the core region 220 and the peripheral region 210 respectively have fins 201 .

The core area 220 is used to form core devices, and the peripheral area 210 is used to form peripheral devices, such as input/output (I/O) devices. The core device density of the core region 220 is greater than the peripheral device density of the peripheral region 210 , and the critical dimension (Critical Dimention, CD for short) of the core device is smaller than the characteristic dimension of the peripheral device. The operating current or operating voltage of the core device is lower than the operating current or operating voltage of the peripheral device. In this embodiment, the surface of the substrate 200 in the core region 220 and the peripheral region 210 has fins 201 for forming fin transistors in the core region 220 and the peripheral region 210 respectively.

In this embodiment, the top surface of the fin portion 201 also has a mask layer 202 . The mask layer 202 is used as a mask for forming the fin portion 201 by etching, and the mask layer 202 can also be used to protect the top surface of the fin portion 201 in a subsequent process.

In this embodiment, the steps of forming the substrate 200 and the fins 201 include: providing a semiconductor base; forming a mask layer 202 on a part of the surface of the semiconductor base, and the mask layer 202 covers The corresponding position and shape of the semiconductor substrate are etched using the mask layer 202 as a mask to form the substrate 200 and the fins 201 .

The semiconductor substrate is a silicon substrate, a germanium substrate and a silicon germanium substrate. In this embodiment, the semiconductor substrate is a single crystal silicon substrate, that is, the material of the fin portion 201 and the substrate 200 is single crystal silicon.

The forming step of the mask layer 202 includes: forming a mask material film on the surface of the semiconductor substrate; forming a second patterned layer on the surface of the mask material film; using the second patterned layer as a mask to etch the The mask material film is formed until the surface of the semiconductor substrate is exposed to form the mask layer 202 .

In one embodiment, the second patterned layer is a patterned photoresist layer, and the second patterned layer is formed by a coating process and a photolithography process. In another embodiment, in order to reduce the feature size of the fins 201 and the distance between adjacent fins 201 , the second patterned layer is formed by a multiple patterned mask process. The multiple patterned mask process includes: self-aligned double patterned (Self-aligned Double Patterned, SaDP) process, self-aligned triple patterned (Self-aligned Triple Patterned) process, or self-aligned quadruple patterned ( Self-aligned Double Double Patterned, SaDDP) process.

The process of etching the semiconductor substrate is an anisotropic dry etching process. The sidewall of the fin 201 is vertical or inclined relative to the surface of the substrate 200 , and when the sidewall of the fin 201 is inclined relative to the surface of the substrate 200 , the bottom dimension of the fin 201 is larger than the top dimension. In this embodiment, the sidewalls of the fins 201 are inclined relative to the surface of the substrate 200 .

The substrate 200 and the fin portion 201 of the peripheral region 210 further have a first well region, and the core region 220 further has a second well region within the substrate 200 and the fin portion 201 . The first well region and the second well region are formed by an ion implantation process; the first well region and the second well region can be formed before etching the semiconductor substrate to form the fin 201; or, the first well region And the second well region can be formed after forming the fin 201 .

In another embodiment, the fins are formed by etching a semiconductor layer formed on the surface of the substrate; the semiconductor layer is formed on the surface of the substrate by a selective epitaxial deposition process. The substrate is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or gallium arsenide substrate, etc. The material of the semiconductor layer is silicon, germanium, silicon carbide or silicon germanium.

In this embodiment, before the subsequent formation of the isolation layer, it further includes forming a pad oxide layer 203 on the surface of the substrate 200 and the fin portion 201 . The formation process of the pad oxide layer 203 is an In-Situ Steam Generation (ISSG for short) process. The parameters of the in-situ steam generation process include: the temperature is 700°C-1200°C, the gas includes hydrogen and oxygen, the flow rate of oxygen is 1slm-50slm, the flow rate of hydrogen is 1slm-10slm, and the time is 20 seconds-10 minutes. The pad oxide layer 203 formed by the in-situ steam generation process has a good step coverage ability, which can make the formed pad oxide layer 203 tightly cover the side wall surface of the fin 201, and the formed pad oxide layer Layer 203 has a uniform thickness.

By forming the pad oxide layer 203 , the damage to the surface of the substrate 200 and the fin portion 201 during the preceding etching process and ion implantation process can be repaired. Moreover, the pad oxide layer 203 can also protect the surface of the fin portion 201 and the substrate 200 in subsequent processes.

Referring to FIG. 6, an isolation layer 204 is formed on the surface of the substrate 200, the isolation layer 204 covers part of the sidewall of the fin 201, and the surface of the isolation layer 204 is lower than the top surface of the fin 201. .

The step of forming the isolation layer 204 includes: forming an isolation film on the surface of the substrate 200 and the fin portion 201; planarizing the isolation film; after planarizing the isolation film, etching back the isolation film until exposed part of the side wall of the fin portion 201.

In this embodiment, the material of the isolation layer 204 is silicon oxide; the thickness of the isolation layer 204 is 1/4˜1/2 of the height of the fin portion 201 . The formation process of the isolation film is a fluid chemical vapor deposition process (FCVD, Flowable Chemical Vapor Deposition). In other embodiments, the isolation film can also be formed by other chemical vapor deposition processes or physical vapor deposition processes; the other chemical vapor deposition processes include plasma enhanced chemical vapor deposition (PECVD) or high aspect ratio chemical vapor deposition process (HARP).

In this embodiment, the steps of the fluid chemical vapor deposition process include: forming a precursor dielectric film on the surfaces of the substrate 200, the fin portion 201 and the mask layer 202; performing an annealing process to solidify the precursor dielectric film to form the the isolation film.

The material of the precursor medium film is a flowable material containing silicon; the flowable material can be a polymer containing one or more of Si-H bonds, Si-N bonds and Si-O bonds. The process parameters for forming the precursor dielectric film include: the process temperature is 60° C. to 70° C., which is 65° C. in this embodiment.

The annealing process in the fluid chemical vapor deposition process can be a wet annealing process or a dry annealing process; the parameters of the annealing process include: the temperature is less than or equal to 600°C, and the annealing gas includes H ₂ , O ₂ , N ₂ , One or more combinations of Ar and He, the annealing time is 5 seconds to 1 minute. Wherein, when the annealing gas includes H ₂ and O ₂ , the annealing process is a wet annealing process.

The planarization process is a chemical mechanical polishing process (CMP); in this embodiment, the chemical mechanical polishing process uses the mask layer 202 as a stop layer. The process of etching back the isolation film is an isotropic dry etching process, an anisotropic dry etching process or a wet etching process.

In this embodiment, the mask layer 202 (as shown in FIG. 5 ) is removed while or after the isolation film is etched back. After the isolation layer 204 is formed, the exposed pad oxide layer 203 is removed; since the exposed pad oxide layer 203 will be damaged in the process of etching back the isolation film, the pad oxide layer 203 It is not suitable as a subsequent gate oxide layer, so the pad oxide layer 203 needs to be removed.

A first gate oxide layer and a protection layer located on the surface of the first gate oxide layer are formed on the sidewall and top surface of the fin in the peripheral region, and the dielectric coefficient of the protection layer is greater than that of the first gate oxide layer. coefficient. The steps of forming the first gate oxide layer and the protection layer are shown in FIG. 7 to FIG. 8 .

Referring to FIG. 7 , a first gate oxide film 211 is formed on the exposed sidewalls and top surfaces of the fin portion 201 .

The first gate oxide film 211 is used to form the gate oxide layer in the fin transistor in the peripheral region 210, and is used to enhance the bonding strength between the fin portion 201 and the subsequently formed first gate dielectric layer in the peripheral region 210, so The material of the first gate dielectric layer is a high-K dielectric material (dielectric coefficient greater than 3.9), and the first gate dielectric layer is used as the gate dielectric layer of the fin field effect transistor in the peripheral region 210 .

The material of the first gate oxide film 211 is silicon oxide, and the thickness of the first gate oxide film 211 is 10 angstroms to 35 angstroms; in this embodiment, the thickness of the first gate oxide film is 15 angstroms. In this embodiment, the formation process of the first gate oxide film 211 is an in-situ steam generation process; the parameters of the in-situ steam generation process include: the temperature is 700°C-1200°C, the gas includes hydrogen and oxygen, oxygen The flow rate is 1slm-50slm, the hydrogen flow rate is 1slm-10slm, and the time is 10 seconds-5 minutes.

In another embodiment, the formation process of the first gate oxide film 211 is a chemical oxidation process; the step of the chemical oxidation process includes: using an aqueous solution fed with ozone to expose the sidewalls and The top surface is oxidized to form a first oxide layer on the sidewall and top surface of the fin 201 . Wherein, in the aqueous solution fed with ozone, the concentration of ozone in water is 1%-15%.

Referring to FIG. 8 , a protective film 212 is formed on the surface of the first gate oxide film 211 and the isolation layer 204 .

The protection film 212 is used to protect the first gate oxide layer when the dummy gate layer is subsequently removed, and the first gate oxide layer is formed by the first gate oxide film 211 of the peripheral region 210 . Since the first gate oxide layer is used to form the gate oxide layer in the fin field effect transistor in the peripheral region 210 , the first gate oxide film 211 in the peripheral region 210 needs to be exposed and retained in subsequent processes. The protection layer formed by the protection film 212 can reduce the damage to the first gate oxide layer in the subsequent etching process for removing the dummy gate layer.

In this embodiment, the material of the protective film 212 includes a high-K dielectric material, the material density and hardness of the formed protective layer are relatively high, and the etching selectivity between the material of the subsequently formed dummy gate layer is relatively large, Therefore, it is enough to protect the formed first gate oxide layer in the subsequent process.

Moreover, since the material of the protection film 212 has a relatively high dielectric coefficient, the formed protection layer is located between the first gate oxide layer and the subsequently formed first gate dielectric layer, and the protection layer can be used without raising the fin. In the case of the threshold voltage of the normal transistor, the carrier tunneling phenomenon between the fin portion 201 and the first gate dielectric layer is suppressed, and the leakage current is reduced.

In this embodiment, the dielectric coefficient of the protection film 212 is 6-20. The material of the protective film 212 includes: Al ₂ O ₃ , ZrO ₂ , HfO ₂ ; Al ₂ O ₃ , ZrO ₂ or HfO ₂ doped with nitrogen; or silicon oxide doped with aluminum, yttrium, hafnium or nitrogen. In other embodiments, the material of the protective film 212 can also be other high-K dielectric materials (dielectric coefficient greater than 3.9).

In this embodiment, the formation process of the protection film 212 is an atomic layer deposition process. The protective film 212 formed by the atomic layer deposition process has good step coverage and can closely adhere to the surface of the isolation layer 204 and the first gate oxide layer 211; moreover, the formed protective film 212 has a uniform thickness, which is conducive to making The threshold voltage of the FinFET formed by region 210 is stabilized.

The thickness of the protection film 212 is 5 angstroms to 25 angstroms; in this embodiment, the thickness of the protection film 212 is 20 angstroms. The thickness of the protective film 212 should not be too thick, otherwise the threshold voltage of the fin transistors formed in the peripheral region 210 will be easily increased, which is not conducive to reducing the power consumption of semiconductor devices. The thickness of the protection film 212 should not be too thin, otherwise the subsequent formation of the protection layer will not be enough to protect the first gate oxide layer, and the first gate oxide layer will still be easily damaged.

Referring to FIG. 9 , a first patterned layer 222 is formed on the surface of the protective film 212 in the peripheral region 210; using the first patterned layer 222 as a mask, the protective film 212 of the core region 220 is etched (as shown in FIG. 8 ) and the first gate oxide film 211 (as shown in FIG. 8 ) expose the sidewalls and top surfaces of the fins 201 of the core region 220 to form a first gate oxide layer 211a and a protective layer 212a.

The first patterned layer 222 is a patterned photoresist layer, and the first patterned layer 222 is formed by a coating process and a photolithography process. The process of etching the protection film 212 and the first gate oxide film 211 is a wet etching process or an isotropic dry etching process.

In this embodiment, the material of the protective film 212 includes a high-K dielectric material, and the material of the first gate oxide film 211 is silicon oxide; the processes of etching the protective film 212 and the first gate oxide film 211 are both It is an isotropic dry etching process.

In this embodiment, the isotropic dry etching process for etching the first gate oxide film 211 can be a SICONI process. The etching rate of the SICONI process in different directions is uniform, and the first gate oxide layer 211 located on the sidewall and top surface of the fin 201 can be uniformly removed, and the damage to the sidewall and top surface of the fin 201 smaller.

The parameters of the SICONI process include: power 10W-100W, frequency less than 100kHz, etching temperature 40-80 degrees Celsius, pressure 0.5 Torr-50 Torr, etching gas includes NH ₃ , NF ₃ , He, wherein, NH The flow rate of ₃ is 0 sccm-500 sccm, the flow rate of NF ₃ is 20 sccm-200 sccm, the flow rate of He is 400 sccm-1200 sccm, and the flow ratio of NF ₃ and NH ₃ is 1:20-5:1.

Referring to FIG. 10 , a dummy gate layer 205 is formed on the surfaces of the isolation layer 204 , the fin portion 201 and the protective layer 212a respectively across the fin portion 201 of the core region 220 and the peripheral region 210 , and the dummy gate layer 205 covers the Part of the sidewall and top of the fin 201 .

In this embodiment, after etching the protective film 212 (as shown in FIG. 8 ) and the first gate oxide film 211 (as shown in FIG. 8 ) of the core region 210 , the first patterned layer 222 is removed.

The material of the dummy gate layer 205 is polysilicon. The step of forming the dummy gate layer 205 includes: forming a dummy gate film on the surface of the isolation layer 204, the surface of the fin portion 201 and the surface of the protective layer 212a of the peripheral region 210; planarizing the dummy gate film; After the planarization process, a third patterned layer is formed on the surface of the dummy gate film, and the third patterned layer covers the position and shape where the dummy gate layer 205 needs to be formed; the third patterned layer is mask, etch the dummy gate film until the surface of the isolation layer 204 , the fin portion 201 and the protective layer 212 a are exposed to form a dummy gate layer 205 .

In this embodiment, it also includes forming a dummy gate dielectric layer 213 on the surface of the isolation layer 204, the surface of the fin portion 201 and the surface of the protective layer 212a before forming the dummy gate film; The dummy gate film is formed on the surface.

In one embodiment, after the dummy gate film is etched, the dummy gate dielectric layer 213 is etched until the surfaces of the isolation layer 204 , the fin portion 201 and the protection layer 212 a are exposed. In another embodiment, after etching the dummy gate film, the dummy gate dielectric layer 213 is not etched.

The material of the dummy gate dielectric layer 213 is silicon oxide; the formation process of the dummy gate dielectric layer 213 is an atomic layer deposition process; the thickness of the dummy gate dielectric layer 213 is 5 angstroms to 15 angstroms. In this embodiment, the thickness of the dummy gate dielectric layer 213 is 10 angstroms. The dummy gate dielectric layer 213 is used to protect the surface of the fin portion 201 of the core region 220 when the dummy gate layer is subsequently removed.

In this embodiment, it also includes forming sidewalls on the sidewall surface of the dummy gate layer 205 ; forming source regions and drain regions in the fins 201 on both sides of the dummy gate layer 205 and sidewalls.

The material of the sidewall includes one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. The step of forming the sidewall includes: forming a sidewall film on the surface of the protective layer and the dummy gate layer 205 by using a deposition process; wall.

In one embodiment, the source region and the drain region are formed by ion implantation process. In another embodiment, the step of forming the source region and the drain region further includes: forming grooves in the fins 201 on both sides of the dummy gate layer 205 and sidewalls; A stress layer is formed in the groove; ions are doped in the stress layer to form a source region and a drain region. The doping process is one or a combination of ion implantation process and in-situ doping process.

When the formed fin transistor is a PMOS transistor, the material of the stress layer is silicon germanium, the ions doped in the stress layer are P-type ions, and the stress layer is a Σ-type stress layer. When the formed fin transistor is an NMOS transistor, the material of the stress layer is silicon carbide, and the ions doped in the stress layer are N-type ions.

Please refer to FIG. 11 , a dielectric layer 206 is formed on the surface of the isolation layer 204 and the fin portion 201, the dielectric layer 206 covers the sidewall of the dummy gate layer 205, and the dielectric layer 206 exposes the dummy gate layer. 205 top.

The step of forming the dielectric layer 206 includes: forming a dielectric film on the surface of the isolation layer 204, the fin portion 201, the protective layer 212a and the dummy gate layer 205; planarizing the dielectric film until the dummy gate layer 205 is exposed The dielectric layer 206 is formed until the top surface of the

The formation process of the dielectric film is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The material of the dielectric layer 206 is silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (dielectric coefficient is greater than or equal to 2.5, less than 3.9, such as porous silicon oxide, or porous silicon nitride) or ultra-low k-dielectric material (dielectric coefficient less than 2.5, such as porous SiCOH).

In this embodiment, the material of the dielectric layer 206 is silicon oxide; the formation process of the dielectric film is a fluid chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD for short) One or more of HDP) process, plasma enhanced deposition process.

Please refer to FIG. 12 , remove the dummy gate layer 205 (as shown in FIG. 11 ), form a first trench 214 in the dielectric layer 206 of the peripheral region 210, and form a first trench 214 in the dielectric layer 206 of the core region 220. the second groove 221 .

The process for removing the dummy gate layer 205 is one or a combination of a dry etching process and a wet etching process; wherein, the dry etching process is an isotropic dry etching process.

In this embodiment, the material of the dummy gate layer 205 is polysilicon, and the process of removing the dummy gate layer 205 is a plasma dry etching process; the parameters of the plasma dry etching process include: the gas includes: One or both of fluorocarbon gas, HBr and Cl ₂ , and a carrier gas, the fluorocarbon gas includes CF ₄ , CHF ₃ , CH ₂ F ₂ or CH ₃ F, and the carrier gas is an inert gas, such as He, the gas flow rate is 50 sccm-400 sccm, and the pressure is 3 millitorr-8 millitorr.

In the plasma dry etching process, since the protective layer 212a has high density and hardness, it is possible to prevent the first gate oxide layer 211a from being damaged by plasma. The protection layer 212a and the first gate oxide layer 211a remain in the fin transistors formed in the peripheral region 210, and since the protection layer 212a and the first gate oxide layer 211a are less damaged, it is beneficial to ensure that the peripheral region 210 The performance of the formed fin transistor is more stable.

In another embodiment, the process of removing the dummy gate layer is a wet etching process, and the etching solution of the wet etching process is a hydrofluoric acid solution.

Referring to FIG. 13 , the dummy gate dielectric layer 213 at the bottom of the first trench 214 and the second trench 221 (as shown in FIG. 12 ) is removed.

In this embodiment, the material of the dummy gate dielectric layer 213 is silicon oxide, and the process of removing the dummy gate dielectric layer 213 is a wet etching process or an isotropic dry etching process. When the dummy gate dielectric layer 213 is removed by a wet etching process, the etchant of the wet etching process is a hydrofluoric acid solution. When the dummy gate dielectric layer 213 is removed by an isotropic dry etching process, the isotropic dry etching process can be a SICONI process.

In this embodiment, since the material of the protective layer 212a is a high-K dielectric material, the etching selection between the protective layer 212a and the dummy gate dielectric layer 213 is relatively large, and the dummy gate layer 205 is removed by etching. , the protective layer 212a suffers less damage.

Referring to FIG. 14 , a second gate oxide layer 223 is formed on the exposed sidewalls and top surfaces of the fin 201 at the bottom of the second trench 221 .

The second gate oxide layer 223 is used as the gate oxide layer of the fin transistor formed in the core region 210 . The material of the second gate oxide layer 223 is silicon oxide; the formation process of the second gate oxide layer 223 is a thermal oxidation process or a wet oxidation process.

The thickness of the second gate oxide layer 223 is 3 nanometers to 10 nanometers. In this embodiment, the formation process of the second gate oxide layer 223 is a chemical oxidation process; the steps of the chemical oxidation process include: using an aqueous solution infused with ozone to expose the sidewalls and tops of the fins 201 The surface is oxidized, and a second gate oxide layer 223 is formed on the sidewall and top surface of the fin portion 201 . Wherein, in the aqueous solution fed with ozone, the concentration of ozone in water is 1%-15%.

Please refer to FIG. 15 , a first gate structure filling the first trench 214 (as shown in FIG. 14 ) is formed on the surface of the protection layer 212a; The second gate structure of the second trench 221 (as shown in FIG. 14 ) is described.

The first gate structure includes a first gate dielectric layer 215 and a first gate layer 216 located on the first gate dielectric layer 215, and the first gate layer 216 fills the first trench 214; The second gate structure includes a second gate dielectric layer 224 and a second gate layer 225 on the second gate dielectric layer 224 , and the second gate layer 225 fills the second trench 221 .

The forming steps of the first gate structure and the second gate structure include: forming a gate dielectric film on the surface of the dielectric layer 206, the inner wall surface of the first trench 214 and the inner wall surface of the second trench 221; After the gate dielectric film, a gate film filling the first trench 214 and the second trench 221 is formed; the gate film and the gate dielectric film are planarized until the surface of the dielectric layer 206 is exposed. A first gate dielectric layer 215 and a first gate layer 216 are formed in a trench 214 , and a second gate dielectric layer 224 and a second gate layer 225 are formed in a second trench 221 .

The material of the first gate dielectric layer 215 and the second gate dielectric layer 224 is a high-k dielectric material (dielectric coefficient greater than 3.9); the high-k dielectric material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, Zirconia silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide. The formation process of the gate dielectric film is an atomic layer deposition process.

The materials of the first gate layer 216 and the second gate layer 225 include copper, tungsten, aluminum or silver; the formation process of the gate film includes chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, Electroplating process or electroless plating process. The process of planarizing the gate film and the gate dielectric film is chemical mechanical polishing (CMP).

In one embodiment, before forming the gate film, it also includes forming a work function film on the surface of the gate dielectric film; forming a gate film on the surface of the work function film; after planarizing the gate film , planarizing the work function film until the surface of the dielectric layer 206 is exposed to form a work function layer. Materials of the work function layers formed in the first trench 214 and the second trench 221 can be the same or different.

In this embodiment, after forming the gate dielectric film and before forming the gate film, performing an annealing process is also included. The annealing process is used to eliminate defects or impurities inside and on the surface of the fin portion 201 , as well as inside the first gate oxide layer 211 , the second gate oxide layer 223 , the first gate dielectric layer 215 and the second gate dielectric layer 224 defects or impurities. Moreover, the annealing process can also be used to activate impurity ions in the source region and the drain region in the fin portion 201 .

To sum up, in this embodiment, a first gate oxide layer is formed on the sidewall and top surface of the fin in the peripheral region, and a protective layer is formed on the surface of the first gate oxide layer, and the dummy gate layer is formed on the Protective layer surface. When the dielectric layer is subsequently formed and the dummy gate layer is removed, the protection layer can be used to protect the first gate oxide layer from damage, avoiding the breakdown effect of the first gate oxide layer over time, thereby improving the formed The ability of the fin transistor to suppress the short channel effect increases the driving current, reduces the power consumption of the transistor, and suppresses the influence of the bias temperature instability effect. Moreover, since the dielectric coefficient of the protective layer is greater than that of the first gate oxide layer, the gap between the subsequently formed first gate structure and the fin can be reduced without increasing the threshold voltage of the fin transistor. carrier tunneling phenomenon. Therefore, the performance and reliability of the formed FinFET are improved.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. a kind of forming method of fin transistor, it is characterised in that including：

Substrate is provided, the substrate includes core space and external zones, the substrate of the core space and external zones Surface has fin respectively；

In substrate surface formation separation layer, the separation layer covers the partial sidewall of the fin, and The insulation surface is less than the top surface of the fin；

In fin side wall and top surface the first grid oxide layer of formation of external zones and positioned at first grid oxygen The protective layer of layer surface, the dielectric coefficient of the protective layer is more than the dielectric coefficient of first grid oxide layer；

In the formation of the separation layer, fin and protective layer respectively across the core space and external zones fin The pseudo- gate layer in portion, the pseudo- gate layer is covered on the side wall and top of the part fin；

In the separation layer and fin portion surface formation dielectric layer, the dielectric layer covers the side of the pseudo- gate layer Wall, and the dielectric layer exposes the pseudo- gate layer top；

The pseudo- gate layer is removed, first groove is formed in the dielectric layer of the external zones, in the core Second groove is formed in the dielectric layer in area；

Fin side wall and top surface the second grid oxide layer of formation gone out in the second groove bottom-exposed；

In the first grid structure of the full first groove of protective layer formation filling；

The second grid structure of the full second groove of filling is formed on the second grid oxide layer surface.

2. the forming method of fin transistor as claimed in claim 1, it is characterised in that first grid oxygen The forming step of layer and protective layer includes：Formed in the side wall and top surface of the fin exposed First grid oxygen film；In the first grid oxygen film and insulation surface formation diaphragm；In the guarantor of external zones Cuticula surface forms the first patterned layer；Using first patterned layer as mask, the core is etched The diaphragm in area and the first grid oxygen film, expose the side wall and top surface of core space fin, form the One grid oxide layer and protective layer；After the diaphragm and the first grid oxygen film of etching core space, remove described First patterned layer.

3. the forming method of fin transistor as claimed in claim 2, it is characterised in that the diaphragm Formation process is atom layer deposition process.

4. the forming method of fin transistor as claimed in claim 1, it is characterised in that also include：In shape Into before pseudo- gate layer, pseudo- gate dielectric layer is formed in the separation layer, fin and protective layer；Going After the pseudo- gate layer, the pseudo- gate dielectric layer of first groove and second groove bottom is removed.

5. the forming method of fin transistor as claimed in claim 4, it is characterised in that the pseudo- gate medium The formation process of layer is atom layer deposition process.

6. the forming method of fin transistor as claimed in claim 1, it is characterised in that the protective layer Material includes high K dielectric material.

7. the forming method of fin transistor as claimed in claim 6, it is characterised in that the protective layer Material includes：Al₂O₃、ZrO₂, HfO₂；The Al of nitrating₂O₃、ZrO₂Or HfO₂；Or, mix aluminium, The silica of yttrium, hafnium or nitrogen.

8. the forming method of fin transistor as claimed in claim 6, it is characterised in that the protective layer Dielectric coefficient is 6~20.

9. the forming method of fin transistor as claimed in claim 6, it is characterised in that the protective layer Thickness is 5 angstroms~25 angstroms.

10. the forming method of fin transistor as claimed in claim 1, it is characterised in that first grid oxygen The formation process of layer is situ steam generation technique.

11. the forming method of fin transistor as claimed in claim 1, it is characterised in that first grid oxygen The thickness of layer is 10 angstroms~35 angstroms.

12. the forming method of fin transistor as claimed in claim 1, it is characterised in that second grid oxygen The formation process of layer is thermal oxidation technology or wet process oxidation technology.

13. the forming method of fin transistor as claimed in claim 1, it is characterised in that remove the pseudo- grid The technique of layer is one or two kinds of combinations in wet-etching technology and dry etch process.

14. the forming method of fin transistor as claimed in claim 1, it is characterised in that the first grid Structure includes the first gate dielectric layer and the first grid layer on the first gate dielectric layer, described the The full first groove of one grid layer filling；The second grid structure include the second gate dielectric layer, with And the second grid layer on the second gate dielectric layer, full second ditch of second grid layer filling Groove.

15. the forming method of fin transistor as claimed in claim 14, it is characterised in that the first grid The forming step of structure and second grid structure includes：In the dielectric layer surface, first groove The inner wall surface formation gate dielectric film of wall surface and second groove；After gate dielectric film is formed, formed The gate electrode film of the filling full first groove and second groove；Planarize the gate electrode film and gate dielectric film Untill the dielectric layer surface is exposed, the first gate dielectric layer and first are formed in first groove Grid layer, forms the second gate dielectric layer and second grid layer in second groove.

16. the forming method of fin transistor as claimed in claim 1, it is characterised in that the top of the fin Portion surface also has mask layer.

17. the forming method of fin transistor as claimed in claim 16, it is characterised in that the substrate and fin The forming step in portion includes：Semiconductor base is provided；Formed in the part surface of the semiconductor base Mask layer, the mask layer covering needs to form the correspondence position of fin and shape；With the mask layer For mask, the semiconductor base is etched, the substrate and fin is formed.

18. the forming method of fin transistor as claimed in claim 16, it is characterised in that the separation layer Forming step includes：In the substrate and fin portion surface formation barrier film；Planarize the barrier film； After the barrier film is planarized, be etched back to the barrier film is up to exposing part fin side wall Only.

19. the forming method of fin transistor as claimed in claim 18, it is characterised in that described in being etched back to While barrier film or afterwards, the mask layer is removed.

20. the forming method of fin transistor as claimed in claim 1, it is characterised in that formed it is described every Before absciss layer, in the substrate and fin portion surface formation cushion oxide layer；Formed the separation layer it Afterwards, the cushion oxide layer exposed is removed.