CN109980003A - Semiconductor devices and forming method thereof - Google Patents

Abstract

A semiconductor device and a method for forming the same, the method comprising: providing a semiconductor substrate with a fin and an isolation structure on the semiconductor substrate, the isolation structure covering part of the sidewall of the fin; forming a first groove in the isolation structure, The sidewalls of the first recess expose the sidewalls of the fin; a dummy gate structure is formed across the fin, the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin; and a dummy gate is formed After the pole structure is formed, a second groove is formed in the fins on both sides of the dummy gate structure, the second groove is communicated with the first groove, and the bottom of the second groove is flush with the bottom of the first groove; A source-drain doped layer is formed in the groove and the second groove. The method improves the performance of the semiconductor device.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming the same.

Background technique

MOS (Metal-Oxide-Semiconductor) transistors are one of the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; Source and drain doped regions in the semiconductor substrate on both sides of the pole structure.

With the development of semiconductor technology, the control ability of traditional planar MOS transistors on channel current is weakened, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fin, Source and drain doped regions in the fins on both sides of the gate structure.

However, the performance of the semiconductor device formed by the fin field effect transistor in the prior art still needs to be improved.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.

In order to solve the above technical problems, the present invention provides a method for forming a semiconductor device, including: providing a semiconductor substrate, the semiconductor substrate has a fin and an isolation structure, and the isolation structure covers part of the sidewall of the fin; forming a first groove inside, the sidewalls of the first groove exposing the sidewalls of the fin; forming a dummy gate structure spanning the fin, the dummy gate structure covering part of the top surface and part of the fin sidewall surface; after the dummy gate structure is formed, a second groove is formed in the fins on both sides of the dummy gate structure, the second groove is communicated with the first groove, and the bottom of the second groove is connected with the first groove The bottom is flush; the source and drain doped layers are formed in the first groove and the second groove.

Optionally, the step of forming the first groove includes: forming a sacrificial layer covering the sidewalls of the fins on the isolation structure; after forming the sacrificial layer, performing ion implantation on the exposed isolation structure, A doped region is formed in the isolation structure; after the doped layer is formed, the sacrificial layer is removed; after the sacrificial layer is removed, the isolation structure is etched using the doped region as a mask, and the first layer is formed in the isolation structure a groove.

Optionally, the step of forming the second groove includes: after forming the dummy gate structure, forming fin spacers on the surface of the sidewalls of the fins; after forming the fin spacers, forming fin spacers on both sides of the dummy gate structure An initial second groove is formed in the initial second groove, and the sidewalls of the initial second groove expose the sidewalls of the fin spacers; the fin spacers of the sidewalls of the initial second groove are removed, and the fins on both sides of the dummy gate structure A second groove is formed in the top fin.

Optionally, the step of forming the sacrificial layer includes: forming an initial sacrificial layer on the surface of the fin; etching back the initial sacrificial layer until the surface of the fin is exposed, and forming a sacrificial layer on the surface of the sidewall of the fin Floor.

Optionally, the material of the sacrificial layer is different from that of the isolation structure.

Optionally, the material of the sacrificial layer includes: silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

Optionally, the thickness of the sacrificial layer is 2 nanometers to 8 nanometers.

Optionally, after the ion implantation is performed on the isolation structure and before the isolation structure is etched back, the isolation structure further includes annealing treatment; the temperature range of the annealing treatment is 800 degrees Celsius to 1100 degrees Celsius, and the annealing treatment The time for the annealing treatment is 5 seconds to 100 seconds, the gas used in the annealing treatment is nitrogen, and the flow rate of the nitrogen gas ranges from 10 sccm to 1000 sccm.

Optionally, the first ions include silicon ions.

Optionally, the parameters of the ion implantation include: an energy range of 5KeV to 30KeV, and a dose range of 1.0E14atom/cm ² to 1.0E16atom/cm ² .

Optionally, the process of removing the sacrificial layer includes a dry etching process or a wet etching process.

Optionally, the included angle from the side wall of the first groove to the bottom is rounded, and the side wall of the first groove is inclined.

Optionally, the process of etching back the isolation structure is an isotropic dry etching process or an isotropic wet etching process.

Optionally, the process parameters for dry etching back the isolation structure include: the gas used includes NH ₃ gas, NF ₃ gas and He, the flow rate of the NH ₃ gas is 100sccm～500sccm, and the flow rate of the NF ₃ gas is 20sccm～ 2000sccm, the flow rate of He is 500sccm～2000sccm, the pressure is 2torr～10torr, and the time is 20s～100s.

Optionally, the step of forming the fin spacer includes: after the dummy gate structure is formed, forming a spacer material layer on the fin and the dummy gate structure; and etching back the spacer material layer, Until the top surface of the dummy gate structure is exposed, fin spacers are formed on the sidewalls of the fins, and gate spacers are formed on the sidewalls of the gate structure.

Optionally, the formation process of the source and drain doped layers is an epitaxy process.

Optionally, when the type of the semiconductor device is a P-type device, the material of the source and drain doped layers includes: silicon, germanium or silicon germanium; when the type of the semiconductor device is an N-type device, the source The material of the drain doping layer includes: silicon, gallium arsenide or indium gallium arsenide.

Optionally, it further includes: after forming the source-drain doped layer, forming a dielectric layer on the semiconductor substrate, the dummy gate structure and the source-drain doped layer, the dielectric layer exposing the top surface of the dummy gate structure; forming a dielectric layer After layering, the dummy gate structure is removed to form a gate opening; after the gate opening is formed, a gate structure is formed in the gate opening.

Correspondingly, the present invention also provides a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate has a fin and an isolation structure, the isolation structure covers part of the sidewall of the fin; a first groove located in the isolation structure, so The sidewalls of the first groove expose the sidewalls of the fins; a dummy gate structure located on the fins, the dummy gate structures span the fins and cover part of the top surface and part of the sidewall surfaces of the fins; The source and drain doped layers are located in the fins on both sides of the dummy gate structure, and the source and drain doped layers are also located in the first grooves.

Optionally, the angle between the side wall of the first groove and the bottom is rounded, and the side wall of the first groove is inclined.

The present invention also provides a semiconductor device formed by any one of the above methods.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the formation method of the technical solution of the present invention, a first groove is formed in the isolation structure, a second groove is formed in the fin, a source-drain doped layer is formed in the first groove and the second groove, the source-drain The doped layer is partially located in the first groove and the second groove, so the volume of the source and drain doped layers higher than the isolation structure portion is relatively reduced, so that the top of the source and drain doped layers is higher than the surface of the isolation structure. Low, the height of the top of the source-drain doped layer relative to the top surface of the fin is also low. Subsequently, a gate structure will be formed at the position of the dummy gate structure. The gate structure and the source-drain doped layer are isolated by gate spacers, and the part of the source-drain doped layer higher than the top of the fin and the gate structure is separated. The parasitic capacitance is formed, the height of the part of the source-drain doped layer higher than the top of the fin is lower, the area where the gate structure and the source-drain doped layer intersect is smaller, and the parasitic capacitance between the two is smaller, thereby improving the device performance.

Further, the first groove is formed by using the doped layer as a mask to etch the isolation structure, and the first groove is formed by using the difference between the etching rates of the doped layer and the isolation structure without ion implantation when etching the isolation structure. a groove, so that the side walls of the first groove are relatively inclined. The source-drain doped layer is formed by epitaxial growth, and the inclined sidewall of the first groove defines the growth direction of the source-drain doped layer, so that the growth rate of the source-drain doped layer in the direction parallel to the surface of the semiconductor substrate is increased, thereby The source-drain doped layer grows wider in the horizontal direction along the plane of the semiconductor substrate, so that the height of the source-drain doped layer along the height direction of the fin is reduced, and the height of the part of the source-drain doped layer higher than the top of the fin is lower, The parasitic capacitance with the gate structure is smaller, thereby improving the performance of the device.

Description of drawings

1 is a schematic structural diagram of each step of a method for forming a semiconductor device;

FIG. 2 to FIG. 12 are schematic structural diagrams of the formation process of the semiconductor device according to the embodiment of the present invention.

Detailed ways

As mentioned in the background, semiconductor devices formed by the prior art have poor performance.

1 is a schematic structural diagram of a semiconductor device formation process;

Referring to FIG. 1, a semiconductor substrate 101 is provided, and the semiconductor substrate 101 has a plurality of fins 110; an isolation structure 102 is formed on the semiconductor substrate 101, and the isolation structure 102 covers part of the sidewall of the fins 110; A gate structure spanning the fins is formed on the fins 110 , and the gate structures cover part of the sidewalls and the top surface of the fins 110 ; sidewalls are formed on both sides of the gate structure, and the sidewalls cover sidewalls of the gate structure; grooves are formed in the fins and isolation structures on both sides of the gate structure and the sidewalls; source and drain doped layers 131 are epitaxially formed in the grooves.

The source and drain doped layers are formed by an epitaxial growth process. The bottom width of the grooves where the source and drain doped layers are located in the isolation structure is relatively small, which has a limiting effect along the plane direction perpendicular to the extension direction of the fins and parallel to the substrate direction. , so that the height of the source and drain doped layers is higher in the direction perpendicular to the extension direction of the fins and the direction perpendicular to the substrate. If the volume of the part is relatively large, the height of the source-drain doping layer along the height direction of the fin is relatively high, and the height of the top surface of the source-drain doping layer higher than the surface of the fin is higher. The source-drain doped layer and the gate structure formed subsequently are separated by sidewalls, and there is parasitic capacitance between the two. When the height of the source-drain doped layer is higher, the relative area between the source-drain doped layer and the gate structure The larger the value, the larger the parasitic capacitance, which affects the performance of the device.

On this basis, the present invention provides a method for forming a semiconductor device. A groove is formed at the junction of the fin and the isolation layer, the volume of the source-drain doping layer below the isolation structure is enlarged, and the volume of the source and drain doped layer below the isolation structure is reduced, and the volume above the isolation layer is reduced. The volume of the source and drain doped layers of the structure part, so that the height of the source and drain doped layers along the height direction of the fins is lower when the volume is determined, thereby reducing the gap between the source and drain doped layers and the gate structure formed subsequently The relative area of the device reduces the parasitic capacitance between the two, thereby improving the performance of the device.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 2 , a semiconductor substrate 201 is provided, and the semiconductor substrate 201 has fins 210 thereon.

In this embodiment, the material of the semiconductor substrate 201 is single crystal silicon. The semiconductor substrate 201 may also be polysilicon or amorphous silicon. The material of the semiconductor substrate 201 may also be semiconductor materials such as germanium, silicon germanium, and gallium arsenide.

In this embodiment, the fins 210 are formed by patterning the semiconductor substrate 201 . In other embodiments, a fin material layer may be formed on the semiconductor substrate, and then the fin material layer may be patterned to form the fin 210 .

In this embodiment, the material of the fin portion 210 is single crystal silicon. In other embodiments, the material of the fin is single crystal germanium silicon or other semiconductor materials. The number of the fins 210 is one or more.

In this embodiment, a pad mask layer 203 located on the top of the fin is also included, and the material of the pad mask layer 203 is silicon nitride. The pad mask layer 203 serves as a planarization stop layer in the subsequent process of forming the isolation structure.

Referring to FIG. 3 , an isolation structure 202 is formed on the semiconductor substrate 201 , and the isolation structure 203 covers part of the sidewall surface of the fin 210 .

The steps of forming the isolation structure 202 include: forming an initial isolation film on the substrate 201 , the initial isolation film covering the top surface of the fins 210 ; planarizing the initial isolation film until the fins 210 are exposed The surface of the top liner mask layer 203 ; the initial isolation film is etched back to expose part of the sidewalls of the fins 210 to form the isolation structure 202 . The isolation structures 202 are used to electrically isolate adjacent fins 210 .

The material of the initial isolation film includes silicon oxide or silicon nitride.

In this embodiment, the material of the initial isolation film is silicon oxide; the thickness of the initial isolation film after etching back is 1/4˜1/2 of the height of the fin portion 210 . The formation process of the initial isolation film is a fluid chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD for short).

In other embodiments, the initial isolation film can also employ plasma enhanced chemical vapor deposition (PECVD) or high aspect ratio chemical vapor deposition (HARP).

The planarization process is a chemical mechanical polishing process (CMP); in this embodiment, the chemical mechanical polishing process is performed until the surface of the pad mask layer 203 on top of the fins 202 is exposed.

The process of etching back the initial isolation film is one or a combination of a wet etching process or a dry etching process.

In this embodiment, the material of the isolation structure 202 is silicon oxide.

After the isolation structure is formed, a first groove is formed in the isolation structure, and the sidewalls of the first grooves expose the sidewalls of the fins.

The step of forming the first groove includes: forming a sacrificial layer covering the sidewalls of the fins on the isolation structure; after forming the sacrificial layer, performing ion implantation on the isolation structure exposed by the sacrificial layer, and performing ion implantation on the isolation structure. forming a doped region; after forming the doped layer, removing the sacrificial layer; after removing the sacrificial layer, using the doped region as a mask, etching the isolation structure, and forming the first a groove. For details, please refer to FIG. 4 to FIG. 7 .

Referring to FIG. 4 , after the isolation structure 202 is formed, a sacrificial layer 220 is formed on the sidewall of the fin portion 210 , and the sacrificial layer 220 covers the sidewall surface of the fin portion 210 .

The sacrificial layer 220 is used to define the width of the first groove 204 formed subsequently, and to protect the isolation structure 202 under the sacrificial layer 220 during subsequent ion implantation.

The steps of forming the sacrificial layer 220 include: forming an initial sacrificial layer (not shown) on the fin portion 210 and the isolation structure 202 ; etching back the initial sacrificial layer to form a sacrificial layer on the sidewall surface of the fin portion 210 220.

The formation process of the initial sacrificial layer includes a deposition process, and the deposition process includes a chemical vapor deposition process or an atomic layer deposition process.

The material of the sacrificial layer 220 includes: silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

The material of the sacrificial layer 220 is different from that of the isolation structure 202 . When the sacrificial layer 220 is subsequently removed, it can ensure that the sacrificial layer 220 is removed while reducing damage to the isolation structure 202 .

In this embodiment, the material of the sacrificial layer 220 is silicon nitride.

In this embodiment, the thickness of the sacrificial layer 220 is 2 nanometers to 8 nanometers.

When the thickness of the sacrificial layer 220 is less than 2 nm, the width of the first groove 204 formed subsequently is small, the width of the bottom of the source-drain doped layer 251 formed subsequently is small, and the height cannot be reduced, which is different from the gate structure formed subsequently. The parasitic capacitance between them is relatively large; when the thickness of the sacrificial layer 220 is greater than 8 nm, the width of the subsequently formed first groove 204 is too wide, the bottom of the subsequently formed source and drain doped layers 251 is too large, and the adjacent source and drain doped layers 251 are too wide. Bridges are prone to occur between them, which in turn affects device performance.

Referring to FIG. 5 , after the sacrificial layer 220 is formed, ion implantation is performed on the isolation structure 202 exposed by the sacrificial layer 220 to form a doped region 230 in the isolation structure 202 .

Ion implantation is performed on the isolation structure 202 .

The substrate mask layer 203 protects the fins 210 during ion implantation.

After the doped region 230 is formed, the isolation structure 202 is subsequently etched using the doped region 230 as a mask. The etching rate of the doped region 230 is relatively slow, and the isolation structure 202 that is not ion-implanted is not etched. The etching rate is faster. Under the same etching conditions, the etching rates of the two are different, resulting in a deeper depth of the isolation structure 202 that is not ion implanted, thereby forming the first groove 204, which is the subsequent source and drain doping layer. Form provides space.

The implanted ions are first ions, and the first ions include carbon ions.

In this embodiment, the first ions are carbon ions, and the parameters of the ion implantation include: an energy range of 5KeV to 30KeV, and a dose range of 1.0E14atom/cm ² to 1.0E16atom/cm ² .

In this embodiment, after the ion implantation, the isolation structure 202 is annealed. The temperature of the annealing treatment is 800 degrees Celsius to 1100 degrees Celsius, and the annealing treatment time is 5 seconds to 100 seconds. The gas used is nitrogen, and the flow rate of the nitrogen ranges from 10 sccm to 1000 sccm.

The depth of the doped region 230 needs to be greater than 1 nm to ensure a good blocking effect during subsequent etching.

In other embodiments, the isolation structure 202 is not annealed after the ion implantation.

Referring to FIG. 6 , after the annealing process, the sacrificial layer 220 on the sidewalls of the fins 210 is removed to expose the sidewall surfaces and the top surfaces of the fins 210 .

The material of the sacrificial layer 220 is silicon nitride, and the material of the substrate mask layer 203 is also silicon nitride. During the process of removing the sacrificial layer 220, the liner mask on the top of the fins 210 is also removed. film layer 203 , thereby exposing sidewall surfaces and top surfaces of the fins 210 .

In this embodiment, the process of removing the sacrificial layer 220 is an isotropic wet etching process, and the wet etching generally adopts a phosphoric acid etching solution formed by a mixture of phosphoric acid and deionized water, wherein the volume percentage of phosphoric acid is The concentration is 80% to 90%, such as 86% to 87%, and the process temperature is in the range of 90 degrees Celsius to 180 degrees Celsius, such as 160 degrees Celsius.

The material of the sacrificial layer 220 is silicon nitride, the material of the isolation structure 202 is silicon oxide, and phosphoric acid has a good etching selectivity ratio of silicon oxide and silicon nitride, which can ensure that the sacrificial layer 220 is removed while reducing the impact on isolation. Damage to structure 202.

In other embodiments, the sacrificial layer 220 is removed by a dry etching process.

Referring to FIG. 7 , after removing the sacrificial layer 220 , the isolation structure 202 is etched by using the doped region 230 as a mask to form a first groove 204 .

Ion implantation is performed on the isolation structure 202 exposed by the sacrificial layer 220, and a doped region 230 is formed in the isolation structure 202. The etching rate of the doped region 230 is relatively slow, and the etching rate of the isolation structure 202 in the portion that is not ion-implanted Faster, under the same etching conditions, the etching rates of the two are different, resulting in a deeper etching depth of the isolation structure 202 located under the sacrificial layer 220 that is not ion-implanted, thereby forming the first groove 204, which is The subsequent source and drain doped layers 251 are formed to provide space.

The process of etching the isolation structure 202 includes: an isotropic dry etching process or an isotropic wet etching process.

In this embodiment, the process of etching the isolation structure 202 is a dry etching process, and the dry etching parameters include: the gas used includes NH ₃ gas, NF ₃ gas and He, and the flow rate of the NH ₃ gas is 100sccm～500sccm, the flow rate of NF ₃ gas is 20sccm～2000sccm, the flow rate of He is 500sccm～2000sccm, the pressure is 2torr～10torr, and the time is 20s～100s.

In other embodiments, the process of etching the isolation structure 202 is an isotropic wet etching process.

Since the process of etching the isolation structure is an isotropic dry etching process, the etching rate in all directions is the same, but since the dopant ions in the doped region 230 are annealed, they will go to the isolation structure located under the sacrificial layer 220. 202 diffuses, and with the deepening of the depth, the concentration of doping ions decreases, and the higher the concentration of doping ions, the slower the etching rate, so the angle between the sidewall and the bottom of the first groove 204 is rounded, and The sidewall of the first groove 204 is inclined.

The source-drain doped layer 251 is formed by epitaxial growth, and the inclined sidewalls of the first groove 204 define the growth direction of the source-drain doped layer 251, so that the source-drain doped layer 251 is in a horizontal direction parallel to the surface of the semiconductor substrate. The growth rate of the fins increases, so that the source-drain doped layer 251 grows wider in the horizontal direction along the plane of the semiconductor substrate, so that the height of the source-drain doped layer 251 along the height direction of the fins 210 decreases, which is different from the gate structure formed subsequently. The inter-parasitic capacitance is small, thereby improving the performance of the device.

After the first groove 204 is formed, a dummy gate structure (not shown) across the fin 210 is formed on the fin 210 , and the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin 210 , The dummy gate dielectric layer 205 covers the sidewalls of the fins.

Referring to FIG. 8 , a dummy gate dielectric layer 205 is formed on the isolation structure 202 and the fins 210 ; a dummy gate layer (not shown) is formed on the dummy gate dielectric layer 205 .

The steps of forming the dummy gate layer include: forming a dummy gate film on the dummy gate dielectric layer 205, forming a patterned layer on the surface of the dummy gate film, and the patterned layer covers the dummy gate that needs to be formed The position and shape of the layer; using the patterned layer as a mask, the dummy gate film is etched until the surface of the dummy gate dielectric layer 205 is exposed.

The material of the dummy gate dielectric layer 205 is silicon oxide.

In this embodiment, the formation process of the dummy gate dielectric layer 205 is an in-situ vapor generation process. The dummy gate dielectric layer 205 formed by the in-situ vapor generation process has a good step coverage capability, so that the formed dummy gate dielectric layer 205 can closely cover the sidewall surface of the fin 210, and the formed dummy gate dielectric layer 205 can The thickness of the gate dielectric layer 205 is uniform.

In another embodiment, the formation process of the dummy gate dielectric layer 205 is a chemical oxidation process; the steps of the chemical oxidation process include: using an ozone-infused aqueous solution to expose sidewalls and tops of the fins 210 The surface is oxidized to form a dummy gate dielectric layer 205 .

In this embodiment, the dummy gate layer is located on the dummy gate dielectric layer 205 , and the material of the dummy gate layer includes silicon, amorphous silicon, polysilicon or doped polysilicon. The formation process of the dummy gate film includes a chemical vapor deposition process or a physical vapor deposition process.

After the dummy gate structure is formed, a second groove is formed in the fins on both sides of the dummy gate structure, and the bottom surface of the second groove is lower than the top surface of the isolation structure; the forming step of the second groove includes: forming a dummy After the gate structure is formed, fin spacers are formed on the sidewalls of the fins, and the fin spacers cover the surface of the fin sidewalls; after the fin spacers are formed, initial first spacers are formed in the fins on both sides of the dummy gate structure. Two grooves, the initial second groove exposes the sidewall of the fin sidewall; the fin sidewall of the sidewall of the initial second groove is removed to form a second groove in the isolation structure. For details, please refer to FIG. 9 to FIG. 11 .

Referring to FIG. 9 , after the dummy gate structure is formed, fin spacers 231 are formed on the sidewalls of the fins 210 , and the fin spacers 231 cover the sidewall surfaces of the fins 210 .

The step of forming the fin spacer 231 includes: after forming the dummy gate structure, forming a spacer material layer (not shown) on the isolation structure 202 , the fin 210 and the dummy gate structure (not shown) ; Etch back the spacer material layer to form fin spacers 231 on the sidewalls of the fins 210 ; at the same time, form gate spacers on the sidewalls of the dummy gate structure.

The process for forming the sidewall material layer is a deposition process, including: a plasma chemical vapor deposition process, an atomic layer deposition process or a low pressure chemical vapor deposition process.

In this embodiment, the formation process of the sidewall material layer is an atomic layer deposition process, and the process parameters include: the gas used is a mixed gas of SiH ₂ Cl ₂ and NH ₃ , and the flow rate of the mixed gas is 1500 sccm to 4000 sccm, The pressure is 1 mtorr to 10 mtorr, the temperature is 200 degrees Celsius to 600 degrees Celsius, and the deposition times are 30 to 100 times.

In this embodiment, the formed device is a P-type device, and the fin spacer is formed by etching back the spacer material layer. In other embodiments, the formed device is an N-type device, and the fin spacer is formed by etching back the spacer material layer.

In other embodiments, when the formed device includes a P-type device and an N-type device, a P-type spacer material layer is formed to cover the P-type dummy gate structure and the N-type gate structure; the two sides of the P-type device dummy gate structure are removed. The P-type sidewall material layer above the fins exposes the fins on both sides of the dummy gate structure of the P-type device; then the fins on both sides of the dummy gate structure of the P-type device are removed to form grooves; P-type devices are formed in the grooves Type source and drain doped layers; then, an N-type spacer material layer is formed on the dummy gate structure and the source-drain doped layers of the P-type device, and the P-type side above the fins on both sides of the dummy gate structure of the N-type device is removed The wall material layer and the N-type spacer material layer expose the fins on both sides of the dummy gate structure of the N-type device; then remove the fins on both sides of the dummy gate structure of the N-type device to form grooves; form grooves in the grooves N-type source and drain doped layers.

Referring to FIG. 10 , after the fin spacers 231 are formed, initial second grooves 206 are formed in the fins 210 on both sides of the dummy gate structure, and the initial second grooves 206 expose the sidewalls of the fin spacers 231 .

The bottom surface of the initial second groove 206 is flush with the bottom surface of the first groove 204 and lower than the top surface of the isolation structure 202 .

The process of etching and removing the fins 210 on both sides of the dummy gate structure is anisotropic dry etching. The parameters of the dry etching include: the etching gas is HBr, O ₂ and Cl ₂ , and He is also introduced into the etching chamber, the pressure of the etching chamber is 2 mtorr to 50 mtorr, the source of the etching is Power is 200 watts to 2000 watts, etch plus bias power is 10 watts to 100 watts, HBr flow is 50sccm to 500sccm, O flow is _2sccm to 20sccm, Cl flow is 10sccm to _300sccm , He flow is 50sccm to 500sccm .

Referring to FIG. 11 , the fin spacers 231 on the sidewalls of the initial second grooves 206 are removed, and second grooves 207 are formed in the fins 210 on both sides of the dummy gate structure.

The bottom surface of the second groove 207 is lower than the top surface of the isolation structure 202 . The second groove 207 provides space for the subsequent formation of the source and drain doped layers 251. The second groove 207 is formed by removing the fin spacers 231 of the sidewalls of the initial second groove 206 , so the bottom surface of the second groove 207 is flush with the bottom surface of the first groove 204 and is lower than the isolation structure 202 on the top surface. In the process of forming the source-drain doped layer 251, the source-drain doped layer 251 will first fill the first groove 204 and the second groove 207 in the isolation structure, and then grow above the isolation structure 202, so the volume is determined. The height of the source-drain doping layer 251 formed above the isolation structure 202 is relatively low, so the height of the top of the source-drain doping layer 251 relative to the top surface of the fin 210 is also relatively low. The relative area of the gate layer is small, and the parasitic capacitance between the two is relatively small.

The process of removing the fin sidewall 231 is an isotropic wet etching process, and the wet etching generally adopts a phosphoric acid etching solution formed by a mixture of phosphoric acid and deionized water, wherein the volume percent concentration of phosphoric acid is 80. % to 90%, such as 86% to 87%, and the process temperature is within the range of 90 degrees Celsius to 180 degrees Celsius, such as 160 degrees Celsius.

The material of the fin sidewall is silicon nitride, and the material of the isolation structure is silicon oxide. Thermal phosphoric acid has a good selectivity ratio for the etching of silicon nitride and silicon oxide, which can ensure that the fin sidewall is removed as much as possible. Possible reduction of damage to isolation structures.

Referring to FIG. 12 , after the second groove 207 is formed, a source-drain doped layer 251 is formed in the first groove 204 and the second groove 207 .

When the type of the semiconductor device is a P-type device, the material of the source-drain doping layer 251 includes: silicon, germanium or silicon germanium; when the type of the semiconductor device is an N-type device, the source-drain doping layer 251 is doped The material of the layer 251 includes: silicon, gallium arsenide or indium gallium arsenide.

In this embodiment, the semiconductor device is a P-type device, and the material of the source-drain doping layer 251 is silicon germanium. In other embodiments, the semiconductor device is an N-type device, and the material of the source-drain doping layer 251 is silicon.

The first groove 204 is located in the isolation structure 202, the second groove 207 is partially located in the isolation structure 202, and the source-drain doped layer 251 is partially located in the first groove 204 and the second groove 207. When the volume of 251 is determined, the volume of the source-drain doped layer 251 higher than the part of the isolation structure 202 is relatively reduced, so that the height of the top of the source-drain doped layer 251 relative to the surface of the isolation structure 202 is lower. The height of the top of the source-drain doped layer 251 relative to the top surface of the fins 210 is also low. Next, a gate structure will be formed at the position of the dummy gate structure. The gate structure and the source-drain doped layer 251 are separated by gate spacers. The part of the source-drain doped layer 251 higher than the top of the fin 210 and the gate are separated. A parasitic capacitance is formed between the structures, the height of the part of the source-drain doping layer 251 higher than the top of the fin 210 is relatively low, the area where the gate structure and the source-drain doping layer 251 intersect is small, and the parasitic capacitance between the two is relatively small. small, thereby improving the performance of the device.

The first groove 251 is formed by etching the isolation structure 202 by using the doped layer 230 as a mask. When etching the isolation structure 202, the etching rate of the doped layer 230 and the isolation structure 202 that is not ion implanted is used to etch the isolation structure 202. The first groove 204 is formed by the difference, so that the sidewall of the first groove 204 is inclined. The source-drain doped layer 251 is formed by epitaxial growth, and the inclined sidewalls of the first groove 204 define the growth direction of the source-drain doped layer 251 , so that the source-drain doped layer 251 is in a horizontal direction parallel to the surface of the semiconductor substrate 201 . The growth rate of the fins is increased, so that the source-drain doped layer 251 grows wider in the horizontal direction along the plane of the semiconductor substrate 201, so that the height of the source-drain doped layer 251 along the height direction of the fin 210 decreases, and the source-drain doped layer 251 The height of the portion above the top of the fin 210 is lower, and the parasitic capacitance with the gate structure is smaller, thereby improving the performance of the device.

After the source-drain doped layer 251 is formed, a dielectric layer is formed on the semiconductor substrate 201, the fins 210, the isolation structure 202, the dummy gate structure and the source-drain doped layer 251, and the dielectric layer exposes the top of the dummy gate structure surface; after the dielectric layer 251 is formed, the dummy gate structure is removed to form a gate opening; after the gate opening is formed, a gate structure is formed in the gate opening.

Correspondingly, the present embodiment also provides a semiconductor device, please refer to FIG. 12 , including: a semiconductor substrate 201 , the semiconductor substrate 201 has a fin 210 and an isolation structure 202 , and the isolation structure 202 covers part of the sidewall of the fin 210 ; a first groove 204 located in the isolation structure 202, the first groove 204 is adjacent to the sidewall of the fin 210, and the bottom surface of the first groove 204 is lower than the surface of the isolation structure 202; located on the fin 210 The gate structure, the gate structure spans the fin 210 and covers part of the top surface and part of the sidewall surface of the fin 210; the source and drain doped layers 251 in the fin 210 on both sides of the gate structure , the source-drain doped layer 251 is also located in the first groove 204 .

In the semiconductor device, the included angle from the side wall of the first groove to the bottom is rounded, and the side wall of the first groove is inclined.

The material, size and structure of the source-drain doping layer 251 refer to the foregoing embodiments.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. A method for forming a semiconductor device, comprising: A semiconductor substrate is provided, the semiconductor substrate has a fin and an isolation structure, and the isolation structure covers part of the sidewall of the fin; forming a first groove in the isolation structure, and the sidewalls of the first grooves expose the sidewalls of the fins; forming a dummy gate structure spanning the fin, the dummy gate structure covering a portion of the top surface and a portion of the sidewall surface of the fin; After the dummy gate structure is formed, a second groove is formed in the fins on both sides of the dummy gate structure, the second groove is communicated with the first groove, and the bottom of the second groove is flush with the bottom of the first groove; A source-drain doped layer is formed in the first groove and the second groove. 2 . The method for forming a semiconductor device according to claim 1 , wherein the step of forming the first groove comprises: forming a sacrificial layer on the isolation structure covering the sidewall of the fin; After the sacrificial layer, ion implantation is performed on the isolation structure exposed by the sacrificial layer, and a doped region is formed in the isolation structure; after the doped region is formed, the sacrificial layer is removed; after the sacrificial layer is removed, the doped region is As a mask, the isolation structure is etched, and a first groove is formed in the isolation structure. 3 . The method for forming a semiconductor device according to claim 1 , wherein the forming step of the second groove comprises: after forming the dummy gate structure, forming a fin sidewall spacer on the surface of the sidewall of the fin; forming After the spacers of the fins, initial second grooves are formed in the fins on both sides of the dummy gate structure, and the sidewalls of the initial second grooves expose the sidewalls of the spacers of the fins; the sidewalls of the initial second grooves are removed The fin spacers are formed, and second grooves are formed in the fins on both sides of the dummy gate structure. 4 . The method for forming a semiconductor device according to claim 2 , wherein the step of forming the sacrificial layer comprises: forming an initial sacrificial layer on the surface of the fin; and etching back the initial sacrificial layer until exposed. 5 . A sacrificial layer is formed on the surface of the sidewall of the fin. 5. The method for forming a semiconductor device according to claim 2, wherein the material of the sacrificial layer is different from that of the isolation structure. 6. The method for forming a semiconductor device according to claim 2, wherein the material of the sacrificial layer comprises: silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. 7 . The method for forming a semiconductor device according to claim 2 , wherein the sacrificial layer has a thickness of 2 nanometers to 8 nanometers. 8 . 8 . The method for forming a semiconductor device according to claim 2 , wherein after ion implanting the isolation structure and before etching the isolation structure back, further comprising annealing the isolation structure; the annealing The temperature range of the treatment is 800 degrees Celsius to 1100 degrees Celsius, the time of the annealing treatment is 5 seconds to 100 seconds, the gas used in the annealing treatment is nitrogen, and the flow rate of the nitrogen gas ranges from 10 sccm to 1000 sccm. 9. The method of forming a semiconductor device according to claim 2, wherein the first ions comprise silicon ions. 10 . The method for forming a semiconductor device according to claim 9 , wherein the parameters of the ion implantation include: an energy range of 5KeV˜30KeV, and a dose range of 1.0E14atom/cm ² to 1.0E16atom/cm ² . 11. The method for forming a semiconductor device according to claim 2, wherein the process of removing the sacrificial layer comprises a dry etching process or a wet etching process. 12 . The method for forming a semiconductor device according to claim 1 , wherein an included angle from the side wall of the first groove to the bottom is rounded, and the side wall of the first groove is inclined. 13 . 13 . The method for forming a semiconductor device according to claim 2 , wherein the process of etching the isolation structure comprises: an isotropic dry etching process or an isotropic wet etching process. 14 . 14 . The method for forming a semiconductor device according to claim 13 , wherein the process parameters of dry etching the isolation structure include: the gas used includes NH ₃ gas, NF ₃ gas and He, NH ₃ gas. 15 . The flow rate is 100sccm～500sccm, the flow rate of NF ₃ gas is 20sccm～2000sccm, the flow rate of He is 500sccm～2000sccm, the pressure is 2torr～10torr, and the time is 20s～100s. 15 . The method for forming a semiconductor device according to claim 3 , wherein the step of forming the fin spacer comprises: after the dummy gate structure is formed, forming on the fin and the dummy gate structure. 16 . A spacer material layer; the spacer material layer is etched back until the top surface of the dummy gate structure is exposed, fin spacers are formed on the sidewalls of the fins, and gate spacers are formed on the sidewalls of the gate structure. 16 . The method for forming a semiconductor device according to claim 1 , wherein the formation process of the source and drain doped layers is an epitaxy process. 17 . 17. The method for forming a semiconductor device according to claim 1, wherein when the type of the semiconductor device is a P-type device, the material of the source and drain doped layers comprises: silicon, germanium or silicon germanium; When the type of the semiconductor device is an N-type device, the material of the source and drain doped layers includes: silicon, gallium arsenide or indium gallium arsenide. 18. The method for forming a semiconductor device according to claim 1, further comprising: forming a dielectric layer on the semiconductor substrate, the dummy gate structure and the source-drain doped layer after forming the source-drain doped layer, The dielectric layer exposes the top surface of the dummy gate structure; after the dielectric layer is formed, the dummy gate structure is removed to form a gate opening; after the gate opening is formed, the gate structure is formed in the gate opening. 19. A semiconductor device, characterized in that it comprises: a semiconductor substrate, the semiconductor substrate is provided with a fin and an isolation structure, and the isolation structure covers part of the sidewall of the fin; a first groove in the isolation structure, the sidewalls of the first grooves expose the sidewalls of the fins; a dummy gate structure on the fin, the dummy gate structure spanning the fin, covering part of the top surface and part of the sidewall surface of the fin; The source and drain doped layers are located in the fins on both sides of the dummy gate structure, and the source and drain doped layers are also located in the first grooves. 20 . The semiconductor device of claim 19 , wherein the included angle from the side wall of the first groove to the bottom is rounded, and the side wall of the first groove is inclined. 21 .