CN108538724A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate and discrete fins located on the substrate; forming an isolation structure covering part of the sidewall of the fin on the substrate; after forming the isolation structure, forming a cross-fin and a dummy gate structure covering the top and sidewall surfaces of the fin part; forming sidewalls on the sidewalls of the dummy gate structure; after forming the sidewalls, forming grooves in the fins on both sides of the dummy gate structure; forming in the grooves Doped epitaxial layer; after the doped epitaxial layer is formed, an interlayer dielectric layer is formed on the isolation structure exposed by the dummy gate structure, and the interlayer dielectric layer exposes the top of the dummy gate structure; the dummy gate structure is removed to form an opening in the interlayer dielectric layer ; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; after removing the barrier layer, filling the opening with a metal layer to form a metal gate structure. The present invention uses the blocking layer to isolate the doped epitaxial layer and the metal layer, thereby reducing the probability of bridging between the metal gate structure and the doped epitaxial layer.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background technique

In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to accommodate the reduction in feature size, the channel length of MOSFETs has also been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to better adapt to the reduction of the feature size, the semiconductor process gradually begins to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate can control the ultra-thin body (fin) from at least two sides. Compared with the planar MOSFET, the gate has stronger control ability on the channel, which can well suppress the short channel effect; and the FinFET is relatively For other devices, it has better compatibility with existing integrated circuit manufacturing.

However, the electrical performance and yield of semiconductor devices formed in the prior art still need to be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor structure and its forming method to optimize the electrical performance and yield of semiconductor devices.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a base, the base includes a substrate and discrete fins located on the substrate; forming a fin on the substrate where the fins are exposed an isolation structure, the isolation structure covers part of the sidewall of the fin, and the top of the isolation structure is lower than the top of the fin; after the isolation structure is formed, a dummy gate structure across the fin is formed, The dummy gate structure covers part of the top surface and the sidewall surface of the fin; sidewalls are formed on the sidewalls of the dummy gate structure; after the sidewalls are formed, the fins on both sides of the dummy gate structure A groove is formed in the groove; a doped epitaxial layer is formed in the groove; after the doped epitaxial layer is formed, an interlayer dielectric layer is formed on the isolation structure exposed by the dummy gate structure, and the interlayer dielectric layer is exposed The top of the dummy gate structure; removing the dummy gate structure, forming an opening in the interlayer dielectric layer; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; removing the opening After the barrier layer is formed, a metal layer is filled in the opening to form a metal gate structure.

Correspondingly, the present invention also provides a semiconductor structure, comprising: a base, the base includes a substrate and discrete fins located on the substrate; an isolation structure is located on the substrate where the fins are exposed, the The isolation structure covers part of the sidewall of the fin, and the top of the isolation structure is lower than the top of the fin; the interlayer dielectric layer on the isolation structure has a structure in the interlayer dielectric layer that exposes the fin and the opening of the isolation structure; the doped epitaxial layer is located in the fins on both sides of the opening; the sidewall is located on the side wall of the opening; the barrier layer is located at the bottom of the opening.

Compared with the prior art, the technical solution of the present invention has the following advantages:

The present invention provides a method for forming a semiconductor structure, including: providing a base, the base including a substrate and discrete fins located on the substrate; forming an isolation structure on the substrate where the fins are exposed; forming lateral A dummy gate structure spanning the fin; sidewalls are formed on the sidewalls of the dummy gate structure; after the sidewalls are formed, grooves are formed in the fins on both sides of the dummy gate structure; A doped epitaxial layer is formed in the groove; after the doped epitaxial layer is formed, an interlayer dielectric layer is formed on the isolation structure exposed by the dummy gate structure, and the interlayer dielectric layer exposes the top of the dummy gate structure; The dummy gate structure, forming an opening in the interlayer dielectric layer; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; after removing the barrier layer in the opening, The opening is filled with a metal layer to form a metal gate structure. During the process of forming grooves in the fins on both sides of the dummy gate structure, since the isolation structure is exposed to the etching process environment for etching the fins, the etching process is easy to damage the dummy gate. The isolation structure exposed by the structure and the fins, and the isolation structure below the sidewall cause etching loss, resulting in the occurrence of gaps under the sidewall caused by the loss of the isolation structure; in the process of forming the barrier layer, the present invention , the barrier layer also fills the gap, and under the protection of the sidewall, after removing the barrier layer in the opening, the barrier layer in the gap is retained; therefore, in the When the opening is filled with a metal layer, the barrier layer in the gap can function to isolate the doped epitaxial layer from the metal layer, and the metal gate structure and the doped epitaxial layer are bridged. The probability is low, that is, through the solution of the present invention, the problem of bridging between the doped epitaxial layer and the metal gate structure can be improved, thereby improving the electrical performance and yield of the semiconductor device.

In an optional solution, the material of the barrier layer is silicon oxide, silicon nitride or silicon oxynitride, and the material of the barrier layer is a dielectric material, so it has high process compatibility, so it can avoid electrical damage to the semiconductor device. performance and yield are adversely affected.

The present invention provides a semiconductor structure, which includes: a base, the base includes a substrate and discrete fins on the substrate; an isolation structure on the substrate exposed by the fins, the The isolation structure covers part of the sidewall of the fin, and the top of the isolation structure is lower than the top of the fin; an interlayer dielectric layer on the isolation structure, the interlayer dielectric layer has the fin and the opening of the isolation structure; the doped epitaxial layer is located in the fins on both sides of the opening; the side wall is located on the side wall of the opening; the barrier layer is located at the bottom of the opening. During the semiconductor manufacturing process, the process of forming the doped epitaxial layer easily causes etching loss to the isolation structure, and also easily causes etching loss to the isolation structure below the sidewall, resulting in A gap generated by the loss of the isolation structure occurs; during the formation of the barrier layer, the barrier layer also fills the gap, and under the protection of the sidewall, when the When the barrier layer is used, the barrier layer in the gap can be retained; and the semiconductor manufacturing process also includes filling the metal layer in the opening to form a metal gate structure, so when filling the metal layer in the opening, the The barrier layer in the gap can function to isolate the doped epitaxial layer from the metal layer, and the probability of bridging between the metal gate structure and the doped epitaxial layer is low, that is, through the present invention The semiconductor structure can improve the problem of bridging between the doped epitaxial layer and the metal gate structure, thereby improving the electrical performance and yield of the semiconductor device.

Description of drawings

FIG. 1 and FIG. 2 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure;

3 to 33 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

It can be seen from the background art that the electrical performance and yield of semiconductor devices still need to be improved. Analyze the reasons for this:

Referring to FIG. 1 and FIG. 2 together, it shows a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure. FIG. 1 is a perspective view, and FIG. 2 is based on FIG. A schematic diagram of the cross-sectional structure as shown by the X1X2 secant line in FIG. 1 .

Referring to FIG. 1 , a base is provided, the base includes a substrate 10 and discrete fins 11 located on the substrate 10; an isolation structure 12 is formed on the substrate 10 exposed by the fins 11, and the isolation structure 12 Part of the sidewall of the fin 11 is covered, and the top of the isolation structure 12 is lower than the top of the fin 11; after the isolation structure 12 is formed, a dummy gate structure 13 across the fin 11 is formed, so The dummy gate structure 13 covers part of the top surface and the sidewall surface of the fin portion 11 ; sidewalls 14 are formed on the sidewall of the dummy gate structure 13 .

Referring to FIG. 2 , after forming the sidewalls 14, the fins 11 on both sides of the dummy gate structure 13 (as shown in FIG. 1 ) are etched to form grooves (not shown) in the fins 11. ; forming a doped epitaxial layer 15 in the groove.

After forming the doped epitaxial layer 15, the subsequent steps further include: forming an interlayer dielectric layer (not shown) on the isolation structure 12 exposed by the dummy gate structure 13; removing the dummy gate structure 13, An opening (not shown) is formed in the interlayer dielectric layer; a metal layer is filled in the opening to form a metal gate structure.

When etching the fins 11 on both sides of the dummy gate structure 13, the isolation structure 12 is exposed to the etching environment for etching the fins 11, so the etching process is easy for the dummy gate structure. 13 and the isolation structure 12 exposed by the fins 11, and the isolation structure 12 below the sidewall 14 (as shown by the dotted circle 50 in FIG. (As shown by the dashed circle 51 in FIG. 2 ). Therefore, when the metal layer is filled in the opening, the metal layer not only fills the opening, but also fills the gap; thus it is easy to cause the metal layer to pass through the gap and the doped epitaxial layer 15. Bridging means that the doped epitaxial layer 15 is likely to be bridged with the formed metal gate structure, thereby resulting in a decrease in the electrical performance and yield of the semiconductor device.

And when the formed doped epitaxial layer 15 is P-type, the amount of etching the fins 11 on both sides of the dummy gate structure 13 is relatively large, and the remaining fins 11 protrude from the isolation after corresponding etching. The height of the structure 12 is relatively low, and the doped epitaxial layer 15 is closer to the isolation structure 12 along the direction normal to the surface of the substrate 10; therefore, when the substrate 10 is used to form a P-type device, the doped epitaxial layer 15 The problem of bridging between the hetero-epitaxial layer 15 and the metal gate structure is even more serious.

In order to solve the technical problem, the present invention provides a method for forming a semiconductor structure, including: providing a base, the base includes a substrate and discrete fins located on the substrate; the substrate exposed at the fins forming an isolation structure on the top; forming a dummy gate structure across the fin; forming sidewalls on the sidewalls of the dummy gate structure; after forming the sidewalls, forming A groove; a doped epitaxial layer is formed in the groove; after the doped epitaxial layer is formed, an interlayer dielectric layer is formed on the isolation structure exposed by the dummy gate structure, and the interlayer dielectric layer exposes the top of the dummy gate structure; removing the dummy gate structure, forming an opening in the interlayer dielectric layer; forming a barrier layer at the bottom of the opening; removing the barrier layer in the opening; removing the barrier layer in the opening After the blocking layer, a metal layer is filled in the opening to form a metal gate structure. During the process of forming grooves in the fins on both sides of the dummy gate structure, since the isolation structure is exposed to the etching process environment for etching the fins, the etching process is easy to damage the dummy gate. The isolation structure exposed by the structure and the fins, and the isolation structure below the sidewall cause etching loss, resulting in the occurrence of gaps under the sidewall caused by the loss of the isolation structure; in the process of forming the barrier layer, the present invention , the barrier layer also fills the gap, and under the protection of the sidewall, after removing the barrier layer in the opening, the barrier layer in the gap is retained; therefore, in the When the opening is filled with a metal layer, the barrier layer in the gap can function to isolate the doped epitaxial layer from the metal layer, and the metal gate structure and the doped epitaxial layer are bridged. The probability is low, that is, through the solution of the present invention, the problem of bridging between the doped epitaxial layer and the metal gate structure can be improved, thereby improving the electrical performance and yield of the semiconductor device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

3 to 33 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIG. 3 , which is a perspective view (only two fins are shown), a base (not labeled) is provided, and the base includes a substrate 100 and discrete fins (not labeled) on the substrate 100 .

The base is used to form the FinFET, the substrate 100 provides a process platform for the subsequent formation of the FinFET, and the fin portion is used to provide a channel for the formed FinFET.

In this embodiment, taking the formed fin field effect transistor as a CMOS device as an example, the substrate 100 includes a PMOS region I for forming a P-type device and an NMOS region II for forming an N-type device. In other embodiments, the substrate may only include a PMOS region for forming a P-type device, or only include an NMOS region for forming an N-type device.

Correspondingly, the fin located on the substrate 100 in the PMOS region I is the first fin 110 , and the fin located on the substrate 100 in the NMOS region II is the second fin 120 .

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-on-insulator substrate. substrate or glass substrate. The material of the substrate 100 can be selected suitable for process requirements or easily integrated.

The material of the fin is the same as that of the substrate 100 . In this embodiment, the material of the fin is silicon, that is, the material of the first fin 110 and the second fin 120 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

Specifically, the steps of forming the substrate 100 and the fins include: providing an initial substrate; forming a patterned fin mask layer 200 on the surface of the initial substrate; using the fin mask layer 200 as a mask The initial substrate is etched, the etched initial substrate is used as the substrate 100 , and the protrusions on the surface of the substrate 100 are used as fins.

In this embodiment, after the substrate 100 and the fins are formed, the fin mask layer 200 on the top of the fins remains. The material of the fin mask layer 200 is silicon nitride. When the subsequent planarization process is performed, the top surface of the fin mask layer 200 is used to define the stop position of the planarization process, and to protect the Describe the function of the top of the fin.

Referring to FIG. 4 , an isolation structure 101 is formed on the substrate 100 where the fin (not marked) is exposed, the isolation structure 101 covers part of the sidewall of the fin, and the top of the isolation structure 101 is lower than the the top of the fin.

The isolation structure 101 is used as an isolation structure of a semiconductor device, and is used for isolating adjacent devices, and is also used for isolating adjacent fins. In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

Specifically, the step of forming the isolation structure 101 includes: filling an isolation film on the substrate 100 exposed by the first fin 110 and the second fin 120, the top of the isolation film is higher than the fin mask layer 200 (as shown in FIG. 3 ); grinding and removing the isolation film higher than the top of the fin mask layer 200; etching back the remaining isolation film of partial thickness to expose the first fin 110 and the second fin 120 to form the isolation structure 101 ; and remove the fin mask layer 200 .

Referring to Figures 5 to 7, Figure 5 is a perspective view based on Figure 4, Figure 6 is a schematic cross-sectional view of Figure 5 along the secant line B1B2, and Figure 7 is a schematic cross-sectional view of Figure 5 along the secant line A1A2 and D1D2, forming the After the isolation structure 101 is formed, a dummy gate structure (dummy gate) 130 is formed across the fin portion (not shown), and the dummy gate structure 130 covers part of the top surface and the sidewall surface of the fin portion.

In this embodiment, the metal gate structure is formed by forming a high k last metal gate layer after forming a high k gate dielectric layer, and the dummy gate structure 130 occupies a spatial position for subsequent formation of a metal gate structure.

In this embodiment, the dummy gate structure 130 is a stacked structure. The dummy gate structure 130 includes a dummy oxide layer 131 and a dummy gate layer 132 on the dummy oxide layer 131 . Wherein, the material of the dummy gate layer 132 is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride or amorphous carbon, and the material of the dummy oxide layer 131 is Silicon oxide or silicon oxynitride. Specifically in this embodiment, the material of the dummy oxide layer 131 is silicon oxide, and the material of the dummy gate layer 132 is polysilicon.

In other embodiments, the dummy gate structure may also be a single-layer structure, and correspondingly, the dummy gate structure includes a dummy gate layer.

Specifically, the step of forming the dummy gate structure 130 includes: forming a dummy oxide layer 131 on the isolation structure 101, the dummy oxide layer 131 spans the fin, and covers the top surface of the fin and sidewall surface; forming a dummy gate film on the dummy oxide layer 131; forming a gate mask 210 on the surface of the dummy gate film, and the gate mask 210 defines the pattern of the dummy gate layer 132 to be formed; Using the gate mask 210 as a mask, the dummy gate film is patterned to form a dummy gate structure 130 on the isolation structure 101 .

In this embodiment, the dummy gate structure 130 of the PMOS region I spans the first fin 110 and covers part of the top surface and part of the sidewall surface of the first fin 110; the dummy gate structure 130 of the NMOS region II The dummy gate structure 130 spans the second fin 120 and covers part of the top surface and part of the sidewall surface of the second fin 120 .

It should be noted that after the dummy gate structure 130 is formed, the gate mask 210 on the top of the dummy gate structure 130 remains. The material of the gate mask 210 is silicon nitride, and the gate mask 210 is used to protect the top of the dummy gate structure 130 in the subsequent process. In other embodiments, the material of the gate mask may also be silicon oxynitride, silicon carbide or boron nitride.

With reference to Figures 8 to 12, Figure 8 is a schematic cross-sectional structure based on Figure 6, Figure 9 is a schematic cross-sectional structure based on Figure 7, Figure 10 is a schematic cross-sectional structure based on Figure 8, and Figure 11 is a schematic cross-sectional structure based on Figure 9 Schematic diagram, FIG. 12 is a schematic cross-sectional structure diagram at the position of the sidewall along the secant line perpendicular to the extending direction of the fin (as shown by the C1C2 secant line in FIG. 5 ), and a sidewall 300 is formed on the sidewall of the dummy gate structure 130 (as shown in Figure 11).

The spacer 300 is used to define the position of the doped epitaxial layer in subsequent processes, and is also used to protect the dummy gate structure 130 .

The material of the sidewall 300 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 can be a single Layer structure or laminated structure. In this embodiment, the sidewall 300 is a single-layer structure, and the material of the sidewall 300 is silicon nitride.

Specifically, the step of forming the spacer 300 includes: forming a spacer film 125 conformally covering the dummy gate structure 130 in the PMOS region I and NMOS region II (as shown in FIG. 9 ); removing the dummy gate structure 130 The sidewall film 125 on the top and the dummy oxide layer 131 remains the sidewall film 125 on the sidewall of the dummy gate structure 130 , and the remaining sidewall film 125 is used as the spacer 300 .

As shown in FIG. 10 and FIG. 11 , in this embodiment, after the spacer 300 is formed, the dummy oxide layer 131 exposed by the sidewall 300 is removed, and the dummy oxide layer 131 exposed by the sidewall 300 and the dummy gate layer 132 remains. covered dummy oxide layer 131 .

It should be noted that, after forming the spacer 300, the forming method further includes: using the sidewall 300 of the PMOS region 1 as a mask, the first fins on both sides of the dummy gate structure 130 in the PMOS region 1 A P-type source-drain lightly doped region (PLDD) (not shown) is formed in the portion 110, and the dopant ions in the P-type source-drain lightly doped region are P-type ions; the sidewall 300 of the NMOS region II As a mask, an N-type source-drain lightly doped region (PLDD) (not shown) is formed in the second fin portion 120 on both sides of the NMOS region II dummy gate structure 130, and the N-type source-drain lightly doped The doping ions in the region are N-type ions;

Referring to FIGS. 13 to 24, after forming the spacer 300, grooves (not shown) are formed in the fins (not shown) on both sides of the dummy gate structure 130; doping is formed in the grooves. epitaxial layer (not labeled).

The groove provides a space position for subsequent formation of a doped epitaxial layer, and the doped epitaxial layer is used as a source region (source) or a drain region (drain) of a semiconductor device.

In this embodiment, the substrate 100 includes a PMOS region I and an NMOS region II, so the step of forming the groove and the doped epitaxial layer includes: first fins on both sides of the dummy gate structure 130 in the PMOS region I Form a P-region groove 111 in the portion 110 (as shown in FIG. 16 ); form a P-type doped epitaxial layer 112 in the P-region groove 111 (as shown in FIG. 19 ); form a dummy gate in the NMOS region II N-region grooves 121 are formed in the second fins 120 on both sides of the structure 130 (as shown in FIG. 21 ); N-type doped epitaxial layers 122 are formed in the N-region grooves 121 (as shown in FIG. 24 ).

In this embodiment, taking the formation of the P-type doped epitaxial layer 112 first and then forming the N-type doped epitaxial layer 122 as an example, the formation of the P-type doped epitaxial layer 112 and the N-type doped epitaxial layer Step 122 is described in detail.

Referring to FIG. 13 and FIG. 14 together, FIG. 13 is a schematic cross-sectional structure based on FIG. 10, and FIG. 14 is a schematic cross-sectional structure based on FIG. A region mask layer 310, the P region mask layer 310 is also located on the top and sidewalls of the fins of the NMOS region II.

Specifically, the P-region mask layer 310 is located on the top and sidewalls of the first fin 110 and on the top and sidewalls of the second fin 120 .

The process for forming the P-region mask layer 310 may be a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the P-region mask layer 310 is formed by an atomic layer deposition process. Therefore, the P-region mask layer 310 is also located on the top and sidewalls of the dummy gate structure 130 in the PMOS region I, on the top and sidewalls of the dummy gate structure 130 in the NMOS region II, and also on the isolation structure 101 .

The function of the P-region mask layer 310 includes: when etching the first fin 110 with a partial thickness of the PMOS region 1 subsequently, the P-region mask layer located on the sidewall of the first fin 110 310 as a mask, so that there is a certain distance between the subsequently formed P-region groove 111 (as shown in FIG. region is completely etched away; and, the P-region mask layer 310 located on the sidewall of the fin can play a role in protecting the sidewall of the fin, avoiding subsequent steps in the first fin 110 and the second fin The epitaxial growth process is performed on the sidewall of 120; in addition, the P-region mask layer 310 located in the NMOS region II will subsequently serve as a part of the N-region mask layer of the NMOS region II.

The material of the P-region mask layer 310 may be silicon nitride (SiN), silicon carbide nitride (SiCN), silicon boride nitride (SiBN), silicon oxycarbide oxynitride (SiOCN) or silicon oxynitride (SiON). The material of the P-region mask layer 310 is different from that of the fin portion, and the material of the P-region mask layer 310 is also different from that of the isolation structure 101 . In this embodiment, the material of the P-region mask layer 310 is silicon nitride.

Referring to FIGS. 15 to 17 in conjunction, FIG. 15 is a schematic cross-sectional structure based on FIG. 13 , and FIG. 16 is a schematic cross-sectional structure based on a secant line along the extending direction of the first fin in FIG. 14 (as shown by the A1A2 secant line in FIG. 5 ), FIG. 17 is a schematic diagram of a cross-sectional structure at the position of the sidewall along the secant line perpendicular to the extending direction of the fin (as shown by the C1C2 secant line in FIG. 5 ), etching the fins on both sides of the dummy gate structure 130 in the PMOS region I ( The P-region mask layer 310 on the top, which exposes the top surfaces of the fins on both sides of the dummy gate structure 130 in the PMOS region I, and also etches the fins in the PMOS region I with a partial thickness, after etching A p-region groove 111 is formed in the fin.

The P-region groove 111 provides a spatial location for the subsequent formation of a P-type doped epitaxial layer 112 (as shown in FIG. 19 ).

It should be noted that, before etching the P-region mask layer 310 on the top of the fins (not marked) on both sides of the dummy gate structure 130 in the PMOS region I, the forming method further includes: A first pattern layer 220 is formed on it, and the first pattern layer 220 covers the P-region mask layer 310 of the NMOS region II. The first pattern layer 220 serves to protect the P-region mask layer 310 of the NMOS region II, and the first pattern layer 220 can also cover the undesired etched region in the PMOS region I.

In this embodiment, the material of the first pattern layer 220 is a photoresist material. After the P-region groove 111 is formed, the first pattern layer 220 is removed by a wet degumming or ashing process.

Specifically, a dry etching process is used to etch and remove the P-region mask layer 310 on the top of the first fin 110 on both sides of the dummy gate structure 130 in the PMOS region I; During the process of the film layer 310, the P-region mask layer 310 located on the top of the dummy gate structure 130 in the PMOS region 1 and on the isolation structure 101 is also etched; on both sides of the dummy gate structure 130 in the PMOS region 1 After the top of the first fin 110 is exposed, continue to etch part of the thickness of the first fin 110 to form the P-region groove 111 in the first fin 110 .

In this embodiment, the partial thickness of the first fin 110 is etched by using an anisotropic etching process, the anisotropic etching process is a reactive ion etching process, and the parameters of the reactive ion etching process include : The reaction gas includes CF ₄ , SF ₆ and Ar, the flow rate of CF ₄ is 50 sccm to 100 sccm, the flow rate of SF ₆ is 10 sccm to 100 sccm, the flow rate of Ar is 100 sccm to 300 sccm, the source power is 50W to 1000W, and the bias power is 50W to 250W, The process pressure is 50mTorr to 200mTorr, and the process temperature is 20°C to 90°C.

It should be noted that, as shown in FIG. 15, in this embodiment, in order to increase the volume of the P-type doped epitaxial layer 112 subsequently formed in the P-region groove 111, the first fin portion 110 is etched. At the same time, the P-region mask layer 310 located on the sidewall of the first fin 110 is also etched, so that after the P-region groove 111 is formed, the P-region mask layer 310 located on the sidewall of the first fin 110 The remaining P-region mask layer 310 is flush with the top of the first fin portion 110 .

It should also be noted that, as shown in FIG. 17 , in the step of etching the first fin portion 110 of the partial thickness on both sides of the dummy gate structure 130 , since the isolation structure 101 of the PMOS region I is exposed to the etching process environment Therefore, the etching process can also easily etch the isolation structure 101 exposed by the dummy gate structure 130 and the first fin 110 of the PMOS region I, and the isolation structure 101 located at the bottom of the sidewall 300 of the PMOS region I. , thus easily causing a gap (as shown by the dotted circle in FIG. 17 ) to appear under the sidewall 300 of the PMOS region I caused by the loss of the isolation structure 101 .

In addition, in order to provide a good interface basis for the subsequent process of forming the P-type doped epitaxial layer 112, so as to improve the formation quality of the P-type doped epitaxial layer 112, after the P-region groove 111 is formed, the P-type doped epitaxial layer is formed. Before the type doped epitaxial layer 112 , the forming method further includes: performing a cleaning process on the P-region groove 111 .

The cleaning process is not only used to remove impurities in the groove 111 of the P region, but also used to remove the natural oxide layer (not shown) on the surface of the fin.

It should be noted that the isolation structure 101 is exposed to the environment of the cleaning process, so in order to reduce the loss of the isolation structure 101 in the cleaning process, so as not to deteriorate the gap under the sidewall 300 of the PMOS region I Problem, in this embodiment, the cleaning process is a SiCoNi process, and the main etching gas used in the SiCoNi process is gaseous hydrofluoric acid.

18 and FIG. 19, FIG. 18 is a schematic cross-sectional structure based on FIG. 15, and FIG. 19 is a schematic cross-sectional structure based on FIG. epitaxial layer 112 .

In this embodiment, a P-region stress layer is formed in the P-region groove 111 by using a selective epitaxial process, and during the process of forming the P-region stress layer, P-type ions are self-doped in situ to form The P-type doped epitaxial layer 112 . In other embodiments, after the P-region stress layer is formed in the P-region groove, the P-region stress layer may be doped with P-type ions to form the P-type doped epitaxial layer.

Specifically, the material of the P-region stress layer is Si or SiGe, and the material of the P-type doped epitaxial layer 112 is P-type doped Si or SiGe. The P-region stress layer provides compressive stress for the channel region of the P-type device, thereby improving the carrier mobility of the P-type device. In this embodiment, the material of the P-type doped epitaxial layer 112 is SiGe.

Referring to Figure 20 to Figure 22 in conjunction, Figure 20 is a schematic cross-sectional structure based on Figure 18, Figure 21 is a schematic cross-sectional structure along the secant in the extending direction of the second fin (as shown by D1D2 secant in Figure 5), and Figure 22 is Schematic diagram of the cross-sectional structure along the secant line perpendicular to the extending direction of the fin at the position of the sidewall (as shown by the C1C2 secant line in FIG. 5 ), after forming the P-type doped epitaxial layer 112 (as shown in FIG. 18 ), after An N-region mask spacer 320 is formed on the P-region mask layer 310 of the NMOS region II, wherein the P-region mask layer 310 and the N-region mask spacer 320 located in the NMOS region II serve as an N-region mask layer (not marked); etch the N-region mask layer on the top of the fins (not marked) on both sides of the dummy gate structure 130 of the NMOS region II, and also etch the fins of the NMOS region II with a partial thickness, in the The N-region groove 121 is formed in the fin portion (as shown in FIG. 21 ).

The N-region groove 121 provides a spatial location for the subsequent formation of an N-type doped epitaxial layer 122 (as shown in FIG. 24 ).

In this embodiment, the N-region mask layer is located on the top and sidewalls of the second fin 120 and the top and sidewalls of the dummy gate structure 130 in the NMOS region II, and is also located in the NMOS region II On the isolation structure 101 ; the second fin portion 120 is etched with a partial thickness, and the N-region groove 121 is formed in the second fin portion 120 .

In this embodiment, the process for forming the N-region mask sidewall 320 may be a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the N-region mask spacer wall 320 is formed by an atomic layer deposition process. Therefore, the N-region mask sidewall 320 is also located on the P-type doped epitaxial layer 112 and the isolation structure 101 of the PMOS region I, and is also located on the dummy gate structure 130 of the PMOS region I (as shown in FIG. 19 shown) on the side walls and top.

The function of the N-region mask sidewall 320 includes: on the one hand, the N-region mask sidewall 320 and the P-region mask layer 310 constitute an N-region mask layer of a stacked structure, and the subsequent etching of the N-region mask layer When the second fins 120 of the partial thickness on both sides of the dummy gate structure 130 in the NMOS region II, the N-region mask layer of the stacked structure is used as a mask, so the N-region mask spacers 320 can be used to increase the subsequent Forming the distance between the groove 121 in the N region (as shown in FIG. 21 ) and the channel region is beneficial to improve the short channel effect.

Regarding the material and formation process of the N-region mask sidewall 320 , reference may be made to the related description of the P-region mask layer 310 , which will not be repeated here.

Therefore, the material of the N-region mask layer may be silicon nitride, silicon nitride carbide, silicon nitride boride, silicon oxycarbide or silicon oxynitride. In this embodiment, the material of the N-region mask sidewall 320 is silicon nitride. Correspondingly, the material of the N-region mask layer is silicon nitride.

Specifically, the step of forming the N-region groove 121 in the second fin portion 120 includes: etching the N-region mask located on the top of the second fin portion 120 on both sides of the NMOS region II dummy gate structure 130 layer, wherein, during the process of etching the N-region mask layer on the top of the second fin portion 120, the N-region mask layer on the top of the NMOS region II dummy gate structure 130 is also etched, and Etching the N-region mask layer on the NMOS region II isolation structure 101; after the tops of the second fins 120 on both sides of the NMOS region II dummy gate structure 12 are exposed, continue to etch the part of the thickness of the The second fin portion 120 , the N-region groove 121 is formed in the second fin portion 120 .

Regarding the etching process for forming the groove 121 in the N region, reference may be made to the related description of forming the groove 111 in the P region (as shown in FIG. 16 ), and details are not repeated here.

In this embodiment, in order to increase the volume of the N-type doped epitaxial layer 122 subsequently formed in the N-region groove 121, while the second fin 120 is etched, the second fin 120 is also etched. The N-region masking layer on the sidewall of the fin 120, so that after the N-region groove 121 is formed, the remaining N-region masking layer on the sidewall of the second fin 120 and the second fin The top of portion 120 is flush.

It should be noted that, according to actual process requirements, the etching amount of the second fin portion 120 is smaller than the etching amount of the first fin portion 110 when forming the P-region groove 111 .

It should also be noted that, before etching the N-region mask layer, the forming method further includes: forming a second pattern layer 230 (as shown in FIG. 20 ) in the PMOS region I, and the second pattern The layer 230 covers the P-type doped epitaxial layer 112, and the second pattern layer 230 also covers the dummy gate structure 130 of the PMOS region I (as shown in FIG. 19 ).

Specifically, the second pattern layer 230 is formed on the N-region mask sidewall 320 of the PMOS region I, the second pattern layer 230 can protect the PMOS region I, and the second pattern layer 230 can protect the PMOS region I. The graphic layer 230 can also cover the undesired etched area in the NMOS area II.

In this embodiment, the material of the second pattern layer 230 is a photoresist material. After the N-region groove 121 is formed, the second graphic layer 230 is removed by a wet stripping or ashing process.

With reference to FIG. 22 , it should be noted that, for the NMOS region II, sidewalls 300 are formed on the sidewalls of the dummy gate structure 130 in the NMOS region II, and a P-region mask is formed on the sidewalls of the sidewalls 300 Layer 310, the sidewall of the P-region mask layer 310 is formed with N-region mask sidewalls 320, so in the extending direction along the second fin 120, for the dummy gate structure 130 on the same side For the N-region mask sidewall 320, the P-region mask layer 310, and the sidewall 300, the sidewall of the N-region mask sidewall 320 facing away from the side of the dummy gate structure 130 faces the direction of the sidewall 300. The distance between the sidewalls on one side of the dummy gate structure 130 is larger, and the distance is the sum of the thicknesses of the N-region mask sidewall 320, the P-region mask layer 310 and the thickness of the sidewall 300; so compared to the PMOS region I, when etching the second fins 120 with a partial thickness on both sides of the dummy gate structure 130 in the NMOS region II, the etching process causes etching loss to the isolation structure 101 below the spacer wall 300 in the NMOS region II The possibility is low, and the possibility of gaps appearing under the sidewall 300 of the NMOS region II is correspondingly low.

It should also be noted that, after forming the N-region groove 121, the forming method further includes: performing a cleaning process on the N-region groove 121 using a SiCoNi process, and the main etching gas used in the SiCoNi process is gaseous hydrofluoric acid.

The cleaning process is used not only to remove impurities in the N-region groove 121, but also to remove a natural oxide layer (not shown) on the surface of the fin.

Regarding the cleaning process of the groove 121 in the N-region, reference may be made to the relevant description of the cleaning process of the groove 111 in the P-region (as shown in FIG. 16 ), which will not be repeated here.

Referring to FIG. 23 and FIG. 24 together, FIG. 23 is a schematic cross-sectional structure based on FIG. 20, and FIG. 24 is a schematic cross-sectional structure based on FIG. heteroepitaxial layer 122.

In this embodiment, a selective epitaxial process is used to form an N-region stress layer in the N-region groove 121, and during the process of forming the N-region stress layer, N-type ions are self-doped in situ to form The N-type doped epitaxial layer 122 . In other embodiments, after the N-region stress layer is formed in the N-region groove, N-type ion doping can be performed on the N-region stress layer to form the N-type doped epitaxial layer.

Specifically, the material of the N-region stress layer is Si or SiC, and the material of the N-type doped epitaxial layer 122 is N-type doped Si or SiC. The N-region stress layer provides tensile stress for the channel region of the N-type device, thereby improving the carrier mobility of the N-type device. In this embodiment, the material of the N-type doped epitaxial layer 122 is SiGe.

Referring to Fig. 25 and Fig. 26 together, Fig. 25 is a schematic cross-sectional structure diagram based on Fig. 23, and Fig. 26 is a secant line along the extending direction of the first fin (as shown by the A1A2 secant line in Fig. 5 ) and extending along the second fin respectively. Schematic diagram of the cross-sectional structure of the direction secant (as shown by the D1D2 secant in FIG. 5 ), after forming the doped epitaxial layer (not marked), an interlayer dielectric layer is formed on the isolation structure 101 exposed by the dummy gate structure 130 102 (as shown in FIG. 26 ), the interlayer dielectric layer 102 exposes the top of the dummy gate structure 130 .

Specifically, after forming the P-type doped epitaxial layer 112 (as shown in FIG. 25 ) and the N-type doped epitaxial layer 122 (as shown in FIG. 25 ), the interlayer dielectric layer 102 is formed.

The interlayer dielectric layer 102 is used to realize electrical isolation between semiconductor structures, and is also used to define the size and position of the subsequently formed metal gate structure. In this embodiment, the material of the interlayer dielectric layer 102 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

Specifically, the step of forming the interlayer dielectric layer 102 includes: forming a dielectric material layer on the isolation structure 101 exposed by the dummy gate structure 130, the dielectric material layer covering the dummy gate structure 130; The dielectric material layer higher than the top of the dummy gate structure 130 is removed in a similar manner to expose the top of the dummy gate structure 130 , and the remaining dielectric material layer is used as the interlayer dielectric layer 102 .

It should be noted that the gate mask 210 is formed on the top of the dummy gate structure 130 , therefore, in the step of forming the interlayer dielectric layer 102 , the dielectric material layer higher than the top of the gate mask 210 is removed. In this embodiment, after the interlayer dielectric layer 102 is formed, the top of the interlayer dielectric layer 102 is flush with the top of the gate mask 210 .

Referring to FIG. 27 , which is a schematic cross-sectional structure diagram based on FIG. 26 , the dummy gate structure 130 (as shown in FIG. 26 ) is removed, and an opening 152 is formed in the interlayer dielectric layer 102 .

The opening provides a space for the subsequent formation of the metal gate structure.

In this embodiment, in the step of removing the dummy gate structure 130, the dummy gate layer 132 and the dummy oxide layer 131 in the PMOS region I are removed to form an interlayer dielectric layer 102 that penetrates the PMOS region I and exposes the first an opening 152 of the fin 110, and remove the dummy gate layer 132 and the dummy oxide layer 131 of the NMOS region II to form an opening 152 that penetrates the interlayer dielectric layer 102 of the NMOS region II and exposes the second fin 120 .

In this embodiment, in order to reduce the loss of the isolation structure 101 , the dummy oxide layer 131 is removed by a dry etching process.

It should be noted that, from the foregoing analysis, it can be known that gaps (shown as dashed circles in FIG. In the process, the remaining material of the isolation structure 101 in the gap can also be removed, so as to enlarge the gap, so as to facilitate subsequent filling of the barrier layer into the gap.

Referring to Figure 28 and Figure 29 together, Figure 28 is a schematic cross-sectional structure based on Figure 27, and Figure 29 is a cross-sectional structure along a secant line perpendicular to the extending direction of the fin at the position of the side wall (as shown by the C1C2 secant line in Figure 5) In a schematic view, a barrier layer 350 is formed at the bottom of the opening 152 .

The barrier layer 350 is used to fill the gap below the side wall 300 of the PMOS region I at the position of the isolation structure 101, and when the metal layer is subsequently filled into the opening 152, the barrier layer 350 in the gap can function as an isolation The effect of the P-type doped epitaxial layer 112 on the metal layer, correspondingly, the metal gate structure formed subsequently has a low probability of bridging with the P-type doped epitaxial layer 112 through the gap .

In order to improve process compatibility, the material of the barrier layer 350 may be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbonitride. In this embodiment, the gap is formed by the loss of the isolation structure 101 , so the material of the barrier layer 350 is the same as that of the isolation structure 101 , that is, the material of the barrier layer 350 is silicon oxide.

In this embodiment, the process of forming the barrier layer 350 is an atomic layer deposition process; correspondingly, the barrier layer 350 is also located on the sidewall of the opening 152 and the top of the interlayer dielectric layer 102 . The atomic layer deposition process has good step coverage and can better fill the corners of the opening 152 . As shown in FIG. 29, and using the characteristics of the atomic layer deposition process, the barrier layer 350 can also better fill the gap under the side wall 300 of the PMOS region I at the position of the isolation structure 101 (as shown in FIG. 22 shown by the dotted circle).

It should be noted that the thickness of the barrier layer 350 should neither be too small nor too large. If the thickness of the barrier layer 350 is too small, the effect of filling the gap under the sidewall 300 of the PMOS region I is not obvious. Correspondingly, the barrier layer 350 isolates the P-type doped epitaxial layer 112 from the metal layer. The effect is not obvious; if the thickness of the barrier layer 350 is too large, it will waste materials and increase the process cost. Therefore, in this embodiment, the thickness of the barrier layer 350 is to

Referring to FIG. 30 and FIG. 31 together, FIG. 30 is a schematic cross-sectional structure based on FIG. 28 , and FIG. 31 is a schematic cross-sectional structure based on FIG. 29 , removing the barrier layer 350 in the opening 152 (as shown in FIG. 30 ).

The opening 152 is used to subsequently form a metal gate structure, so the barrier layer 350 is used to fill the gap under the sidewall 300 of the PMOS region I (as shown by the dotted circle in FIG. 22 ), and the opening 152 is removed. The barrier layer 350 in.

In this embodiment, the process of removing the barrier layer 350 in the opening 152 is a dry etching process. Specifically, the dry etching process is a SiCoNi process, and the main etching gas used in the SiCoNi process is gaseous hydrofluoric acid. Wherein, specific etching process parameters may be determined according to the thickness of the barrier layer 350 .

Compared with the wet etching process, the dry etching process has better anisotropic etching characteristics, so the loss of the barrier layer 350 in the gap by the etching process can be reduced to avoid damage to the barrier layer 350. The filling effect of the layer 350 in the gap has a negative effect. Therefore, under the protection of the side wall 300 , during the step of removing the barrier layer 350 in the opening 152 , the barrier layer 350 in the gap is retained.

Referring to FIG. 32 and FIG. 33 together, FIG. 32 is a schematic cross-sectional structure based on FIG. 30 , and FIG. 33 is a schematic cross-sectional structure based on FIG. 31 , removing the barrier layer 350 in the opening 152 (as shown in FIG. 30 ). As shown in FIG. 28 ), a metal layer 520 is filled in the opening 152 to form a metal gate structure 500 .

The metal gate structure 500 is used to control the conduction and disconnection of the channel of the formed semiconductor device.

It should be noted that, after removing the barrier layer 350 in the opening 152 and before filling the opening 152 with the metal layer 520 , the forming method further includes: forming A gate dielectric layer (not shown), the gate dielectric layer is also located on the top of the interlayer dielectric layer 102 . Specifically, the gate dielectric layer includes an interface layer (IL, Interfacial Layer) (not shown in the figure) and a high-k gate dielectric layer 510 located on the surface of the interface layer.

The interface layer is formed at the bottom of the opening 152 of the PMOS region I and the NMOS region II, and the interface layer provides a good interface basis for forming the high-k gate dielectric layer 510, thereby improving the high-k gate dielectric layer 510 quality, reduce the interface state density between the high-k gate dielectric layer 510 and the first fin 110 and the second fin 120, and avoid the high-k gate dielectric layer 510 and the first fin Adverse effects caused by direct contact between the portion 110 and the second fin portion 120 . The material of the interface layer is silicon oxide or silicon oxynitride.

The material of the high-k gate dielectric layer 510 is a gate dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer 510 is HfO ₂ . In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ .

Therefore, the step of forming the metal gate junction 500 includes: forming a metal layer 520 on the gate dielectric layer of the PMOS region I and the NMOS region II; removing the metal layer 520 higher than the top of the interlayer dielectric layer 102, and The high-k gate dielectric layer 510 higher than the top of the interlayer dielectric layer 102 is also removed, and the remaining gate dielectric layer and metal layer 520 in the opening 152 of the PMOS region 1 are used to form the metal gate junction of the PMOS region 1 500, the remaining gate dielectric layer and metal layer 520 in the opening 152 of the NMOS region II are used to form the metal gate junction 500 of the NMOS region II, and the top of the metal gate junction 500 is connected to the interlayer dielectric The top of layer 102 is flush.

In this embodiment, the process of forming a p-region groove 111 (as shown in FIG. 16 ) in the first fins 110 (as shown in FIG. 16 ) on both sides of the dummy gate structure 130 (as shown in FIG. 16 ) During the process, since the isolation structure 101 (as shown in FIG. 17 ) is exposed to the etching process environment for etching the first fin portion 110, the etching process is easy for the dummy gate structure 130 and the first fin portion 110. The isolation structure 101 exposed by a fin 110 and the isolation structure 101 below the sidewall 300 (as shown in FIG. 17 ) cause etching loss, resulting in the loss of the isolation structure 101 under the sidewall 300. gap (as shown by the dotted circle in FIG. 17 ); and after removing the dummy gate structure 130 to form an opening 152 in the interlayer dielectric layer 102 (as shown in FIG. During the process of forming the barrier layer 350 (as shown in FIG. 28 ), the barrier layer 350 also fills the gap, and under the protection of the side wall 300, the barrier layer in the opening 152 is removed After 350, the barrier layer 350 in the gap is retained; therefore, when the metal layer 520 is filled in the opening 152 (as shown in FIG. 32 ), the barrier layer 350 in the gap can isolate the P-type Due to the interaction between the doped epitaxial layer 112 (as shown in FIG. 32 ) and the metal layer 520, the probability of bridging between the metal gate structure 500 and the P-type doped epitaxial layer 112 is low, that is, through The solution of the present invention can solve the bridging problem between the P-type doped epitaxial layer 112 and the metal gate structure 500, thereby improving the electrical performance and yield of the semiconductor device.

Referring to Fig. 25, Fig. 28 and Fig. 29, Fig. 25 is a schematic diagram of the cross-sectional structure perpendicular to the extending direction of the fin (as shown by the secant line B1B2 in Fig. Line (as shown by the A1A2 secant in Figure 5) and the secant along the extending direction of the second fin (as shown by the D1D2 secant in Figure 5), and Figure 29 is a schematic diagram of the cross-sectional structure at the position of the side wall along the vertical direction of the fin The schematic diagram of the cross-sectional structure of the secant line in the extension direction (as shown by the C1C2 secant line in Figure 5). Correspondingly, the present invention also provides a semiconductor structure, including:

A base, the base includes a substrate 100 and a discrete fin (not shown) on the substrate 100; an isolation structure 101, located on the substrate 100 where the fin is exposed, and the isolation structure 101 covers the Part of the sidewall of the fin, and the top of the isolation structure 101 is lower than the top of the fin; the interlayer dielectric layer 102 (as shown in FIG. 25 ) located on the isolation structure 101, the interlayer dielectric layer 102 There is an opening 152 (as shown in FIG. 28 ) exposing the fin and the isolation structure 101; a doped epitaxial layer (not shown) is located in the fin on both sides of the opening 152; sidewalls 300 are located in the opening 152 on the sidewall; the barrier layer 350 is located at the bottom of the opening 152 .

The base is used to form the FinFET, the substrate 100 provides a process platform for forming the FinFET, and the fin part is used to provide a channel of the FinFET.

In this embodiment, taking the formed fin field effect transistor as a CMOS device as an example, the substrate 100 includes a PMOS region I for forming a P-type device and an NMOS region II for forming an N-type device. In other embodiments, the substrate may only include a PMOS region for forming a P-type device, or only include an NMOS region for forming an N-type device.

Correspondingly, the fin located on the substrate 100 in the PMOS region I is the first fin 110 , and the fin located on the substrate 100 in the NMOS region II is the second fin 120 .

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-on-insulator substrate. substrate or glass substrate. The material of the substrate 100 can be selected suitable for process requirements or easily integrated.

The material of the fin is the same as that of the substrate 100 . In this embodiment, the material of the fin is silicon, that is, the material of the first fin 110 and the second fin 120 is silicon. In other embodiments, the material of the fin portion may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

The isolation structure 101 is used as an isolation structure of a semiconductor device, and is used for isolating adjacent devices, and is also used for isolating adjacent fins 110 . In this embodiment, the material of the isolation structure 101 is silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

The interlayer dielectric layer 102 is used to realize electrical isolation between semiconductor structures, and is also used to define the size and position of the metal gate structure during the semiconductor manufacturing process. In this embodiment, the material of the interlayer dielectric layer 102 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

The interlayer dielectric layer 102 has an opening 152; wherein, the opening 152 located in the PMOS region I penetrates the interlayer dielectric layer 102 of the PMOS region I and exposes the first fin 110, and is located in the NMOS region The opening 152 of II penetrates the interlayer dielectric layer 102 of the NMOS region II and exposes the second fin 120; the opening 152 of the PMOS region I provides a space for forming the metal gate structure of the PMOS region I. The opening 152 of the NMOS region II provides a spatial location for the metal gate structure forming the NMOS region II.

The doped epitaxial layer serves as a source or drain of a semiconductor device.

In this embodiment, the substrate 100 includes a PMOS region I and an NMOS region II, so the doped epitaxial layer in the first fin portion 110 located on both sides of the opening 152 of the PMOS region I is a P-type doped epitaxial layer 112 , the doped epitaxial layer in the second fin portion 120 located on both sides of the opening 152 of the NMOS region II is an N-type doped epitaxial layer 122 . Correspondingly, the P-type doped epitaxial layer 112 serves as a source region or a drain region of a P-type device, and the N-type doped epitaxial layer 122 serves as a source region or a drain region of an N-type device.

The formation process of the P-type doped epitaxial layer 112 and the N-type doped epitaxial layer 122 is a selective epitaxial process, so the material of the P-type doped epitaxial layer 112 is P-type doped Si or SiGe, the The material of the N-type doped epitaxial layer 122 is N-type doped Si or SiC. In this embodiment, the material of the P-type doped epitaxial layer 112 is SiGe, and the material of the N-type doped epitaxial layer 122 is SiP.

Therefore, the semiconductor structure further includes: a P-region mask layer 310 located on the sidewall of the first fin 110 of the PMOS region I, and an N-region mask layer 310 located on the sidewall of the second fin 120 of the NMOS region II. film layer (not labeled).

When forming the P-type doped epitaxial layer 112, the P-region mask layer 310 is used as an etching mask for etching the first fin portion 110, and the P-region mask layer 310 can also avoid An epitaxial growth process is performed on the sidewalls of the first fin 110 and the second fin 120 .

The material of the P-region mask layer 310 may be silicon nitride (SiN), silicon carbide nitride (SiCN), silicon boride nitride (SiBN), silicon oxycarbide oxynitride (SiOCN) or silicon oxynitride (SiON). The material of the P-region mask layer 310 is different from that of the fin portion, and the material of the P-region mask layer 310 is also different from that of the isolation structure 101 . In this embodiment, the material of the P-region mask layer 310 is silicon nitride.

In this embodiment, during the process of forming the P-region mask layer 310, the P-region mask layer 310 is also formed on the sidewall of the second fin 120, so the N-region mask layer includes The P-region mask layer 310 located on the sidewall of the second fin 120 and the N-region mask sidewall 320 located on the sidewall of the P-region mask layer 310, and the N-region mask sidewall 320 It is also located on the P-type doped epitaxial layer 112 .

That is to say, the N-region mask layer is a laminated structure; when forming the N-type doped epitaxial layer 122, the N-region mask layer is used as an etching mask for etching the second fin portion 120 film, and is beneficial to increase the distance between the N-type doped epitaxial layer 122 and the channel region, thereby improving the short channel effect.

Therefore, the material of the N-region mask layer is silicon nitride, silicon nitride carbide, silicon nitride boride, silicon oxycarbide or silicon oxynitride. In this embodiment, the material of the N-region mask sidewall 320 is silicon nitride, and correspondingly, the material of the N-region mask layer is silicon nitride.

The spacer 300 is used to define the positions of the P-type doped epitaxial layer 112 and the N-type doped epitaxial layer 122 .

The material of the sidewall 300 can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 can be a single Layer structure or laminated structure. In this embodiment, the sidewall 300 is a single-layer structure, and the material of the sidewall 300 is silicon nitride.

It should be noted that, in the semiconductor manufacturing process, the dummy gate structure across the fin is generally formed first; forming a groove in the fin; forming the doped epitaxial layer in the groove; after forming the doped epitaxial layer, removing the dummy gate structure and filling a metal layer at the position of the dummy gate structure to form the doped epitaxial layer The metal gate structure described above.

When etching the fin, the isolation structure 101 is exposed to the etching process environment, so the etching process is easy to remove the dummy gate structure, the isolation structure exposed by the fin, and the bottom of the spacer 300 The isolation structure 101, the loss of the isolation structure 101 under the sidewall 300 of the PMOS region I is particularly severe, which easily leads to the occurrence of gaps caused by the loss of the isolation structure 101 under the sidewall 300 of the PMOS region I (as shown in FIG. 22 indicated by the dotted circle).

For the NMOS region II, the sidewall of the opening 152 has a sidewall 300, the sidewall of the sidewall 300 has a P-region mask layer 310, and the sidewall of the P-region mask layer 310 has a The N-region mask sidewall 320, therefore, in the extending direction along the second fin 120, for the N-region mask sidewall 320, the P-region mask layer 310 and the sidewall 300 on the same side of the opening 152 , the distance between the side wall of the N-region mask sidewall 320 facing away from the opening 152 and the sidewall of the sidewall 300 exposed by the opening 152 is relatively large, and the distance is the N-region mask sidewall 320, the sum of the thicknesses of the P-region mask layer 310 and the sidewall 300; therefore, compared to the PMOS region I, when etching the second fin 120, the etching process has a greater impact on the NMOS region II sidewall 300 The possibility of etching loss caused by the isolation structure 101 below is relatively low, and the possibility of gaps appearing under the sidewall 300 of the NMOS region II is correspondingly low.

Therefore, during the formation process of the barrier layer 350, the barrier layer 350 can fill the gap under the sidewall 300 of the PMOS region I, and under the protection of the sidewall 300, when the opening 152 is removed When the barrier layer 350 is formed, the barrier layer 350 in the gap is retained; and the semiconductor manufacturing process also includes filling the opening 152 with a metal layer to form a metal gate structure, so filling the opening 152 When forming a metal layer, the barrier layer 350 in the gap can play a role in isolating the P-type doped epitaxial layer 112 from the metal layer, and the metal gate structure and the P-type doped epitaxial layer 112 The probability of bridging is low, that is, the problem of bridging between the P-type doped epitaxial layer 112 and the metal gate structure can be improved through the barrier layer 350 , thereby improving the electrical performance and yield of the semiconductor device.

In order to improve process compatibility, the material of the barrier layer 350 may be an insulating dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbonitride. In this embodiment, the gap is formed by the loss of the isolation structure 101 , so the material of the barrier layer 350 is the same as that of the isolation structure 101 , that is, the material of the barrier layer 350 is silicon oxide.

In this embodiment, in order to enable the barrier layer 350 to fill the gap under the sidewall 300 of the PMOS region I, the process of forming the barrier layer 350 is an atomic layer deposition process; therefore, the barrier layer 350 is also located in the The sidewall of the opening 152 and the top of the interlayer dielectric layer 102 .

It should be noted that the thickness of the barrier layer 350 should neither be too small nor too large. If the thickness of the barrier layer 350 is too small, the effect of filling the gap under the sidewall 300 of the PMOS region I is not obvious. Correspondingly, the barrier layer 350 isolates the P-type doped epitaxial layer 112 from the metal layer. The effect is not obvious; if the thickness of the barrier layer 350 is too large, it will waste materials and increase the process cost. Therefore, in this embodiment, the thickness of the barrier layer 350 is to

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:

providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate;

forming an isolation structure on the substrate with the exposed fin portion, wherein the isolation structure covers part of the side wall of the fin portion, and the top of the isolation structure is lower than the top of the fin portion;

after the isolation structure is formed, forming a pseudo-gate structure crossing the fin part, wherein the pseudo-gate structure covers part of the top surface and the side wall surface of the fin part;

forming a side wall on the side wall of the pseudo gate structure;

after the side walls are formed, grooves are formed in the fin parts on two sides of the pseudo gate structure;

forming a doped epitaxial layer in the groove;

after the doped epitaxial layer is formed, forming an interlayer dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate structure;

removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer;

forming a barrier layer at the bottom of the opening;

removing the barrier layer in the opening;

and after removing the barrier layer in the opening, filling a metal layer in the opening to form a metal gate structure.

2. The method of claim 1, wherein the barrier layer is formed of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

3. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness ofTo

4. The method of forming a semiconductor structure of claim 1, wherein the process of forming the barrier layer is an atomic layer deposition process.

5. The method of claim 1, wherein the process of removing the barrier layer in the opening is a dry etching process.

6. The method of claim 1, wherein the step of forming the recess in the fin on both sides of the dummy gate structure comprises: and etching the fin parts with partial thickness at two sides of the pseudo-gate structure by adopting a dry etching process, and forming grooves in the fin parts.

7. The method for forming the semiconductor structure according to claim 6, wherein in the step of etching the fin portions at the two sides of the dummy gate structure, the isolation structure exposed by the dummy gate structure and the fin portions and the isolation structure at the bottom of the sidewall are also etched, and a gap is formed at the bottom of the sidewall;

in the step of forming a barrier layer at the bottom of the opening, the barrier layer also fills the gap;

and in the step of removing the barrier layer in the opening, the barrier layer in the gap is reserved.

8. The method of forming a semiconductor structure of claim 1, wherein after forming a recess in the fin on both sides of the dummy gate structure, before forming a doped epitaxial layer in the recess, the method further comprises: and carrying out a cleaning process on the groove.

9. The method of claim 8, wherein the cleaning process is a SiCoNi process, and wherein a main etching gas used in the SiCoNi process is gaseous hydrofluoric acid.

10. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate comprises a PMOS region for forming a P-type device and an NMOS region for forming an N-type device;

the step of forming the recess and doping the epitaxial layer comprises: forming P-region grooves in the fin parts on two sides of the PMOS region pseudo-gate structure; forming a P-type doped epitaxial layer in the P region groove; forming N-region grooves in the fin parts on two sides of the NMOS region pseudo-gate structure; and forming an N-type doped epitaxial layer in the N-region groove.

11. The method of forming a semiconductor structure of claim 10, wherein forming the P-doped epitaxial layer and the N-doped epitaxial layer comprises: forming a P-region mask layer on the top and the side wall of the fin part of the PMOS region, wherein the P-region mask layer is also positioned on the top and the side wall of the fin part of the NMOS region;

etching the P-region mask layers on the tops of the fin parts on the two sides of the PMOS region pseudo-gate structure, exposing the top surfaces of the fin parts on the two sides of the PMOS region pseudo-gate structure, etching the fin parts of the PMOS region with partial thickness, and forming P-region grooves in the etched fin parts;

forming a P-type doped epitaxial layer in the P region groove;

after the P-type doped epitaxial layer is formed, forming N-region mask side walls on the P-region mask layer of the NMOS region, wherein the P-region mask layer and the N-region mask side walls located in the NMOS region serve as N-region mask layers;

etching N-region mask layers on the tops of fin parts on two sides of the NMOS region pseudo-gate structure, etching the fin parts of the NMOS region with partial thickness, and forming N-region grooves in the fin parts;

and forming an N-type doped epitaxial layer in the N-region groove.

12. The method of claim 11, wherein the P-region mask layer is made of silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride; the N-region mask layer is made of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide or silicon oxynitride.

13. The method of claim 1, wherein the substrate is used to form a P-type device, and the step of forming a doped epitaxial layer in the recess is performed by using P-type doped Si or SiGe as the material of the doped epitaxial layer;

or,

the substrate is used for forming an N-type device, and in the step of forming the doped epitaxial layer in the groove, the doped epitaxial layer is made of N-type doped Si or SiC.

14. The method of claim 1, wherein after removing the barrier layer in the opening and before filling the opening with a metal layer, the method further comprises: and forming gate dielectric layers on the bottom and the side wall of the opening, wherein the gate dielectric layers comprise an interface layer and a high-k gate dielectric layer positioned on the surface of the interface layer.

15. A semiconductor structure, comprising:

the base comprises a substrate and a discrete fin part positioned on the substrate;

the isolation structure is positioned on the substrate with the exposed fin part, covers partial side walls of the fin part, and has the top lower than the top of the fin part;

the interlayer dielectric layer is positioned on the isolation structure and is internally provided with an opening for exposing the fin part and the isolation structure;

the doped epitaxial layer is positioned in the fin parts at two sides of the opening;

the side wall is positioned on the side wall of the opening;

and the barrier layer is positioned at the bottom of the opening.

16. The semiconductor structure of claim 15, wherein the material of the barrier layer is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

17. The semiconductor structure of claim 15, wherein the barrier layer has a thickness ofTo

18. The semiconductor structure of claim 15, wherein the substrate is used to form a P-type device, and the material of the doped epitaxial layer is P-type doped Si or SiGe;

or,

the substrate is used for forming an N-type device, and the material of the doped epitaxial layer is N-type doped Si or SiC.

19. The semiconductor structure of claim 15, wherein the substrate comprises a PMOS region for forming a P-type device and an NMOS region for forming an N-type device;

the doped epitaxial layers in the fin parts on the two sides of the opening of the PMOS region are P-type doped epitaxial layers, and the doped epitaxial layers in the fin parts on the two sides of the opening of the NMOS region are N-type doped epitaxial layers;

the semiconductor structure further includes: the N-region mask layer is located on the side wall of the NMOS region fin portion.

20. The semiconductor structure of claim 19, wherein the P-region mask layer is made of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide, or silicon oxynitride; the N-region mask layer is made of silicon nitride, silicon carbide nitride, silicon boride nitride, silicon oxycarbide or silicon oxynitride.