CN105244276B - A kind of FinFET and its manufacturing method, electronic device - Google Patents
A kind of FinFET and its manufacturing method, electronic device Download PDFInfo
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- CN105244276B CN105244276B CN201410260429.4A CN201410260429A CN105244276B CN 105244276 B CN105244276 B CN 105244276B CN 201410260429 A CN201410260429 A CN 201410260429A CN 105244276 B CN105244276 B CN 105244276B
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- 238000001312 dry etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000004381 surface treatment Methods 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 15
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of FinFET of present invention offer and its manufacturing method, electronic device, the method includes：Semiconductor substrate is provided, is formed with fin on a semiconductor substrate；The dummy gate structure of the sacrificial gate dielectric layer and sacrificial gate material layer including stacking gradually is formed in the both sides of fin and top；Interlevel dielectric deposition, to cover dummy gate structure, fin and semiconductor substrate；Interlayer dielectric layer is ground, until exposing the top of dummy gate structure；Remove the sacrificial gate material layer in dummy gate structure；Sacrificial gate dielectric layer in Joint Implementation dry etching, surface treatment and wet etching removal dummy gate structure.According to the present invention it is possible to effectively enhance the control accuracy of the removal to sacrificial gate dielectric layer, the loss on fin surface is avoided.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of FinFET and its manufacturing method, electronic device.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
The size of device is realized with improving its speed.Currently, due in pursuing high device density, high-performance and low cost half
Conductor industry has advanced to that nanotechnology process node, the preparation of semiconductor devices are limited by various physics limits.
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FinFET).Relative to existing planar transistor, FinFET is to be used for 22nm and following work
The advanced semiconductor device of skill node, can effectively control device it is scaled caused by be difficult to the short channel overcome effect
It answers, the density of transistor array formed on a substrate can also be effectively improved, meanwhile, the grid in FinFET is set around fin
It sets, therefore electrostatic effect can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent.
The following processing step of prior art generally use forms the fin of FinFET：First, it is formed on silicon substrate
Buried oxide layer is to make silicon-on-insulator (SOI) structure；Then, silicon layer is formed on silicon structure on insulator, is constituted
Material can be monocrystalline silicon or polysilicon；Then, graphical silicon layer, and etch it is described through patterned silicon layer, to form fin
Piece.Next, forming the grid of the gate dielectric and gate material layers including being laminated from bottom to top in the both sides of fin and top
Pole structure, and form germanium silicon stressor layers at the both ends of fin.
If the high k dielectric layer-metal gate process of subsequent implementation, needs first to remove gate structure, the prior art uses
One time etch process implements the removal.For the FinFET with 22nm and following process node, in gate structure
The very thin thickness of gate dielectric implements an etch process (including the dry etching and wet etching implemented successively) for grid
The control accuracy of the removal of pole dielectric layer is very poor, causes the removal of the gate dielectric positioned at the both sides of different fins and top equal
One property is poor, in turn results in the loss on fin surface.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of FinFET, including：Semiconductor lining is provided
Bottom is formed with fin on the semiconductor substrate；It includes the sacrifice stacked gradually to be formed in the both sides of the fin and top
The dummy gate structure of gate dielectric and sacrificial gate material layer；Interlevel dielectric deposition, to cover the dummy gate structure, institute
State fin and the semiconductor substrate；Interlayer dielectric layer is ground, until exposing the top of the dummy gate structure；Remove the puppet
Sacrificial gate material layer in gate structure；Joint Implementation dry etching, surface treatment and wet etching remove the dummy grid
Sacrificial gate dielectric layer in structure.
In one example, the Joint Implementation order of the dry etching, surface treatment and wet etching is：The dry method
Etching → the surface treatment → dry etching → the surface treatment → wet etching, the dry etching are
SiCoNi is etched, and the cleaning solution of the surface treatment is the deionized water dissolved with ozone, and the corrosive liquid of the wet etching is
Hydrofluoric acid.
In one example, contain a small amount of fluorine in the etching gas of the SiCoNi etchings.
In one example, the sacrificial gate material layer is removed using another dry etching.
In one example, it is formed after the dummy gate structure before depositing the interlayer dielectric layer, further includes in institute
State the step of germanium silicon stressor layers are formed on the fin of dummy gate structure both sides exposing.
In one example, the germanium silicon stressor layers are formed using selective epitaxial growth process.
In one example, further include following step after removing the sacrificial gate dielectric layer：High k dielectric layer is formed,
To cover the fin；Metal gates are formed, the high k dielectric layer and the interlayer dielectric layer are covered；Chemical machinery is executed to grind
Mill is until expose the top of the interlayer dielectric layer.
In one example, the metal gates include the workfunction setting metal layer stacked gradually, barrier layer and metal
Gate material layers.
In one embodiment, the present invention also provides a kind of FinFETs manufactured using the above method.
In one embodiment, the present invention also provides a kind of electronic device, the electronic device includes the FinFET devices
Part.
According to the present invention it is possible to effectively enhance the control accuracy of the removal to the sacrificial gate dielectric layer, avoid described
The loss on fin surface.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A-Fig. 1 F are the device that is obtained respectively the step of implementation successively according to the method for exemplary embodiment of the present one
The vertical view of part；
Fig. 2A-Fig. 2 F are the schematic cross section for the device obtained along the trend of grid for corresponding respectively to Figure 1A-Fig. 1 F
Figure；
Fig. 3 is flow chart the step of implementation successively according to the method for exemplary embodiment of the present one.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
FinFET and its manufacturing method, electronic device.Obviously, execution of the invention is not limited to the technology of semiconductor applications
The specific details that personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
[exemplary embodiment one]
According to an exemplary embodiment of the present one method is shown successively in A- Fig. 1 F and Fig. 2A-Fig. 2 F referring to Fig.1
The device that the vertical view for the device that the step of implementation obtains respectively and the corresponding trend along grid obtain schematically cuts open
Face figure.
First, as shown in Figure 1A and Fig. 2A, semiconductor substrate 100 is provided, the constituent material of semiconductor substrate 100 can be adopted
With undoped monocrystalline silicon, doped with the monocrystalline silicon etc. of impurity.As an example, in the present embodiment, the structure of semiconductor substrate 100
At material selection monocrystalline silicon.
Next, forming fin 102 on a semiconductor substrate 100.To put it more simply, a fin is only shown in legend, this
Field technology personnel could be aware that, need to form multiple fins, the width whole phase of the fin on a semiconductor substrate 100
Together or the fin is divided into multiple fins groups with different in width.As an example, in the present embodiment, forming fin 102
The step of it is as follows：It is first sequentially depositing buried oxide layer 101 and silicon layer on a semiconductor substrate 100, the deposition can be low
Pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD
(UHVCVD), rapid thermal CVD (RTCVD), physical vapour deposition (PVD) (PVD), atomic layer deposition (ALD) and molecular beam
The material of one kind in extension (MBE), buried oxide layer 101 can be Si oxide, and the material of silicon layer can be monocrystalline silicon,
Its surface orientation is<110>、<100>Or other crystal orientation, to constitute the matrix of fin 102；The graphical silicon layer is with shape again
At fin 102, step includes：The photoresist layer that the pattern with fin 102 is formed on the silicon layer, with the photoresist
Layer is mask, etches the silicon layer, to form fin 102, the photoresist layer is removed by cineration technics.
It should be noted that following step can also be used to form fin 102：Being formed on a semiconductor substrate 100 has
The photoresist layer of the pattern of fin 102；Using the photoresist layer as mask, semiconductor substrate 100 is etched, to form fin 102,
The photoresist layer is removed by cineration technics.If forming fin 102 using latter approach, following dummy grids are being formed
Before structure, need to increase the step of gap between fin 102 forms isolation structure.The technique for forming the isolation structure
Step is familiar with by those skilled in the art, is not repeated here herein.
Then, as shown in fig. ib and fig. 2b, it includes the sacrifice grid stacked gradually to be formed in the both sides of fin 102 and top
The dummy gate structure of dielectric layer 104a and sacrificial gate material layer 104b.As an example, in the present embodiment, sacrificing gate dielectric
The material of layer 104a is silica, and the material of sacrificial gate material layer 104b is polysilicon.Form the side of the dummy gate structure
Method is well known in the art, is not repeated here herein.
Next, optionally, forming germanium silicon stressor layers 105 on the fin 102 that the dummy gate structure both sides are exposed.Make
Germanium silicon stressor layers 105, the selective epitaxial life are formed using selective epitaxial growth process in the present embodiment for example
It is true that low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), superelevation may be used in long technique
One kind in empty chemical vapor deposition (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
Then, as shown in figures 1C and 2C, interlevel dielectric deposition 106 cover the dummy gate structure, germanium silicon stressor layers
105, fin 102 and buried oxide layer 101.As an example, in the present embodiment, it is described to be deposited as low-pressure chemical vapor deposition
(LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermalization
Learn one kind in vapor deposition (RTCVD), physical vapour deposition (PVD) (PVD), atomic layer deposition (ALD) and molecular beam epitaxy (MBE).
Then, implement chemical mechanical grinding until exposing the top of the dummy gate structure.
Then, the dummy gate structure is removed, gate groove is left.As an example, in the present embodiment, removing the pseudo- grid
Pole structure includes the following steps：First the first dry etching is used to remove sacrificial gate material layer 104b, technological parameter includes：Erosion
The flow for carving gaseous-HBr is 30-300sccm, pressure 5-30mTorr, and power 200-1800W, wherein mTorr represent milli milli
Meter mercury column(unit of pressure), sccm represent cc/min, since the narrower in width of fin 102, height are very high, such as Fig. 1 D and Fig. 2 D
It is shown, after implementing the first dry etching, it can be remained by remaining sacrificial gate material layer in the both sides of fin 102 and top
The coating substances 104b ' that 104b and etch byproducts are collectively formed, it should be noted that the dotted line in Fig. 1 D is thrown for fin 102
Two boundary lines on shadow to buried oxide layer 101, also, the thickness of the coating substances 104b ' is inhomogenous, is located at
The part of the both sides of fin 102 is usually thicker；For another example shown in Fig. 1 E and Fig. 2 E, the second dry etching of Joint Implementation, surface
Processing and wet etching remove the coating substances 104b ' and sacrificial gate dielectric layer 104a, the second dry etching, surface treatment
Implementation order with wet etching is：Second dry etching → surface treatment → the second dry etching → surface treatment → wet method erosion
It carves, implements the second dry etching for the first time and implement surface treatment for the first time to remove the coating substances 104b ' with will be for the first time
The substance that second dry etching does not remove is converted into oxide, implement second of second dry etching with remove the oxide and
Sacrificial gate dielectric layer 104a implements second of surface treatment to remove the residue and impurity of aforementioned etching, implements wet method erosion
It carves to remove the sacrifice that second of second dry etching of the both sides and top that are located at the larger fin 102 of characteristic size does not remove
The residual fraction of gate dielectric 104a, wherein SiCoNi etchings, and institute may be used in the second dry etching twice of implementation
It states and contains a small amount of fluorine in the etching gas of SiCoNi etchings, percentage of the usual fluoro-gas in etching gas is no more than
10%, the deionized water dissolved with ozone, the wet etching of implementation may be used in the cleaning solution of the surface clean twice of implementation
Corrosive liquid hydrofluoric acid may be used.
Then, as shown in Fig. 1 F and Fig. 2 F, high k dielectric layer 107 is formed in gate groove, to cover buried oxide layer
101 and fin 102.
Next, metal gates 108 are formed, to cover high k dielectric layer 107 and interlayer dielectric layer 106.Then, execution
Mechanical lapping is learned until exposing the top of interlayer dielectric layer 106.
In one example, the k values (dielectric constant) of high k dielectric layer 107 are usually 3.9 or more, and constituent material includes
Hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, oxygen
Change barium titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably hafnium oxide, zirconium oxide or aluminium oxide.In one example, metal
Grid 108 includes workfunction setting metal layer, barrier layer and the metal gate material layer stacked gradually, wherein work function is set
Metal layer includes one or more layers metal or metallic compound, including titanium, tantalum, aluminium, zirconium, hafnium, ruthenium, palladium, platinum, tungsten and its alloy,
Further include carbide, the nitride etc. of above-mentioned metallic element；The material on barrier layer includes tantalum nitride or titanium nitride, metal gates material
The material of the bed of material includes tungsten or aluminium.It should be noted that can be between high k dielectric layer 107 and workfunction setting metal layer
Coating is formed, constituent material includes titanium nitride or tantalum nitride, and the effect for forming coating is to prevent workfunction setting metal
Diffusion of the metal material to high k dielectric layer in layer；Soakage layer can also be formed between barrier layer and metal gate material layer,
Its constituent material includes titanium or titanium-aluminium alloy, and the effect for forming soakage layer is improved between barrier layer and metal gate material layer
Interfacial characteristics, to put it more simply, being omitted in diagram.In one example, high k dielectric is formed using chemical vapor deposition method
Layer 107 forms metal gates 108 using atom layer deposition process or physical gas-phase deposition.
So far, the processing step that the method for completing according to an exemplary embodiment of the present one is implemented.It, can according to the present invention
Effectively to enhance the control accuracy of the removal to sacrificial gate dielectric layer 104a, the loss on 102 surface of fin is avoided.
The flow of the step of reference Fig. 3, the method for being shown according to an exemplary embodiment of the present one is implemented successively
Figure, the flow for schematically illustrating manufacturing process.
In step 301, semiconductor substrate is provided, is formed with fin on a semiconductor substrate；
In step 302, it includes the sacrificial gate dielectric layer stacked gradually and sacrifice to be formed in the both sides of fin and top
The dummy gate structure of gate material layers；
In step 303, interlevel dielectric deposition, to cover dummy gate structure, fin and semiconductor substrate；
In step 304, interlayer dielectric layer is ground, until exposing the top of dummy gate structure；
In step 305, the sacrificial gate material layer in dummy gate structure is removed；
Within step 306, the sacrifice in Joint Implementation dry etching, surface treatment and wet etching removal dummy gate structure
Gate dielectric.
[exemplary embodiment two]
Next, the making of entire FinFET can be completed by subsequent technique, it is possible to implement conventional FinFET
Device front end fabrication process：
In an exemplary embodiment, first, another interlayer dielectric layer is formed, interlayer dielectric layer 106 and metal are covered
Grid 108；Then, the top of connection metal gates 108 and the top of germanium silicon stressor layers 105 are formed in above-mentioned interlayer dielectric layer
The contact hole in portion, by the contact hole, in the top of the metal gates 108 of exposing and the top shape of germanium silicon stressor layers 105
At self-aligned silicide；Filling metal (being usually tungsten) forms connection in the contact hole and implements back end fabrication and formed
Interconnecting metal layer and the self-aligned silicide contact plug.
Next, it is possible to implement conventional FinFET back end fabrication, including：The shape of multiple interconnecting metal layers
It is completed at, generally use dual damascene process；The formation of metal pad, for implementing wire bonding when device encapsulation.
[exemplary embodiment three]
The present invention also provides a kind of electronic devices comprising two method manufactures according to an exemplary embodiment of the present
FinFET.The electronic device can be mobile phone, tablet computer, laptop, net book, game machine, television set,
Any electronic product such as VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products for including the semiconductor devices.The electronic device due to the use of the semiconductor devices, thus has
There is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacturing method of FinFET, including：
Semiconductor substrate is provided, is formed with fin on the semiconductor substrate；
It includes the sacrificial gate dielectric layer stacked gradually and sacrificial gate material layer to be formed in the both sides of the fin and top
Dummy gate structure；
Interlevel dielectric deposition, to cover the dummy gate structure, the fin and the semiconductor substrate；
Interlayer dielectric layer is ground, until exposing the top of the dummy gate structure；
Remove the sacrificial gate material layer in the dummy gate structure；
Joint Implementation dry etching, surface treatment and wet etching remove the sacrificial gate dielectric layer in the dummy gate structure.
2. according to the method described in claim 1, it is characterized in that, Joint Implementation dry etching, surface treatment and wet etching
Order be：Dry etching → surface treatment → dry etching → surface treatment → wet etching, the dry etching are
SiCoNi is etched, and the cleaning solution of the surface treatment is the deionized water dissolved with ozone, and the corrosive liquid of the wet etching is
Hydrofluoric acid.
3. according to the method described in claim 2, it is characterized in that, the etching gas of SiCoNi etchings includes containing fluorine gas
Body, percentage of the fluoro-gas in the etching gas are no more than 10%.
4. according to the method described in claim 1, it is characterized in that, removing the sacrificial gate material using another dry etching
Layer.
5. according to the method described in claim 1, being situated between it is characterized in that, depositing the interlayer after forming the dummy gate structure
Further include the steps that the formation germanium silicon stressor layers on the fin that the dummy gate structure both sides are exposed before electric layer.
6. according to the method described in claim 5, being answered it is characterized in that, forming the germanium silicon using selective epitaxial growth process
Power layer.
7. according to the method described in claim 1, it is characterized in that, after removing the sacrificial gate dielectric layer, under further including
State step：High k dielectric layer is formed, to cover the fin；Metal gates are formed, the high k dielectric layer and the interlayer are covered
Dielectric layer；Chemical mechanical grinding is executed until exposing the top of the interlayer dielectric layer.
8. the method according to the description of claim 7 is characterized in that the metal gates include the work function setting stacked gradually
Metal layer, barrier layer and metal gate material layer.
9. a kind of FinFET using the method manufacture described in one of claim 1-8.
10. a kind of electronic device, the electronic device includes the FinFET described in claim 9.
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| EP1043348A1 (en) * | 1997-12-26 | 2000-10-11 | Daikin Industries, Ltd. | Flexible heat-resistant material for office automation equipment and coating material |
| CN1726582A (en) * | 2002-12-20 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Method for manufacturing semiconductor device and semiconductor device obtained by the method |
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| CN1726582A (en) * | 2002-12-20 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Method for manufacturing semiconductor device and semiconductor device obtained by the method |
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