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CN105990237B - A kind of semiconductor devices and its manufacturing method, electronic device - Google Patents

A kind of semiconductor devices and its manufacturing method, electronic device Download PDF

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Publication number
CN105990237B
CN105990237B CN201510058666.7A CN201510058666A CN105990237B CN 105990237 B CN105990237 B CN 105990237B CN 201510058666 A CN201510058666 A CN 201510058666A CN 105990237 B CN105990237 B CN 105990237B
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layer
dielectric layer
semiconductor substrate
gate
interlayer dielectric
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CN105990237A (en
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肖莉红
徐建华
周洁鹏
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The present invention provides a kind of semiconductor devices and its manufacturing method, electronic device, which comprises provides the semiconductor substrate with first crystal area under control and second transistor area, is formed with dummy gate structure on a semiconductor substrate;The interlayer dielectric layer being made of hydrogenation agraphitic carbon is formed, on a semiconductor substrate to fill the gap between dummy gate structure;The sacrificial gate dielectric layer in dummy gate structure is removed, gate groove is obtained;Deposited metal gate material layers, to be filled up completely the gate groove.According to the present invention, the interlayer dielectric layer of formation have bigger consistency and hardness, implement chemical mechanical grinding when be not in pit defect.

Description

A kind of semiconductor devices and its manufacturing method, electronic device
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacturing method, electronics Device.
Background technique
In the manufacturing process of next generation's integrated circuit, for the system of the grid of complementary metal oxide semiconductor (CMOS) Make, generallys use post tensioned unbonded prestressed concrete (gate-last) technique.The process of typical post tensioned unbonded prestressed concrete technique includes: firstly, in semiconductor substrate Upper formation dummy gate structure, the dummy gate structure usually by be laminated from bottom to top boundary layer, high k dielectric layer, coating (capping layer) and sacrificial gate dielectric layer are constituted;Then, gate pitch wall construction is formed in the two sides of dummy gate structure, Contact etch stop layer and interlayer dielectric layer are sequentially formed on a semiconductor substrate and implement chemical mechanical grinding until exposing The top of dummy gate structure removes the sacrificial gate dielectric layer in dummy gate structure later;Then, it successively sinks in the groove left Product workfunction layers (workfunction metal layer), barrier layer (barrier layer) and soakage layer (wetting layer);Finally carry out the filling of metal gate (usually aluminium).Transistor arrangement using the production of above-mentioned technique is logical Frequently referred to high k dielectric layer/metal gate transistor.
With the continuous reduction of feature sizes of semiconductor devices, formed between dummy gate structure on a semiconductor substrate The depth-to-width ratio in gap constantly increases, and the constituent material of interlayer dielectric layer needs to have good fill out greater than 10 gap to depth-to-width ratio Ability is filled, therefore, the precursor material of tetraethoxysilane (TEOS) and ozone as interlevel dielectric deposition is usually selected, rear The continuous plasma-induced damage that when implementing heat treatment procedure, interlayer dielectric layer can also be effectively avoided to generate semiconductor substrate Wound.But, subsequent implementation chemistry poor using the mechanical strength that above-mentioned precursor material implementation deposition is formed by interlayer dielectric layer Mechanical lapping is during exposing the top of dummy gate structure, the interlayer dielectric of the gap location between dummy gate structure Layer, which can collapse, makes upper part pit defect occur, and then seriously affects the contact at the top of the subsequent high k dielectric layer/metal gate of electrical connection The formation of plug.To solve the above-mentioned problems, the prior art is usually to pass through implementation annealing to promote the close of interlayer dielectric layer Degree and hardness, and then increase its mechanical strength, still, this behave is unfavorable for the reduction of heat budget.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, comprising: providing has the The semiconductor substrate of one transistor area and second transistor area, is formed with dummy gate structure on the semiconductor substrate;Institute The interlayer dielectric layer that formation is made of hydrogenation agraphitic carbon in semiconductor substrate is stated, between filling between the dummy gate structure Gap;The sacrificial gate dielectric layer in the dummy gate structure is removed, gate groove is obtained;Deposited metal gate material layers, to fill out completely Fill the gate groove.
In one example, using plasma enhancing chemical vapor deposition process forms the interlayer dielectric layer, described Depositing the precursor used is the acetylene gas with argon-dilution.
In one example, the first crystal area under control is the area PMOS, and the second transistor area is NMOS area, alternatively, The first crystal area under control is NMOS area, and the second transistor area is the area PMOS.
In one example, interlayer dielectric layer is formed on the semiconductor substrate to fill between the dummy gate structure Gap the step of include: first to form the interlayer dielectric layer for covering the dummy gate structure on the semiconductor substrate, The first chemical mechanical grinding is executed again, until exposing the top of the dummy gate structure;Deposit the metal gate material layer it Before, it further include sequentially forming the step of workfunction setting metal layer, barrier layer and soakage layer in the side wall of the gate groove and bottom Suddenly;After depositing the metal gate material layer, further include the steps that executing the second chemical mechanical grinding, until exposing the layer Between dielectric layer top.
In one example, it is formed before the interlayer dielectric layer, further includes forming contact on the semiconductor substrate The step of hole etching stopping layer, the contact etch stop layer cover the dummy gate structure.
In one example, the material of the contact etch stop layer is the silicon nitride with tensile stress.
In one example, the removal of the sacrificial gate dielectric layer and the deposition of the metal gate material layer include following Step: first removal is located at the sacrificial gate dielectric layer in the first crystal area under control, deposits the first gold medal in the first gate groove left Belong to gate material layers;The sacrificial gate dielectric layer positioned at the second transistor area is removed again, is sunk in the second gate groove left The second metal gate material layer of product.
In one example, it is formed between the sacrificial gate dielectric layer and the semiconductor substrate and is laminated from bottom to top Boundary layer, high k dielectric layer and coating, side wall construction is formed in the two sides of the dummy gate structure, in the side wall knot It is formed with source/drain region in the semiconductor substrate of structure two sides, is formed with self-aligned silicide at the top of the source/drain region.
In one embodiment, the present invention also provides a kind of semiconductor devices manufactured using the above method.
In one embodiment, the present invention also provides a kind of electronic device, the electronic device includes the semiconductor device Part.
According to the present invention, the interlayer dielectric layer of formation has bigger consistency and hardness, implements chemical machinery and grinds It is not in pit defect when mill.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A-Fig. 1 F is the device that obtains respectively the step of successively implementation according to the method for exemplary embodiment of the present one The schematic cross sectional view of part;
Fig. 2 is flow chart the step of successively implementation according to the method for exemplary embodiment of the present one.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention Semiconductor devices and its manufacturing method, electronic device.Obviously, execution of the invention is not limited to the technology of semiconductor field The specific details that personnel are familiar with.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this Invention can also have other embodiments.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety, Step, operation, element, component and/or their combination.
[exemplary embodiment one]
The step of A- Fig. 1 F referring to Fig.1, the method for being shown according to an exemplary embodiment of the present one is successively implemented The schematic cross sectional view of the device obtained respectively.
Firstly, as shown in Figure 1A, providing semiconductor substrate 100, the constituent material of semiconductor substrate 100, which can use, not to be mixed Miscellaneous monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc..As an example, in the present embodiment, semiconductor Substrate 100 selects single crystal silicon material to constitute.Isolation structure 101 is formed in semiconductor substrate 100, as an example, isolation junction Structure 101 is shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure.Isolation structure 101 serves as a contrast semiconductor Bottom 100 is divided for different transistor areas, as an example, in the present embodiment, isolation structure 101, which divides semiconductor substrate 100, is The area PMOS and NMOS area.Various traps (well) structure is also formed in semiconductor substrate 100, to put it more simply, giving in diagram It omits.
It is formed with dummy gate structure 102 on a semiconductor substrate 100, as an example, dummy gate structure 102 may include High k dielectric layer 102a, coating 102b and the sacrificial gate dielectric layer 102c stacked gradually.K value (the dielectric of high k dielectric layer 102a Constant) be usually 3.9 or more, constituent material can for hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, Zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably aoxidize Hafnium, zirconium oxide and aluminium oxide.Coating 102b can inhibit the metal gate material in the metal gate structure being subsequently formed (logical Often it is aluminium) diffusion into high k dielectric layer 102a, constituent material may include titanium nitride and tantalum nitride.Sacrificial gate dielectric layer The material of 102c may include polysilicon.As another example, shape is gone back between high k dielectric layer 102a and semiconductor substrate 100 At interfacial TCO layer, to put it more simply, being omitted in diagram.Boundary layer can improve high k dielectric layer 102a and semiconductor substrate 100 Between interfacial characteristics, constituent material may include Si oxide (SiOx).Art technology can be used by forming above each layer The various suitable technologies that personnel are familiar with form boundary layer for example, by using thermal oxidation technology, using chemical vapor deposition Technique forms high k dielectric layer 102a and sacrificial gate dielectric layer 102c, using physical gas-phase deposition, chemical vapor deposition process Or atom layer deposition process forms coating 102b.
In addition, as an example, being formed with side wall construction 103 in the two sides of dummy gate structure 102, wherein side wall construction 103 Including at least oxide skin(coating) and/or nitride layer.The method for forming side wall construction 103 is known to those skilled in the art, This is not repeated here.
It is formed with source/drain region in the semiconductor substrate 100 of 103 two sides of side wall construction, in the source/drain region in the area PMOS It is formed with embedded germanium silicon layer, embedded carbon silicon layer is formed in the source/drain region of NMOS area, on the top of embedded germanium silicon layer It is formed with self-aligned silicide at the top of portion and embedded carbon silicon layer, to put it more simply, being omitted in diagram.It needs to illustrate It is that also can choose after the area PMOS and NMOS area are respectively formed the first metal gate structure and the second metal gate structure, It is formed in the interlayer dielectric layer being formed in semiconductor substrate 100 after contact hole again and forms institute in the bottom of the contact hole State self-aligned silicide.
Then, as shown in Figure 1B, the interlayer dielectric layer being made of hydrogenation agraphitic carbon is formed on a semiconductor substrate 100 105, cover dummy gate structure 102 and side wall construction 103.Then, chemical mechanical grinding is executed, until exposing dummy gate structure 102 top.Using plasma enhances chemical vapor deposition process and forms interlayer dielectric layer 105, before the deposition uses Body is the acetylene gas with argon-dilution.Before forming interlayer dielectric layer 105, it can also be formed on a semiconductor substrate 100 Contact etch stop layer 104 covers dummy gate structure 102 and side wall construction 103.It is familiar with using those skilled in the art Various suitable techniques form contact etch stop layer 104, stop for example, forming contact etch using conformal deposition process Silicon nitride or the silicon nitride with tensile stress may be selected in the material of layer 104, contact etch stop layer 104.
Then, as shown in Figure 1 C, removal is located at the sacrificial gate dielectric layer 102c in the dummy gate structure 102 of NMOS area, obtains To the first gate groove 106.As an example, sequentially forming unazotized 110 He of dielectric antireflective coatings on a semiconductor substrate 100 The material of patterned photoresist layer 111, dielectric antireflective coatings 110 can be silicon oxynitride, and thickness is not more than 200 angstroms;With Photoresist layer 111 is exposure mask, implements the removal, such as dry etching or wet etching using traditional handicraft, wherein dry method erosion Etching gas used in carving can be fluorine-based, chloro or bromine-based gas, and corrosive liquid used in wet etching can be tetramethyl Base Ammonia (TMAH), the dielectric antireflective coatings 110 also one during implementing the removal, positioned at NMOS area And it is removed;After implementing the removal, photoresist layer 111 is removed using cineration technics.
Then, wet cleaning processes are executed, to remove etch residues and impurity in the first gate groove 106.It is described wet The cleaning solution of method cleaning can be diluted hydrofluoric acid (DHF).
Then, as shown in figure iD, the first metal gate material layer 107 is deposited, to be filled up completely the first gate groove 106.So Afterwards, chemical mechanical grinding is executed, until exposing the top of interlayer dielectric layer 105.It further include the before implementing the deposition The step of side wall of one gate groove 106 and bottom sequentially form the first workfunction setting metal layer, barrier layer and soakage layer, in order to Simplify, is not shown the first workfunction setting metal layer, barrier layer and soakage layer in figure.Wherein, the first workfunction setting metal Layer includes one or more layers metal or metallic compound, suitable for the metal material of NMOS, including titanium, tantalum, aluminium, zirconium, hafnium and its Alloy further includes carbide, nitride of above-mentioned metallic element etc.;The material on barrier layer includes tantalum nitride or titanium nitride;Infiltration The material of layer includes titanium or titanium-aluminium alloy;The constituent material of first metal gate material layer 107 includes aluminium.Forming above each layer can With the various suitable technologies being familiar with using those skilled in the art, for example, by using atom layer deposition process or physics gas Phase depositing operation forms the first workfunction setting metal layer, forms resistance using atom layer deposition process or physical gas-phase deposition Barrier and soakage layer;First metal gate material layer 107 is formed using chemical vapor deposition process or physical gas-phase deposition.
Then, as referring to figure 1E, removal is located at the sacrificial gate dielectric layer 102c in the dummy gate structure 102 in the area PMOS, obtains To the second gate groove 108.The removal, such as dry etching or wet etching are completed using traditional handicraft, wherein dry etching Used etching gas can be fluorine-based, chloro or bromine-based gas, and corrosive liquid used in wet etching can be tetramethyl Ammonia.
Then, another wet cleaning processes are executed, to remove etch residues and impurity in the second gate groove 108.Institute The cleaning solution for stating wet-cleaning can be diluted hydrofluoric acid.
Then, as shown in fig. 1F, the second metal gate material layer 109 is deposited, to be filled up completely the second gate groove 108.So Afterwards, another chemical mechanical grinding is executed, until exposing the top of interlayer dielectric layer 105.Before implementing the deposition, further include In the step of side wall of the second gate groove 108 and bottom sequentially form the second workfunction setting metal layer, barrier layer and soakage layer, To put it more simply, being not shown the second workfunction setting metal layer, barrier layer and soakage layer in figure.Wherein, the second work function is set Metal layer includes one or more layers metal or metallic compound, and in the present embodiment, constituent material is the gold suitable for PMOS Belong to material, including titanium, ruthenium, palladium, platinum, tungsten and its alloy, further includes carbide, nitride of above-mentioned metallic element etc.;Barrier layer Material include tantalum nitride or titanium nitride;The material of soakage layer includes titanium or titanium-aluminium alloy;Second metal gate material layer 109 Constituent material includes aluminium.The various suitable technologies that above each layer can be familiar with using those skilled in the art are formed, The second workfunction setting metal layer is formed for example, by using atom layer deposition process or physical gas-phase deposition, using atomic layer deposition Product technique or physical gas-phase deposition form barrier layer and soakage layer;Using chemical vapor deposition process or physical vapour deposition (PVD) Technique forms the second metal gate material layer 109.
So far, the processing step that the method for completing according to an exemplary embodiment of the present one is implemented.Above-described embodiment is explained What is released is that first removal is located at the sacrificial gate dielectric layer 102c in the dummy gate structure 102 of NMOS area, forms the first metal gate later Pole structure is (including the first workfunction setting metal layer, barrier layer, soakage layer and the first metal gate material layer stacked gradually 107), then the sacrificial gate dielectric layer 102c in the dummy gate structure 102 in the area PMOS is removed, forms the second metal gates later Structure (including the second workfunction setting metal layer, barrier layer, soakage layer and the second metal gate material layer 109 stacked gradually) Implementation process;Those skilled in the art could be aware that, can also first remove in the dummy gate structure 102 in the area PMOS Sacrificial gate dielectric layer 102c, form the second metal gate structure later (including the second workfunction setting metal stacked gradually Layer, barrier layer, soakage layer and the second metal gate material layer 109), then remove in the dummy gate structure 102 of NMOS area Sacrificial gate dielectric layer 102c, formed later the first metal gate structure (including stack gradually the first workfunction setting metal layer, Barrier layer, soakage layer and the first metal gate material layer 107).According to the present invention, the interlayer dielectric layer 105 of formation has bigger Consistency and hardness, implement chemical mechanical grinding when be not in pit defect.
The process of the step of reference Fig. 2, the method for being shown according to an exemplary embodiment of the present one is successively implemented Figure, for schematically illustrating the process of manufacturing process.
In step 201, semiconductor substrate is provided, is formed with dummy gate structure on a semiconductor substrate;
In step 202, the interlayer dielectric layer being made of hydrogenation agraphitic carbon is formed, on a semiconductor substrate to fill puppet Gap between gate structure;
In step 203, the sacrificial gate dielectric layer in dummy gate structure is removed, gate groove is obtained;
In step 204, deposited metal gate material layers, to be filled up completely gate groove.
[exemplary embodiment two]
Next, the production of entire semiconductor devices can be completed by subsequent technique, comprising: in interlayer dielectric layer 105 It is upper to form another interlayer dielectric layer, cover the top of the first metal gate material layer 107 and the second metal gate material layer 109; Contact hole is formed in the interlayer dielectric layer, exposes the first metal gate material layer 107 and the second metal gate material layer 109 Top and the source/drain region being formed in semiconductor substrate 100 top;Fill metal (usually tungsten) shape in contact hole The contact plug of the interconnecting metal layer and the self-aligned silicide that are subsequently formed at connection;Multiple interconnecting metal layers are formed, usually It is completed using dual damascene process;Metal pad is formed, wire bonding when for the encapsulation of subsequent implementation device.
[exemplary embodiment three]
The present invention also provides a kind of electronic devices comprising the half of two method manufacture according to an exemplary embodiment of the present Conductor device.The electronic device can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD, Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, are also possible to any Intermediate products including the semiconductor devices.The electronic device due to having used the semiconductor devices, thus has more Good performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by The appended claims and its equivalent scope are defined.

Claims (9)

1. a kind of manufacturing method of semiconductor devices, comprising:
The semiconductor substrate for having first crystal area under control and second transistor area is provided, is formed with puppet on the semiconductor substrate Gate structure;
The interlayer dielectric layer being made of hydrogenation agraphitic carbon is formed, on the semiconductor substrate to fill the dummy gate structure Between gap;
The sacrificial gate dielectric layer in the dummy gate structure is removed, gate groove is obtained;
Deposited metal gate material layers, to be filled up completely the gate groove;
Wherein, the removal of the sacrificial gate dielectric layer and the deposition of the metal gate material layer are the following steps are included: first remove Sacrificial gate dielectric layer positioned at the first crystal area under control deposits the first metal gate material in the first gate groove left Layer;The sacrificial gate dielectric layer positioned at the second transistor area is removed again, deposits the second metal in the second gate groove left Gate material layers;After depositing the metal gate material layer, further include the steps that executing the second chemical mechanical grinding, until dew The top of the interlayer dielectric layer out.
2. the method according to claim 1, wherein using plasma enhancing chemical vapor deposition process is formed The interlayer dielectric layer, the precursor used that deposits is the acetylene gas with argon-dilution.
3. described second is brilliant the method according to claim 1, wherein the first crystal area under control is the area PMOS Body area under control is NMOS area, alternatively, the first crystal area under control is NMOS area, the second transistor area is the area PMOS.
4. the method according to claim 1, wherein forming interlayer dielectric layer on the semiconductor substrate to fill out The step of gap filled between the dummy gate structure includes: first to be formed to cover the dummy grid knot on the semiconductor substrate The interlayer dielectric layer of structure, then the first chemical mechanical grinding is executed, until exposing the top of the dummy gate structure;Deposition institute Before stating metal gate material layer, further include the side wall of the gate groove and bottom sequentially form workfunction setting metal layer, The step of barrier layer and soakage layer.
5. further including described the method according to claim 1, wherein being formed before the interlayer dielectric layer The step of contact etch stop layer is formed in semiconductor substrate, the contact etch stop layer covers the dummy grid knot Structure.
6. according to the method described in claim 5, it is characterized in that, the material of the contact etch stop layer is to answer with drawing The silicon nitride of power.
7. the method according to claim 1, wherein the sacrificial gate dielectric layer and the semiconductor substrate it Between be formed with the boundary layer being laminated from bottom to top, high k dielectric layer and coating, be formed with side in the two sides of the dummy gate structure Wall construction is formed with source/drain region in the semiconductor substrate of the side wall construction two sides, is formed at the top of the source/drain region There is self-aligned silicide.
8. a kind of semiconductor devices manufactured using method described in one of claim 1-7.
9. a kind of electronic device, the electronic device includes semiconductor devices according to any one of claims 8.
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CN108630608A (en) * 2017-03-17 2018-10-09 中芯国际集成电路制造(上海)有限公司 A kind of manufacturing method of semiconductor devices
CN111900131B (en) * 2020-07-03 2022-01-07 沈佳慧 Sealing ring structure of semiconductor wafer and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101971322A (en) * 2008-01-30 2011-02-09 东京毅力科创株式会社 Method of aftertreatment of amorphous hydrocarbon film and method for manufacturing electronic device by using the aftertreatment method
CN102915953A (en) * 2011-08-05 2013-02-06 中芯国际集成电路制造(上海)有限公司 Amorphous carbon film processing method and opening forming method
CN103021837A (en) * 2011-09-27 2013-04-03 中芯国际集成电路制造(上海)有限公司 Method of processing and forming amorphous carbon layer and production method of semiconductor device
CN103151250A (en) * 2011-12-06 2013-06-12 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device
CN103579111A (en) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 Method for manufacturing metal gate semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8377818B2 (en) * 2006-07-05 2013-02-19 Tokyo Electron Limited Aftertreatment method for amorphous carbon film

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101971322A (en) * 2008-01-30 2011-02-09 东京毅力科创株式会社 Method of aftertreatment of amorphous hydrocarbon film and method for manufacturing electronic device by using the aftertreatment method
CN102915953A (en) * 2011-08-05 2013-02-06 中芯国际集成电路制造(上海)有限公司 Amorphous carbon film processing method and opening forming method
CN103021837A (en) * 2011-09-27 2013-04-03 中芯国际集成电路制造(上海)有限公司 Method of processing and forming amorphous carbon layer and production method of semiconductor device
CN103151250A (en) * 2011-12-06 2013-06-12 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor device
CN103579111A (en) * 2012-07-26 2014-02-12 中芯国际集成电路制造(上海)有限公司 Method for manufacturing metal gate semiconductor device

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