CN111900131B - Sealing ring structure of semiconductor wafer and preparation method thereof - Google Patents
Sealing ring structure of semiconductor wafer and preparation method thereof Download PDFInfo
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- CN111900131B CN111900131B CN202010629707.4A CN202010629707A CN111900131B CN 111900131 B CN111900131 B CN 111900131B CN 202010629707 A CN202010629707 A CN 202010629707A CN 111900131 B CN111900131 B CN 111900131B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000007789 sealing Methods 0.000 title abstract description 17
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 239000002082 metal nanoparticle Substances 0.000 claims abstract description 88
- 229910052751 metal Inorganic materials 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 239000007769 metal material Substances 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 28
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 18
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 18
- 238000004528 spin coating Methods 0.000 claims description 15
- 229910052759 nickel Inorganic materials 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 239000003989 dielectric material Substances 0.000 claims description 9
- 229910052742 iron Inorganic materials 0.000 claims description 9
- 229910052763 palladium Inorganic materials 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000002207 thermal evaporation Methods 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 description 7
- 239000000126 substance Substances 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 238000003475 lamination Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002105 nanoparticle Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- FOIXSVOLVBLSDH-UHFFFAOYSA-N Silver ion Chemical compound [Ag+] FOIXSVOLVBLSDH-UHFFFAOYSA-N 0.000 description 1
- 208000013201 Stress fracture Diseases 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a sealing ring structure of a semiconductor wafer and a preparation method thereof, wherein the method comprises the following steps: forming a first groove and a second groove which are arranged in parallel in a seal ring area of a semiconductor substrate, sequentially forming a first metal nanoparticle layer, a first dielectric layer and a second metal nanoparticle layer in the first groove, depositing a metal material in the second groove to form a first metal layer, removing the second metal nanoparticle layer positioned outside the first groove and the first metal layer positioned outside the second groove through a planarization process, and then depositing a first metal/dielectric stack on the second metal nanoparticle layer to form a first seal ring; and depositing a second metal/dielectric stack on the first metal layer to form a second seal ring.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a sealing ring structure of a semiconductor wafer and a preparation method thereof.
Background
In a manufacturing process of a semiconductor wafer, a semiconductor chip including a semiconductor active device and an interconnection structure provided on the device may be formed on a semiconductor substrate through processes such as photolithography, etching, and deposition. Generally, a plurality of chips may be formed on a wafer, and finally, the chips are cut from the wafer and subjected to a packaging process to form an integrated circuit region. In the process of cutting the chip, the stress generated by the cutting knife can damage the edge of the chip, and even can cause the chip to collapse. The sealing ring is arranged on the periphery of an active device area of the chip, can prevent stress generated by a cutting knife from causing unwanted stress fracture of the active device area, can prevent water vapor from permeating chemical damage caused by diffusion of acid-containing substances, alkali-containing substances or pollution sources, and cannot well protect a semiconductor chip at present.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art and to provide a seal ring structure of a semiconductor wafer and a method for fabricating the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method for preparing a sealing ring structure of a semiconductor wafer comprises the following steps:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a scribing region, an integrated circuit region and a seal ring region positioned between the scribing region and the integrated circuit region, and a first groove and a second groove which are arranged in parallel are formed in the seal ring region of the semiconductor substrate, wherein the first groove is close to the scribing region, and the second groove is close to the integrated circuit region.
2) Then, a first mask is formed on the semiconductor substrate, and the first mask only exposes the first groove.
3) Then spin-coating a solution containing metal nanoparticles on the semiconductor substrate to form a first metal nanoparticle layer at the bottom of the first groove, then depositing a dielectric material on the first metal nanoparticle layer to form a first dielectric layer, then forming an opening on the first dielectric layer to expose the first metal nanoparticle layer, then spin-coating a solution containing metal nanoparticles to form a second metal nanoparticle layer on the first dielectric layer and in the opening, wherein the first metal nanoparticle layer, the first dielectric layer, and the second metal nanoparticle layer are embedded in the first groove, the first and second metal nanoparticle layers have a gap therebetween, and then removing the first mask.
4) Then, a second mask is formed on the semiconductor substrate, wherein the second mask only exposes the second groove.
5) And then depositing a metal material in the second groove to form a first metal layer, wherein the first metal layer fills the second groove, and then removing the second mask.
6) Removing the second metal nanoparticle layer located outside the first groove and the first metal layer located outside the second groove through a planarization process.
7) Then depositing a first metal/dielectric stack on the second layer of metal nanoparticles to form a first seal ring; and depositing a second metal/dielectric stack on the first metal layer to form a second seal ring.
Preferably, in step 1), the first groove and the second groove are both formed by wet etching or dry etching, and the depth of the first groove and the depth of the second groove are 1-3 micrometers.
Preferably, in the step 2), a photoresist is first coated on the semiconductor substrate to form a photoresist layer, the photoresist layer is then irradiated with ultraviolet light through a reticle, and then the photoresist in the unexposed region is removed through a developing process to expose the first recess.
Preferably, in the step 3), the material of the metal nanoparticles is one or more of gold, silver, copper, nickel, iron, cobalt, titanium and palladium, the particle diameter of the metal nanoparticles is 50-200 nm, the thickness of the first metal nanoparticle layer is 200-600 nm, and the thickness of the second metal nanoparticle layer is 600-2000 nm.
Preferably, in the step 3), the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide and tantalum oxide, and the first dielectric layer is prepared by one of plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition and chemical vapor deposition.
Preferably, in the step 4), a photoresist is first coated on the semiconductor substrate to form a photoresist layer, the photoresist layer is then irradiated with ultraviolet light through a reticle, and then the photoresist in the unexposed region is removed through a developing process to expose the second recess.
Preferably, in the step 5), the metal material includes one or more of copper, aluminum, silver, nickel, iron, palladium, titanium and nickel, and the first metal layer is formed by thermal evaporation, electroplating, electroless plating, magnetron sputtering or electron beam evaporation.
The invention also provides a sealing ring structure of the semiconductor wafer, which is prepared by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the preparation process of the seal ring structure of the semiconductor wafer, by forming a first groove and a second groove which are arranged in parallel in the seal ring area, and a first metal nanoparticle layer, a first dielectric layer, and a second metal nanoparticle layer are sequentially formed in the first groove, and the formation process of the first and second metal nanoparticle layers, because the spin coating process is adopted, gaps exist among the metal nano particles, and further the stress generated when the cutting knife cuts the semiconductor substrate can be absorbed, simultaneously depositing a metallic material in the second recess to form a first metallic layer and depositing a first metal/dielectric stack on the second metallic nanoparticle layer, and depositing a second metal/dielectric lamination on the first metal layer, and well blocking water vapor permeation through the arrangement of the double-sealing ring structure. Through the arrangement of the double-sealing ring structure, the metal nanoparticle layer is arranged in the first groove, the cutting stress can be prevented from further extending to the integrated circuit region by utilizing the gap existing in the metal nanoparticle layer, the water vapor permeation can be prevented by arranging the metal layer in the second groove, the manufacturing method is simple and easy to implement, and the double-sealing ring structure can be fused with the prior art.
Drawings
Fig. 1-5 are schematic structural diagrams illustrating a process for fabricating a seal ring structure of a semiconductor wafer according to the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, etc. may be used to describe semiconductor chips in embodiments of the present invention, these semiconductor chips should not be limited to these terms. These terms are only used to distinguish the semiconductor chips from one another. For example, the first semiconductor chip may also be referred to as a second semiconductor chip, and similarly, the second semiconductor chip may also be referred to as a first semiconductor chip, without departing from the scope of embodiments of the present invention.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 5, the present embodiment provides a method for manufacturing a seal ring structure of a semiconductor wafer, the method comprising the following steps:
as shown in fig. 1, step 1) is first performed, a semiconductor substrate 1 is provided, where the semiconductor substrate 1 may specifically be a silicon substrate, a germanium substrate, a silicon germanium substrate or a SOI substrate, the semiconductor substrate 1 includes a scribe region 11, an integrated circuit region 13, and a seal ring region 12 located between the scribe region 11 and the integrated circuit region 13, and a first groove 121 and a second groove 122 are formed in the seal ring region 12 of the semiconductor substrate 1 and are arranged in parallel, where the first groove 121 is close to the scribe region, and the second groove 122 is close to the integrated circuit region.
Specifically, the integrated circuit region 13 includes devices such as a field effect transistor, a resistor, a capacitor, an inductor, and a diode, and the semiconductor substrate 1 includes a plurality of integrated circuit regions 13 arranged in a matrix.
Specifically, the first groove and the second groove are both formed by wet etching or dry etching, the depth of the first groove and the second groove is 1 to 3 micrometers, more specifically, the depth of the first groove 121 may be 1 micrometer, 1.5 micrometer, 2 micrometer, 2.5 micrometer, or 3 micrometer, the depth of the second groove may be 1 micrometer, 1.5 micrometer, 2 micrometer, 2.5 micrometer, or 3 micrometer, and in a specific embodiment, the depth of the second groove may be equal to or greater than the depth of the first groove.
As shown in fig. 2, step 2) is performed next, a first mask 2 is formed on the semiconductor substrate 1, and the first mask 2 exposes only the first recess 121.
In the step 2), a photoresist layer is first formed on the semiconductor substrate 1, and then the photoresist layer is irradiated with ultraviolet light through a mask, and then the photoresist in the unexposed region is removed through a developing process to expose the first recess 121.
Followed by step 3), followed by spin-coating a solution containing metal nanoparticles on the semiconductor substrate 1 to form a first metal nanoparticle layer 31 at the bottom of the first groove, a dielectric material is then deposited on the first layer of metal nanoparticles 31 to form a first dielectric layer 32, openings are then formed in the first dielectric layer 32 to expose the first metal nanoparticle layer 31, followed by spin coating a solution containing metal nanoparticles to form a second metal nanoparticle layer 33 on the first dielectric layer and in the openings, wherein the first metal nanoparticle layer 31, the first dielectric layer 32, and the second metal nanoparticle layer 33 are embedded in the first groove 121, the first and second metal nanoparticle layers 31 and 33 have a gap (not shown) therein, and then the first mask (not shown) is removed.
In the step 3), the material of the metal nanoparticles is one or more of gold, silver, copper, nickel, iron, cobalt, titanium and palladium, the particle size of the metal nanoparticles is 50-200 nm, the thickness of the first metal nanoparticle layer is 200-600 nm, and the thickness of the second metal nanoparticle layer is 600-2000 nm. The spin coating of the solution containing metal nanoparticles is performed at a rotation speed of 2000-5000 rpm for 1-5 minutes, followed by a drying process at 120 ℃ for 10-20 minutes to remove the solvent, and a plurality of spin coating/drying processes are performed to form the first metal nanoparticle layer 31 and the second metal nanoparticle layer 33, respectively, with appropriate thicknesses. The dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and tantalum oxide, and the first dielectric layer 32 is formed by one of plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, and chemical vapor deposition.
In a specific embodiment, the metal nanoparticles may be silver nanoparticles or copper nanoparticles, the metal nanoparticles preferably have a particle size of 80-150 nm, the first metal nanoparticle layer preferably has a thickness of 200 nm, 250 nm, 300 nm, 400 nm, 500 nm or 600 nm, and the second metal nanoparticle layer preferably has a thickness of 600 nm, 700 nm, 900 nm, 1200 nm, 1400 nm, 1600 nm, 1800 nm or 2000 nm. The rotation speed of spin-coating the solution containing the metal nanoparticles is preferably 3000-4000 rpm, more preferably 3500 rpm, the spin-coating time is preferably 2-4 minutes, more preferably 3 minutes, then a baking treatment is performed at 110 ℃ for 15 minutes to remove the solvent, and the first metal nanoparticle layer 31 and the second metal nanoparticle layer 33 are formed by a plurality of spin-coating/baking treatments, respectively, the dielectric material is preferably a silicon oxide/silicon nitride stacked structure, and the first dielectric layer 32 is formed by plasma enhanced chemical vapor deposition.
As shown in fig. 3, step 4) is then performed, and then a second mask 4 is formed on the semiconductor substrate 1, the second mask 4 exposing only the second recess 122.
In the step 4), a photoresist is first coated on the semiconductor substrate 1 to form a photoresist layer, the photoresist layer is then irradiated with ultraviolet light through a mask, and then the photoresist in the unexposed region is removed through a developing process to expose the second recess 122.
Then, step 5) is performed, a metal material is deposited in the second recess 122 to form a first metal layer 5, the first metal layer 5 fills the second recess 122, and the second mask 4 is removed (not shown).
The metal material includes one or more of copper, aluminum, silver, nickel, iron, palladium, titanium, and nickel, the first metal layer 5 is formed by thermal evaporation, electroplating, chemical plating, magnetron sputtering, or electron beam evaporation, in a specific embodiment, the metal material is specifically copper or aluminum, and the first metal layer 5 is formed by thermal evaporation.
As shown in fig. 4, step 6) is then performed, and the second metal nanoparticle layer 33 located outside the first groove 121 and the first metal layer 5 located outside the second groove 122 are removed by a planarization process.
Specifically, the second metal nanoparticle layer outside the first groove and the first metal layer outside the second groove may be removed by a chemical mechanical masking process, so as to obtain a flat upper surface.
As shown in fig. 5, followed by step 7), followed by depositing a first metal/dielectric stack 6 on the second metal nanoparticle layer 33 to form a first seal ring; and a second metal/dielectric stack 7 is deposited on said first metal layer 5 to form a second seal ring.
The specific preparation method of the first metal/dielectric lamination 6 and the second metal/dielectric lamination 7 comprises the following steps: depositing a dielectric layer on the substrate, specifically depositing the dielectric layer by using a chemical vapor deposition method, a low-pressure chemical vapor deposition method, a plasma-enhanced chemical vapor deposition method or a physical vapor deposition method, wherein the material of the dielectric layer is preferably one or more of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, then performing laser opening on the dielectric layer to expose part of the second metal nanoparticle layer 33 and part of the first metal layer 5, then filling metal into the opening to form a metal plug, and depositing a metal layer on the dielectric layer, wherein the material of the metal plug and the material of the metal layer comprise one or more of copper, aluminum, silver, nickel, iron, palladium, titanium and nickel, the metal plug and the metal layer are formed by thermal evaporation, electroplating, magnetron sputtering or electron beam evaporation, the metal layer is then patterned using a mask and the above steps are repeated a plurality of times to simultaneously form the first metal/dielectric stack 6 and the second metal/dielectric stack 7.
The invention also provides a sealing ring structure of the semiconductor wafer, which is prepared by adopting the method.
In the preparation process of the seal ring structure of the semiconductor wafer, by forming a first groove and a second groove which are arranged in parallel in the seal ring area, and a first metal nanoparticle layer, a first dielectric layer, and a second metal nanoparticle layer are sequentially formed in the first groove, and the formation process of the first and second metal nanoparticle layers, because the spin coating process is adopted, gaps exist among the metal nano particles, and further the stress generated when the cutting knife cuts the semiconductor substrate can be absorbed, simultaneously depositing a metallic material in the second recess to form a first metallic layer and depositing a first metal/dielectric stack on the second metallic nanoparticle layer, and depositing a second metal/dielectric lamination on the first metal layer, and well blocking water vapor permeation through the arrangement of the double-sealing ring structure. Through the arrangement of the double-sealing ring structure, the metal nanoparticle layer is arranged in the first groove, the cutting stress can be prevented from further extending to the integrated circuit region by utilizing the gap existing in the metal nanoparticle layer, the water vapor permeation can be prevented by arranging the metal layer in the second groove, the manufacturing method is simple and easy to implement, and the double-sealing ring structure can be fused with the prior art.
The invention provides a sealing ring structure of a semiconductor wafer and a preparation method thereof.
Item 1: a method for preparing a sealing ring structure of a semiconductor wafer comprises the following steps:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a scribing region, an integrated circuit region and a seal ring region positioned between the scribing region and the integrated circuit region, and a first groove and a second groove which are arranged in parallel are formed in the seal ring region of the semiconductor substrate, wherein the first groove is close to the scribing region, and the second groove is close to the integrated circuit region.
2) Then, a first mask is formed on the semiconductor substrate, and the first mask only exposes the first groove.
3) Then spin-coating a solution containing metal nanoparticles on the semiconductor substrate to form a first metal nanoparticle layer at the bottom of the first groove, then depositing a dielectric material on the first metal nanoparticle layer to form a first dielectric layer, then forming an opening on the first dielectric layer to expose the first metal nanoparticle layer, then spin-coating a solution containing metal nanoparticles to form a second metal nanoparticle layer on the first dielectric layer and in the opening, wherein the first metal nanoparticle layer, the first dielectric layer, and the second metal nanoparticle layer are embedded in the first groove, the first and second metal nanoparticle layers have a gap therebetween, and then removing the first mask.
4) Then, a second mask is formed on the semiconductor substrate, wherein the second mask only exposes the second groove.
5) And then depositing a metal material in the second groove to form a first metal layer, wherein the first metal layer fills the second groove, and then removing the second mask.
6) Removing the second metal nanoparticle layer located outside the first groove and the first metal layer located outside the second groove through a planarization process.
7) Then depositing a first metal/dielectric stack on the second layer of metal nanoparticles to form a first seal ring; and depositing a second metal/dielectric stack on the first metal layer to form a second seal ring.
Item 2: in the step 1), the first groove and the second groove are both formed by wet etching or dry etching, and the depth of the first groove and the second groove is 1-3 microns.
Item 3: in the step 2), a photoresist is first coated on the semiconductor substrate to form a photoresist layer, the photoresist layer is then irradiated with ultraviolet light through a reticle, and then the photoresist in an unexposed region is removed through a developing process to expose the first recess.
Item 4: in the step 3), the material of the metal nanoparticles is one or more of gold, silver, copper, nickel, iron, cobalt, titanium and palladium, the particle size of the metal nanoparticles is 50-200 nm, the thickness of the first metal nanoparticle layer is 200-600 nm, and the thickness of the second metal nanoparticle layer is 600-2000 nm.
Item 5: in the step 3), the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and tantalum oxide, and the first dielectric layer is prepared by one of plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, and chemical vapor deposition.
Item 6: in the step 4), a photoresist is first coated on the semiconductor substrate to form a photoresist layer, the photoresist layer is then irradiated with ultraviolet light through a reticle, and then the photoresist in the unexposed region is removed through a developing process to expose the second recess.
Item 7: in the step 5), the metal material includes one or more of copper, aluminum, silver, nickel, iron, palladium, titanium and nickel, and the first metal layer is formed by thermal evaporation, electroplating, electroless plating, magnetron sputtering or electron beam evaporation.
Item 8: the invention also provides a sealing ring structure of the semiconductor wafer, which is prepared by adopting the method.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A method for preparing a seal ring structure of a semiconductor wafer is characterized by comprising the following steps: the method comprises the following steps:
1) providing a semiconductor substrate, wherein the semiconductor substrate comprises a scribing region, an integrated circuit region and a seal ring region positioned between the scribing region and the integrated circuit region, and a first groove and a second groove which are arranged in parallel are formed in the seal ring region of the semiconductor substrate, wherein the first groove is close to the scribing region, and the second groove is close to the integrated circuit region;
2) then forming a first mask on the semiconductor substrate, wherein the first mask only exposes the first groove;
3) then spin-coating a solution containing metal nanoparticles on the semiconductor substrate to form a first metal nanoparticle layer at the bottom of the first groove, then depositing a dielectric material on the first metal nanoparticle layer to form a first dielectric layer, then forming an opening on the first dielectric layer to expose the first metal nanoparticle layer, then spin-coating a solution containing metal nanoparticles to form a second metal nanoparticle layer on the first dielectric layer and in the opening, wherein the first metal nanoparticle layer, the first dielectric layer, and the second metal nanoparticle layer are embedded in the first groove, the first and second metal nanoparticle layers have a gap therebetween, and then removing the first mask;
4) then forming a second mask on the semiconductor substrate, wherein the second mask only exposes the second groove;
5) depositing a metal material in the second groove to form a first metal layer, filling the second groove with the first metal layer, and removing the second mask;
6) removing the second metal nanoparticle layer positioned outside the first groove and the first metal layer positioned outside the second groove through a planarization process;
7) then depositing a first metal/dielectric stack on the second layer of metal nanoparticles to form a first seal ring; and depositing a second metal/dielectric stack on the first metal layer to form a second seal ring.
2. The method of claim 1, wherein the step of forming the seal ring structure comprises: in the step 1), the first groove and the second groove are both formed by wet etching or dry etching, and the depth of the first groove and the second groove is 1-3 microns.
3. The method of claim 1, wherein the step of forming the seal ring structure comprises: in the step 2), a photoresist is first coated on the semiconductor substrate to form a photoresist layer, the photoresist layer is then irradiated with ultraviolet light through a reticle, and then the photoresist in an unexposed region is removed through a developing process to expose the first recess.
4. The method of claim 1, wherein the step of forming the seal ring structure comprises: in the step 3), the material of the metal nanoparticles is one or more of gold, silver, copper, nickel, iron, cobalt, titanium and palladium, the particle size of the metal nanoparticles is 50-200 nm, the thickness of the first metal nanoparticle layer is 200-600 nm, and the thickness of the second metal nanoparticle layer is 600-2000 nm.
5. The method of claim 4, wherein the step of preparing the seal ring structure of the semiconductor wafer comprises: in the step 3), the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and tantalum oxide, and the first dielectric layer is prepared by one of plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, and chemical vapor deposition.
6. The method of claim 1, wherein the step of forming the seal ring structure comprises: in the step 4), a photoresist is first coated on the semiconductor substrate to form a photoresist layer, the photoresist layer is then irradiated with ultraviolet light through a reticle, and then the photoresist in the unexposed region is removed through a developing process to expose the second recess.
7. The method of claim 1, wherein the step of forming the seal ring structure comprises: in the step 5), the metal material includes one or more of copper, aluminum, silver, nickel, iron, palladium, titanium and nickel, and the first metal layer is formed by thermal evaporation, electroplating, electroless plating, magnetron sputtering or electron beam evaporation.
8. A seal ring structure of a semiconductor wafer, characterized in that it is formed by a method according to any one of claims 1 to 7.
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| US12100670B2 (en) | 2021-03-26 | 2024-09-24 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor structure and semiconductor structure |
| CN113078140B (en) * | 2021-03-26 | 2022-05-20 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| US12300492B2 (en) | 2021-03-26 | 2025-05-13 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor structure, and semiconductor structure |
| CN113471163B (en) * | 2021-07-23 | 2023-06-20 | 重庆平创半导体研究院有限责任公司 | Wafer interconnection structure and process |
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| JP2011165745A (en) * | 2010-02-05 | 2011-08-25 | Mitsubishi Electric Corp | Ceramic package |
| CN105990313A (en) * | 2015-02-17 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Sealing ring of chip |
| CN105990237A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
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| JP2011165745A (en) * | 2010-02-05 | 2011-08-25 | Mitsubishi Electric Corp | Ceramic package |
| CN105990237A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof, and electronic device |
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