CN107492496B - Semiconductor structure and its manufacturing method - Google Patents

Abstract

A semiconductor structure and a manufacturing method thereof, the method comprising: providing a substrate, the substrate has fins; forming an isolation structure on the substrate between the fins, the fin protruding from the isolation structure as the first fin region; forming a gate structure across the fin and covering part of the top surface and sidewall surface of the first region of the fin; using the gate structure as a mask, performing first light doping on one side of the first region of the fin process, the doping ions are the first ions; using the gate structure as a mask, a second light doping process is performed on the other side of the first region of the fin, the doping ions are the second ions, and the second ion type is the same as the first The first ion type is the same, and the atomic mass of the second ion is smaller than the atomic mass of the first ion; after the first light doping process and the second light doping process, the substrate is annealed. Through the combination of the first ions and the second ions, not only the quality of the fin portion is improved, but also the short channel effect of the device is improved, thereby optimizing the electrical performance of the semiconductor device.

Description

Semiconductor structure and manufacturing method thereof

technical field

The invention relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

In semiconductor manufacturing, with the development trend of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to the reduction of feature size, the channel length of MOSFET field effect transistors is also continuously shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to better adapt to the reduction of feature size, the semiconductor process gradually begins to transition from planar MOSFET transistors to three-dimensional three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistors (FinFETs). In FinFET, the gate can control the ultra-thin body (fin) from at least two sides, which has a much stronger gate-to-channel control ability than planar MOSFET devices, and can well suppress short-channel effects; and FinFET is relatively Compared with other devices, it has better compatibility with the existing integrated circuit manufacturing technology.

However, the electrical properties of semiconductor devices formed in the prior art still need to be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor structure and its manufacturing method to optimize the electrical performance of the semiconductor device.

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate has fins; forming an isolation structure on the substrate between the fins, wherein the The fin of the isolation structure is used as the first region of the fin; a gate structure is formed across the fin, and the gate structure covers part of the top surface and the sidewall surface of the first region of the fin; The gate structure is a mask, and a first lightly doped process is performed on one side of the first region of the fin to form a first lightly doped ion region, and the dopant ion of the first lightly doped process is the first Ions; using the gate structure as a mask, perform a second lightly doped process on the other side of the first region of the fin to form a second lightly doped ion region, the second lightly doped process The dopant ion is a second ion, wherein the second ion type is the same as the first ion type, and the atomic mass of the second ion is smaller than the atomic mass of the first ion; the first light doping process After the second light doping process, an annealing process is performed on the substrate.

Optionally, the substrate is used to form an N-type device, and the first ions and the second ions are N-type ions.

Optionally, the first ions are As ions, and the second ions are P ions.

Optionally, the parameters of the first light doping process include: implanted ion energy is 1Kev to 8Kev, implanted ion dose is 1E14 to 8E14 atoms per square centimeter, and implantation angle is 7 degrees to 20 degrees.

Optionally, the parameters of the second light doping process include: implanted ion energy is 1Kev to 6Kev, implanted ion dose is 1E14 to 5E14 atoms per square centimeter, and implantation angle is 7 degrees to 20 degrees.

Optionally, the annealing process is laser annealing, spike annealing or rapid thermal annealing process.

Optionally, the annealing process is a spike annealing process; the process parameters of the annealing process include: the annealing temperature is 900 degrees Celsius to 1050 degrees Celsius, the pressure is a standard atmospheric pressure, the reaction gas is nitrogen, and the gas flow rate of nitrogen is 5 per minute Standard rose to 40 standard liters per minute.

Optionally, after performing an annealing process on the substrate, the manufacturing method further includes: forming source-drain doped regions in the fins on both sides of the gate structure.

Optionally, the substrate includes a first region and a second region, the substrate in the first region is used to form an N-type device, and the substrate in the second region is used to form a P-type device; The fins on the regional substrate are first fins, the fins on the second regional substrate are second fins; the first fins protruding from the first regional isolation structure are first fins The first region of the first region, the second fin protruding from the isolation structure of the second region is the first region of the second fin; in the step of performing the first lightly doped process on one side of the first region of the fin performing a first lightly doped process on one side of the first region of the first fin; performing a second lightly doped process on the other side of the first region of the fin, the first performing a second light doping process on the other side of the first region of the fin; before performing an annealing process on the substrate, the manufacturing method further includes: performing a third light doping process on the first region of the second fin process to form a third lightly doped ion region.

Optionally, the parameters of the third light doping process include: the implanted ion energy is 2Kev to 8Kev, the implanted ion dose is 8E13 to 5E14 atoms per square centimeter, and the implantation angle is 7 degrees to 20 degrees.

Optionally, the step of performing an annealing process on the substrate includes: performing an annealing process on the first lightly doped ion region, the second lightly doped ion region and the third lightly doped ion region at the same time, so as to activate the ion .

Correspondingly, the present invention also provides a semiconductor structure, including: a substrate having fins; an isolation structure located on the substrate between the fins, wherein the fins protruding from the isolation structure The part serves as the first region of the fin; the gate structure spans the fin and covers part of the top surface and the sidewall surface of the first region of the fin; the first lightly doped ion region is located in the first region of the fin On one side of a region, the doping ions of the first lightly doped ion region are first ions; the second lightly doped ion region is located on the other side of the first region of the fin, and the first lightly doped ion region is located on the other side of the first region of the fin. The doping ions in the second lightly doped ion region are second ions, wherein the second ion type is the same as the first ion type, and the atomic mass of the second ion is smaller than the atomic mass of the first ion.

Optionally, the semiconductor structure is an N-type device, and the first ions and the second ions are N-type ions.

Optionally, the first ions are As ions, and the second ions are P ions.

Optionally, the ion concentration of the first lightly doped ion region is 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.

Optionally, the ion concentration of the second lightly doped ion region is 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter.

Optionally, the semiconductor structure further includes: source and drain doped regions located in the fins on both sides of the gate structure.

Optionally, the substrate includes a first region and a second region, the semiconductor structure in the first region is an N-type device, the semiconductor structure in the second region is a P-type device; The fin on the bottom is the first fin, the fin located on the substrate in the second region is the second fin; the first fin protruding from the isolation structure in the first region is the first fin and the second fin. A region, the second fin protruding from the isolation structure of the second region is the first region of the second fin; the first lightly doped ion region is located on one side of the first region of the first fin ; the second lightly doped ion region is located on the other side of the first region of the first fin; the semiconductor structure further includes: a third lightly doped ion region located in the first region of the second fin ion region.

Optionally, the dopant ions in the third lightly doped ion region include boron ions, and the ion concentration of the third lightly doped ion region is 8E13 atoms per cubic centimeter to 5E14 atoms per cubic centimeter.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the present invention, the first light doping process is performed on one side of the first region of the fin, and the dopant ions in the first light doping process are first ions, and the other side of the first region of the fin is Performing a second light doping process, the dopant ions of the second light doping process are second ions, wherein the second ion type is the same as the first ion type, and the atomic mass of the second ion is less than the set Atomic mass of the first ion. On the one hand, only one side of the first region of the fin is doped with heavier ions to prevent the fins on the other side of the first region of the fin from being transformed into amorphous due to doping with heavier ions. state, so that during the subsequent annealing process, the part of the first region of the fin that is not bombarded by the first ions provides more single crystal material, so as to prevent the first region of the fin from being difficult to repair due to the lack of single crystal material single-crystal state, thereby improving the quality of the fin; on the other hand, by only doping the other side of the first region of the fin with lighter-weight ions, avoiding too many lighter-weight ions Laterally diffused into the channel region, thereby improving the short channel efficiency of the device. Therefore, through the combination of the first ions and the second ions, not only the quality of the fin portion is improved, but also the short channel effect of the device is improved, thereby optimizing the electrical performance of the semiconductor device.

In the semiconductor structure provided by the present invention, the first lightly doped ion region is located on one side of the first region of the fin, and the doping ions of the first lightly doped ions are first ions; the first lightly doped ion region is the first ion; Two lightly doped ion regions are located on the other side of the first region of the fin, and the doping ions of the second lightly doped ions are second ions; wherein, the second ion type is the same as the first ion type The ion types are the same, and the atomic mass of the second ion is smaller than the atomic mass of the first ion. On the one hand, prevent the other side of the first region of the fin from being bombarded by heavy first ions during the formation process of the first lightly doped ion region from being transformed from a single crystal state into an amorphous state, so that the non-crystalline state The portion of the first region of the fin bombarded by the first ions provides more single crystalline material during the fin repair process to reconvert the amorphous material to single crystalline material, thereby improving the quality of the fin. ; On the other hand, it can avoid excessive lateral diffusion of ions with lighter mass to the channel region of the device, thereby improving the short channel effect of the device. Therefore, through the combination of the first ions and the second ions, not only the quality of the fin portion is improved, but also the short channel effect of the device is improved, so that the electrical performance of the semiconductor device is optimized.

Description of drawings

Fig. 1 and Fig. 2 are a kind of structure diagram corresponding to each step in the manufacturing method of semiconductor structure;

Fig. 3 is a schematic diagram of an electron microscope of a semiconductor structure;

4 to 13 are schematic diagrams of structures corresponding to each step in an embodiment of the manufacturing method of the semiconductor structure of the present invention.

Detailed ways

It can be seen from the background art that the electrical performance of the FinFET formed in the prior art still needs to be improved.

Combined with a method of forming a semiconductor structure, the reason is analyzed. Referring to FIG. 1 and FIG. 2 together, a schematic structural diagram corresponding to each step in a manufacturing method of a semiconductor structure is shown.

Referring to FIG. 1 , a substrate 100 is provided with fins 110 thereon; an isolation structure 101 is formed on the substrate 100 between the fins 110 , wherein the fins 110 exposed to the isolation structure serve as a first region of the fin (not labeled); forming a gate structure 102 across the fin 110, the gate structure 102 covering part of the top surface and sidewall surfaces of the first region of the fin; The gate structure 102 is a mask, and a lightly doped process 120 is performed on the first region of the fin to form a lightly doped ion region (not shown).

In the above method, the substrate 100 is used to form an N-type device; the dopant ions in the light doping process 120 are N-type ions. Specifically, the N-type ions include As ions or P ions.

However, when the dopant ions of the light doping process 120 are P ions, since the atomic mass of the P ions is relatively light, when the light doping process 120 is performed, it is easy to laterally diffuse to the channel region of the device, thereby easily It has adverse effects on the short-channel effects (SCE: short-channel effects) of the device, and then has an adverse effect on the electrical performance of the semiconductor device.

When the doping ions of the light doping process 120 are As ions, refer to FIG. 2 and FIG. 3 in combination. FIG. 2 is a schematic cross-sectional structure diagram along the AA1 direction of FIG. 1 , and FIG. 3 is an electron microscope image of region B in FIG. 2 . Due to the heavy atomic mass of As ions, after the first region of the fin is bombarded by As ions, the material on both sides of the first region of the fin is easily converted from a single crystal state to an amorphous state, that is, the two sides are transformed into Amorphous layer 111 (as shown in FIG. 2 ); after the subsequent annealing process, the amorphous layer 110 is easily repaired into a single crystal state due to the lack of single crystal material, and is transformed into the amorphous layer 110 The more severe the phenomenon (i.e., the more material in the first fin region is converted to the amorphous layer 110), the more difficult it is to repair the first fin region, resulting in a decrease in the quality of the first fin region, which in turn adversely affect the electrical performance of semiconductor devices.

In order to solve the technical problem, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, the substrate has fins; forming an isolation structure on the substrate between the fins, wherein the protruding the fin portion of the isolation structure as a fin portion first region; forming a gate structure across the fin portion, the gate structure covering part of the top surface and the sidewall surface of the fin portion first region; The gate structure is a mask, and a first lightly doped process is performed on one side of the first region of the fin to form a first lightly doped ion region, and the dopant ions in the first lightly doped process are First ions; using the gate structure as a mask, perform a second lightly doped process on the other side of the first region of the fin to form a second lightly doped ion region, the second lightly doped The dopant ion of the process is a second ion, wherein the second ion type is the same as the first ion type, and the atomic mass of the second ion is smaller than the atomic mass of the first ion; the first lightly doped After the impurity process and the second light doping process, the substrate is annealed.

In the present invention, the first light doping process is performed on one side of the first region of the fin, and the dopant ions in the first light doping process are first ions, and the other side of the first region of the fin is Performing a second light doping process, the dopant ions of the second light doping process are second ions, wherein the second ion type is the same as the first ion type, and the atomic mass of the second ion is less than the set Atomic mass of the first ion. On the one hand, only one side of the first region of the fin is doped with heavier ions to prevent the fins on the other side of the first region of the fin from being transformed into amorphous due to doping with heavier ions. state, so that during the subsequent annealing process, the part of the first region of the fin that is not bombarded by the first ions provides more single crystal material, so as to prevent the first region of the fin from being difficult to repair due to the lack of single crystal material single-crystal state, thereby improving the quality of the fin; on the other hand, by only doping the other side of the first region of the fin with lighter-weight ions, avoiding too many lighter-weight ions Laterally diffused into the channel region, thereby improving the short channel efficiency of the device. Therefore, through the combination of the first ions and the second ions, not only the quality of the fin portion is improved, but also the short channel effect of the device is improved, thereby optimizing the electrical performance of the semiconductor device.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

4 to 13 are schematic diagrams of structures corresponding to each step in an embodiment of the manufacturing method of the semiconductor structure of the present invention.

4 and 5 in combination, wherein, FIG. 4 is a perspective view of a semiconductor structure (only two fins are shown), and FIG. 5 is a schematic cross-sectional structure diagram of FIG. 4 along CC1 direction, providing a substrate 200, the substrate 200 Has fins (not shown).

The substrate 200 provides a process platform for subsequent formation of semiconductor devices.

In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. substrate.

In this embodiment, the substrate 200 includes a first region I (as shown in FIG. 5 ) and a second region II (as shown in FIG. 5 ). Correspondingly, the fins located on the substrate 200 in the first region I are the first fins 210 , and the fins located on the substrate 200 in the second region II are the second fins 220 .

The material of the first fin 210 and the second fin 220 is the same as that of the substrate 200 . In this embodiment, the material of the first fin portion 210 and the second fin portion 220 is silicon. In other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

In this embodiment, the first region I is used to form N-type devices, and the second region II is used to form P-type devices. In another embodiment, the first region is used to form a P-type device, and the second region is used to form an N-type device. In other embodiments, both the first region and the second region are used to form N-type devices.

Specifically, the step of providing the substrate 200 and the fins includes: providing an initial base, forming a patterned hard mask layer 300 on the initial base; using the hard mask layer 300 as a mask, etching The initial base forms several discrete protrusions; the protrusions are fins, and the etched initial base serves as a substrate 200, the substrate 200 includes a first region I and a second region II, located in the The fins in the first region I are the first fins 210 , and the fins in the second region II are the second fins 220 .

In this embodiment, the material of the hard mask layer 300 is silicon nitride, and when the planarization process is performed subsequently, the surface of the hard mask layer 300 is used to define the stop position of the planarization process, and the hard mask layer The film layer 300 can also protect the top of the first fin 210 and the top of the second fin 220 .

It should be noted that after the substrate 200 and the fins are provided, the manufacturing method further includes: forming a pad oxide layer (not shown) on the surfaces of the first fins 210 and the second fins 220 , using for repairing the first fin portion 210 and the second fin portion 220 .

During the oxidation process, since the protruding corners of the first fin 210 and the second fin 220 have a larger specific surface area, they are more likely to be oxidized. After the subsequent removal of the pad oxide layer, not only the first The defect layer on the surface of the first fin 210 and the second fin 220 is removed, and the protruding corners are also removed, so that the surface of the first fin 210 and the second fin 220 is smooth, and the lattice quality is improved. Avoiding the discharge problem at the top corners of the first fin portion 210 and the second fin portion 220 is beneficial to improve the performance of the FinFET.

In this embodiment, the pad oxide layer is also located on the surface of the substrate 200, and the material of the pad oxide layer is silicon oxide.

Unless otherwise specified, the structural schematic diagrams provided in the subsequent process are all schematic diagrams based on FIG. 5 .

Referring to FIG. 6 , an isolation structure 201 is formed on the substrate 200 between the fins (not shown), wherein the fin protruding from the isolation structure 201 serves as a first fin region (not shown).

The isolation structure 201 is used as an isolation structure of a semiconductor structure for isolating adjacent devices. In this embodiment, the material of the isolation structure 201 is silicon oxide. In other embodiments, the material of the isolation structure 201 may also be silicon nitride, silicon oxynitride or silicon oxycarbonitride.

It should be noted that, in this embodiment, the isolation structure 201 is a shallow trench isolation layer, but is not limited to a shallow trench isolation layer.

In this embodiment, the fins include a first fin 210 located on the substrate 200 in the first region I, and a second fin 210 located on the substrate 200 in the second region II. Correspondingly, the first fin portion 210 protruding from the isolation structure 201 in the first region I is the first region of the first fin portion (not marked); the second fin portion protruding from the isolation structure 201 in the second region II Portion 220 is the first region of the second fin (not shown).

Specifically, the step of forming the isolation structure 201 includes: forming an isolation film on the pad oxide layer (not shown), the top of the isolation film is higher than the hard mask layer 300 (as shown in FIG. 5 (shown) top; grinding and removing the isolation film higher than the top of the hard mask layer 300; removing part of the thickness of the isolation film to form the isolation structure 201; removing the hard mask layer 300.

It should be noted that part of the pad oxide layer on the surface of the fin is also removed while part of the thickness of the isolation film is removed.

Referring to FIG. 7 , a gate structure (not shown) is formed across the fin (not shown), the gate structure covers part of the top surface and the sidewall surface of the first region (not shown) of the fin.

In this embodiment, the gate structure includes a first gate structure 211 across the first region (not marked) of the first fin, and the first gate structure 211 covers the first fin of the first fin. Part of the top surface and sidewall surface of a region; also includes a second gate structure 221 across the first region (not labeled) of the second fin, the second gate structure 221 covers the second fin part of the top surface and sidewall surface of the first region.

In this embodiment, the gate structure is a dummy gate structure, and the gate structure is used to occupy a space position for subsequent formation of a metal gate structure.

The gate structure is a single-layer structure or a stacked structure, and the gate structure includes a dummy gate layer, or the gate structure includes a dummy oxide layer and a dummy gate layer located on the surface of the dummy oxide layer. The material of the dummy oxide layer is silicon oxide, and the material of the dummy gate layer is polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. In this embodiment, the material of the dummy gate layer is polysilicon.

In another embodiment, the gate structure is a metal gate structure. The gate structure includes a gate dielectric layer and a gate electrode layer located on the surface of the gate dielectric layer, wherein the material of the gate dielectric layer is silicon oxide or a high-k gate dielectric material, and the material of the gate electrode layer is polysilicon or metal Material, the metal material includes one or more of Ti, Ta, TiN, TaN, TiAl, TiAlN, Cu, Al, W, Ag or Au.

In this embodiment, it is taken as an example that the gate structure is a dummy gate structure. The process steps of forming the gate structure include: forming a dummy gate film on the isolation structure 201, the dummy gate film covering the fins (not shown); performing a planarization process on the dummy gate film; A pattern layer (not shown) is formed on the surface of the dummy gate film, and the pattern layer defines the pattern of the gate structure to be formed; using the pattern layer as a mask, patterning the dummy gate film, in the A first gate structure 211 is formed on the surface of the first fin portion 210 , and a second gate structure 221 is also formed on the surface of the second fin portion 220 .

It should be noted that, after forming the first gate structure 211 and the second gate structure 221, the manufacturing method further includes: forming a first sidewall (first region) on the sidewall of the first gate structure 211 ( Not shown in the figure), forming a first sidewall in the second region (not shown in the figure) on the sidewall of the second gate structure 221 .

The material of the first sidewall in the first region and the first sidewall in the second region can be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride or carbon For boron nitride, the first sidewall in the first region and the first sidewall in the second region can be a single-layer structure or a laminated structure. In this embodiment, the first sidewall in the first region and the first sidewall in the second region have a single-layer structure, and the material of the first sidewall in the first region and the first sidewall in the second region is silicon nitride .

Referring to FIG. 8 and FIG. 9, FIG. 8 is a schematic structural diagram based on FIG. 4, wherein FIG. 8 only shows one fin, and FIG. 9 is a schematic cross-sectional structural schematic diagram of FIG. ) as a mask, and perform a first lightly doped process 231 on one side of the first region (not shown) of the fin to form a first lightly doped ion region (not shown in the figure), and the first lightly doped The dopant ions in process 231 are the first ions.

Specifically, the step of forming the first lightly doped ion region includes: forming a first pattern layer 310 on the substrate 200 in the second region II, and the first pattern layer 310 also covers the second gate Pole structure 221: using the first pattern layer 310 and the first side wall (not shown) in the first region as a mask, perform a first lightening on one side of the first region (not shown) of the first fin Doping process 231 .

In this embodiment, after the formation of the first lightly doped ion region, the first pattern layer 310 remains, and the first pattern layer 310 also serves as a mask layer for a subsequent doping process.

In this embodiment, the first region I substrate 200 is used to form an N-type device, and correspondingly, the first ions are N-type ions.

In this embodiment, the first ions are As ions. Specifically, the parameters of the first light doping process 231 include: the implantation angle is 7 degrees to 20 degrees.

It should be noted that the implanted ion energy should not be too large, nor should it be too small. If the implanted ion energy is too small, it will be difficult for the ions to be implanted into the preset depth of the first region of the first fin; if the implanted ion energy If it is too large, it is easy to deteriorate the short channel effect, resulting in a decrease in the electrical performance of the device. Therefore, in this embodiment, the ion energy implanted in the first light doping process 231 is 1Kev to 8Kev.

It should be noted that the dose of implanted ions should not be too large, nor should it be too small. If the implanted ion dose is too small, the resistance of the first fin portion 210 will increase easily; if the implanted ion dose is too large, the short channel effect will be deteriorated, resulting in a decrease in the electrical performance of the device. Therefore, in this embodiment, the ion dose implanted in the first light doping process 231 is 1E14 to 8E14 atoms per square centimeter.

Referring to FIG. 8 and FIG. 10 in conjunction, FIG. 10 is a schematic structural diagram based on FIG. 9 , using the gate structure (not marked) as a mask to perform the second step on the other side of the first region (not marked) of the fin Second light doping process 232, forming a second lightly doped ion region (not shown in the figure), the doping ions of the second lightly doping process are second ions, wherein the second ion type is the same as the first ion type An ion of the same type, the atomic mass of the second ion is smaller than the atomic mass of the first ion.

Specifically, the step of forming the second lightly doped ion region includes: using the first pattern layer 310 and the first sidewall (not shown in the figure) in the first region as a mask, to the first region of the first fin The other side (not shown) is subjected to a second light doping process 232; the first pattern layer 310 is removed.

In this embodiment, the first pattern layer 310 is a photoresist layer. The first graphic layer 310 is removed by wet stripping or ashing process.

In this embodiment, the first region I substrate 200 is used to form N-type devices, the first ions are N-type ions, and correspondingly, the second ions are N-type ions.

In this embodiment, the second ions are P ions. Specifically, the parameters of the second light doping process 232 include: the implantation angle is 7 degrees to 20 degrees.

It should be noted that the implanted ion energy should not be too large, nor should it be too small. If the implanted ion energy is too small, it will be difficult for the ions to be implanted into the preset depth of the first region of the first fin; if the implanted ion energy If it is too large, it is easy to deteriorate the short channel effect, resulting in a decrease in the electrical performance of the device. Therefore, in this embodiment, the energy of ions implanted in the second light doping process 232 is 1Kev to 6Kev.

It should also be noted that the dose of implanted ions should not be too large, nor should it be too small. If the implanted ion dose is too small, the resistance of the first fin portion 210 will increase easily; if the implanted ion dose is too large, the short channel effect will be deteriorated, resulting in a decrease in the electrical performance of the device. Therefore, in this embodiment, the ion dose implanted in the second light doping process 232 is 1E14 to 5E14 atoms per square centimeter.

Referring to FIG. 11 , FIG. 11 is a cross-sectional view of a partial structure of the first area I in FIG. 8 . In this embodiment, the doping ions of the first light doping process 231 are As ions, and the doping ions of the second light doping process 232 are P ions;

It should be noted that, on the one hand, due to the heavy atomic mass of As ions, after one side of the first region (not shown) of the first fin is bombarded by As ions, the material is converted from a single crystal state to an amorphous state, That is, one side is transformed into an amorphous layer 215 (as shown in FIG. 11 ), but the material on the other side is still in a single crystal state because it is not bombarded by As ions; therefore, in the subsequent annealing process, the Part of the first region of the first fin can provide more single crystal material, so that the first region of the first fin can be repaired, and the amorphous layer 215 can be converted into a single crystal layer again, so as to improve the The quality of the first fin portion 210; on the other hand, because the atomic mass of P ions is relatively light, by only carrying out P ion doping to the other side of the first region of the first fin portion, too much light mass can be avoided. The P ions diffuse laterally to the channel region of the device, which can improve the short channel effect of the device.

Therefore, the combination of As ions and P ions not only improves the quality of the first fin 210 but also improves the short channel effect of the device, thereby optimizing the electrical performance of the semiconductor device.

It should also be noted that, after the first light doping process 231 (as shown in FIG. 9 ) and the second light doping process 232 (as shown in FIG. 10 ), the manufacturing method further includes: A third lightly doped process (not shown) is performed on the first region (not shown) of the second fin to form a third lightly doped ion region (not shown), and the doped ions are third ions.

In this embodiment, the second region II substrate 200 is used to form P-type devices, and correspondingly, the third ions are P-type ions. Specifically, the parameters of the third light doping process include: the implanted ions include boron ions, the implanted ion energy is 2Kev to 8Kev, the implanted ion dose is 8E13 to 5E14 atoms per square centimeter, and the implantation angle is 7 degrees to 20 degrees .

It should also be noted that in this embodiment, the first lightly doped process 231 and the second lightly doped process 232 are performed on the first region of the first fin first, and then the first region of the second fin is performing the third light doping process; in another embodiment, the third light doping process may be firstly performed on the first region of the second fin, and then the first a lightly doped process and a second lightly doped process.

Referring to FIG. 12 , after the first light doping process 231 (as shown in FIG. 9 ) and the second light doping process 232 (as shown in FIG. 10 ), an annealing process 400 is performed on the substrate 200 .

In this embodiment, the step of performing the annealing process 400 on the substrate 200 includes: simultaneously treating the first lightly doped ion region (not shown in the figure), the second lightly doped ion region (not shown in the figure) and the first lightly doped ion region (not shown in the figure) Three lightly doped ion regions (not shown) are annealed 400 to activate ions.

After performing the annealing process 400, the first ions, the second ions and the third ions are activated, and the annealing process 400 can also repair the lattice damage in the first region of the fin, and the The amorphous material in the first region of the first fin is converted into a single crystal material, that is, after the annealing process 400, the amorphous layer 215 (as shown in FIG. 11 ) is converted into a single crystal material. crystalline layer.

In this embodiment, the annealing process 400 is a spike annealing process. In other embodiments, laser annealing or rapid thermal annealing can also be used to perform the annealing process.

It should be noted that, in order to activate the first ions, the second ions and the third ions, and promote the transformation of the amorphous material in the first region of the first fin into a single crystal material, avoid The first ions, the second ions and the third ions, and the first light doping process 231 (as shown in FIG. 9 ), the second light doping process 232 (as shown in FIG. 10 ) and the third light doping process The distribution of ions implanted in the ion doping process before the impurity process will cause adverse effects, and the process parameters of the annealing process 400 need to be controlled within a reasonable range.

Specifically, the process parameters of the spike annealing process include: the annealing temperature is 750 degrees Celsius to 1000 degrees Celsius, the pressure is one standard atmospheric pressure, the reaction gas is nitrogen, and the gas flow rate of nitrogen gas is 5 standard liters per minute to 40 standard liters per minute.

With reference to FIG. 13 , it should be noted that after the annealing process 400 (as shown in FIG. 12 ) is performed on the substrate 200, the manufacturing method further includes: forming source and drain in the fins on both sides of the gate structure doped region (not shown).

In this embodiment, the first region I substrate 200 is used to form N-type devices, and the second region II substrate 200 is used to form P-type devices.

Correspondingly, the source-drain doped region includes: a first source-drain doped region (not shown) located in the first fin portion 210 on both sides of the first gate structure 211; The second source-drain doped regions (not shown) in the second fin portion 220 on both sides of the pole structure 221 . Wherein, the ion type of the first source-drain doped region is N-type, and the ion type of the second source-drain doped region is P-type.

In another embodiment, the substrate in the first region is used to form a P-type device, and the substrate in the second region is used to form an N-type device. Correspondingly, the ion type of the first source-drain doped region is P-type, and the ion type of the second source-drain doped region is N-type. In yet another embodiment, both the substrate in the first region and the substrate in the second region are used to form N-type devices, and correspondingly, the ions in the first source-drain doped region and the second source-drain doped region All types are N-type.

In this embodiment, the step of forming the source-drain doped region includes: forming a first stress layer 212 in the first fin portion 210 on both sides of the first gate structure 211; The second stress layer 222 is formed in the second fin portion 220 on both sides of 221; the first source-drain doped region is formed in the first stress layer 212; the second source-drain doped region is formed in the second stress layer 222. Miscellaneous area.

In this embodiment, in the process of forming the first stress layer 212, in-situ self-doping treatment is used to form the first source-drain doped region; in the process of forming the second stress layer 222, in-situ Self-doping process forms the second source-drain doping region.

In other embodiments, after forming the first stress layer 212, the first stress layer 212 may be heavily doped to form the first source-drain doped region; After the second stress layer 222, the second stress layer 222 is heavily doped to form the second source-drain doped region.

It should also be noted that, after performing the annealing process 400 (as shown in FIG. 12 ) on the substrate 200 and before forming the source-drain doped regions, the manufacturing method further includes: A second side wall (not shown) in the first region is formed on the surface of the side wall (not shown in the figure); a second side wall (not shown in the figure) in the second region is formed on the surface of the first side wall (not shown in the figure). ).

The material of the second sidewall in the first region and the second sidewall in the second region may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride or carbon For boron nitride, the second sidewall in the first region and the second sidewall in the second region may have a single-layer structure or a laminated structure. In this embodiment, the second sidewall in the first region and the second sidewall in the second region have a single-layer structure, and the material of the second sidewall in the first region and the second sidewall in the second region is silicon nitride

In this embodiment, a first light doping process 231 (as shown in FIG. 9 ) is performed on one side of the first region (not marked) of the first fin, and the doping ions in the first light doping process 231 are The first ions are used to perform a second light doping process 232 (as shown in FIG. 10 ) on the other side of the first region of the fin, and the doping ions in the second light doping process 232 are second ions, wherein, The second ion type is the same as the first ion type, and the atomic mass of the second ion is less than the atomic mass of the first ion. The problem that the first region of the first fin is difficult to repair is avoided, and the short channel effect of the device is improved, thereby optimizing the electrical performance of the semiconductor device.

Continuing to refer to FIG. 13, the present invention also provides a semiconductor structure, including:

a substrate 200, the substrate 200 has fins (not labeled);

an isolation structure 201 located on the substrate 200 between the fins, wherein the fin protruding from the isolation structure 201 serves as a first region of the fin (not marked);

a gate structure (not shown) spanning the fin and covering part of the top surface and sidewall surface of the first region of the fin;

a first lightly doped ion region (not shown in the figure), located on one side of the first region of the fin, and the doping ions in the first lightly doped ion region are first ions;

The second lightly doped ion region (not shown in the figure) is located on the other side of the first region of the fin, and the doping ions in the second lightly doped ion region are second ions, wherein the first The two ion types are the same as the first ion type, and the atomic mass of the second ion is less than the atomic mass of the first ion.

In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. substrate.

In this embodiment, the substrate 200 includes a first region I and a second region II. Correspondingly, the fins located on the substrate 200 in the first region I are the first fins 210 , and the fins located on the substrate 200 in the second region II are the second fins 220 .

The material of the first fin 210 and the second fin 220 is the same as that of the substrate 200 . In this embodiment, the material of the first fin portion 210 and the second fin portion 220 is silicon. In other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

In this embodiment, the semiconductor structure in the first region I is an N-type device, and the semiconductor structure in the second region II is a P-type device. In another embodiment, the semiconductor structure in the first region is a P-type device, and the semiconductor structure in the second region is an N-type device. In other embodiments, the semiconductor structures in the first region and the second region are both N-type devices.

The isolation structure 201 is used as an isolation structure of a semiconductor structure for isolating adjacent devices. In this embodiment, the material of the isolation structure 201 is silicon oxide. In other embodiments, the material of the isolation structure 201 may also be silicon nitride, silicon oxynitride or silicon oxycarbonitride.

It should be noted that, in this embodiment, the isolation structure 201 is a shallow trench isolation layer, but is not limited to a shallow trench isolation layer.

Correspondingly, the first fin portion 210 protruding from the isolation structure 201 in the first region I is the first region of the first fin portion (not marked); the second fin portion protruding from the isolation structure 201 in the second region II Portion 220 is the first region of the second fin (not shown).

Correspondingly, the first lightly doped ion region is located on one side of the first region of the first fin; the second lightly doped ion region is located on the other side of the first region of the first fin. side.

In this embodiment, the semiconductor structure in the first region I is an N-type device, and correspondingly, the first ions and the second ions are N-type ions. Specifically, the first ions are As ions, and the second ions are P ions.

It should be noted that the ion concentration of the first lightly doped ion region and the second lightly doped ion region should not be too high, nor should it be too low. If the ion concentration is too low, the resistance of the first fin portion 210 will increase easily; if the ion concentration is too high, the short channel effect will be deteriorated, thereby reducing the electrical performance of the device. Therefore, in this embodiment, the ion concentration of the first lightly doped ion region is 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter; the ion concentration of the second lightly doped ion region is 1E19 atoms per cubic centimeter cm to 5E20 atoms per cubic centimeter.

It should be noted that the semiconductor structure further includes: a third lightly doped ion region (not shown) located in the first region (not shown) of the second fin, and the dopant ions are third ions.

In this embodiment, the semiconductor structure in the second region II is a P-type device, and correspondingly, the third ions are P-type ions. Specifically, the third ions include boron ions, and the ion concentration of the third lightly doped ion region is 8E13 atoms per cubic centimeter to 5E14 atoms per cubic centimeter.

In this embodiment, the gate structure includes a first gate structure 211 across the first region (not marked) of the first fin, and the first gate structure 211 covers the first fin of the first fin. Part of the top surface and sidewall surface of a region; also includes a second gate structure 221 across the first region (not labeled) of the second fin, the second gate structure 221 covers the second fin part of the top surface and sidewall surface of the first region.

The gate structure is a metal gate structure. The gate structure includes a gate dielectric layer and a gate electrode layer located on the surface of the gate dielectric layer, wherein the material of the gate dielectric layer is silicon oxide or a high-k gate dielectric material, and the material of the gate electrode layer is polysilicon or metal Material, the metal material includes one or more of Ti, Ta, TiN, TaN, TiAl, TiAlN, Cu, Al, W, Ag or Au. In this embodiment, the metal material is W.

It should also be noted that the semiconductor structure further includes: doped source and drain regions (not shown) located in the fins on both sides of the gate structure.

Specifically, the source-drain doped region includes: a first source-drain doped region (not shown) located in the first fin portion 210 on both sides of the first gate structure 211; The second source-drain doped regions (not shown) in the second fin portion 220 on both sides of the pole structure 221 . Wherein, the ion type of the first source-drain doped region is N-type, and the ion type of the second source-drain doped region is P-type.

In another embodiment, the semiconductor structure in the first region is a P-type device, and the semiconductor structure in the second region is an N-type device. Correspondingly, the ion type of the first source-drain doped region is P type, the ion type of the second source-drain doped region is N-type. In yet another embodiment, the semiconductor structures in the first region and the second region are both N-type devices, and correspondingly, the ion types of the first source-drain doped region and the second source-drain doped region are both Type N.

In this embodiment, the semiconductor structure further includes: a first stress layer 212 located in the first fins 210 on both sides of the first gate structure 211 , a second fin located on both sides of the second gate structure 221 The second stress layer 222 in the portion 220 ; wherein, the first source-drain doped region is located in the first stress layer 212 , and the second source-drain doped region is located in the second stress layer 222 .

The first lightly doped ion region (not shown) is located on one side of the first fin region (not shown), and the doping ions of the first lightly doped ions are first ions; The second lightly doped ion region (not shown) is located on the other side of the first region of the first fin, and the doping ions of the second lightly doped ions are second ions; wherein, the The second ion type is the same as the first ion type, and the atomic mass of the second ion is less than the atomic mass of the first ion. On the one hand, prevent the other side of the first region of the first fin from being bombarded by heavy first ions during the formation of the first lightly doped ion region from being transformed from a single crystal state to an amorphous state, thereby Part of the first region of the fin not bombarded by As ions provides more single-crystal material during the repair process of the first fin 210, so as to reconvert the amorphous material into a single-crystal material, thereby improving the first fin 210. The quality of the fin portion 210; on the other hand, it can avoid excessive lateral diffusion of ions with lower mass to the channel region of the device, thereby improving the short channel effect of the device. Therefore, through the combination of the first ions and the second ions, not only the quality of the first fin 210 is improved, but also the short channel effect of the device is improved, so that the electrical performance of the semiconductor device is optimized.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (19)

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate having fins; forming an isolation structure on the substrate between the fins, wherein the fin protruding from the isolation structure serves as a first region of the fin; forming a gate structure across the fin, the gate structure covering a portion of a top surface and a sidewall surface of the first region of the fin; Using the gate structure as a mask, perform a first lightly doped process on one side of the first region of the fin to form a first lightly doped ion region, and the dopant ions in the first lightly doped process is the first ion; Using the gate structure as a mask, perform a second lightly doped process on the other side of the first region of the fin to form a second lightly doped ion region, and the doping in the second lightly doped process the ion is a second ion, wherein the second ion type is the same as the first ion type, and the atomic mass of the second ion is less than the atomic mass of the first ion; After the first light doping process and the second light doping process, the substrate is annealed. 2. The method for manufacturing a semiconductor structure according to claim 1, wherein the substrate is used to form an N-type device, and the first ions and the second ions are N-type ions. 3. The method for manufacturing a semiconductor structure according to claim 1, wherein the first ions are As ions, and the second ions are P ions. 4. The method for manufacturing a semiconductor structure according to claim 3, wherein the parameters of the first light doping process include: implanted ion energy is 1Kev to 8Kev, implanted ion dose is 1E14 to 8E14 atoms per square centimeter, and the injection angle is 7 degrees to 20 degrees. 5. The method for manufacturing a semiconductor structure according to claim 3, wherein the parameters of the second light doping process include: implanted ion energy is 1Kev to 6Kev, implanted ion dose is 1E14 to 5E14 atoms per square centimeter, and the injection angle is 7 degrees to 20 degrees. 6. The method for manufacturing a semiconductor structure according to claim 1, wherein the annealing process is laser annealing, spike annealing or rapid thermal annealing process. 7. The method for manufacturing a semiconductor structure according to claim 6, wherein the annealing process is a spike annealing process; The process parameters of the annealing process include: the annealing temperature is 900 to 1050 degrees Celsius, the pressure is one standard atmospheric pressure, the reaction gas is nitrogen, and the gas flow rate of nitrogen is 5 standard liters per minute to 40 standard liters per minute. 8. The method for manufacturing a semiconductor structure according to claim 1, wherein after performing an annealing process on the substrate, the manufacturing method further comprises: forming source and drain in the fins on both sides of the gate structure doped region. 9. The method for manufacturing a semiconductor structure according to claim 1, wherein the substrate comprises a first region and a second region, the first region substrate is used to form an N-type device, and the second region The regional substrate is used to form a P-type device; The fins located on the substrate in the first region are first fins, and the fins located on the substrate in the second region are second fins; The first fin protruding from the first region isolation structure is the first fin portion first region, and the second fin portion protruding from the second region isolation structure is the second fin portion first region; In the step of performing a first lightly doped process on one side of the first region of the fin, performing a first lightly doped process on one side of the first region of the first fin; In the step of performing a second lightly doped process on the other side of the first region of the fin, performing a second lightly doped process on the other side of the first region of the first fin; Before performing the annealing process on the substrate, the manufacturing method further includes: performing a third lightly doped process on the first region of the second fin to form a third lightly doped ion region. 10. The method for manufacturing a semiconductor structure according to claim 9, wherein the parameters of the third light doping process include: the implanted ions include boron ions, the energy of the implanted ions is 2Kev to 8Kev, and the implanted ions The dose is 8E13 to 5E14 atoms per square centimeter, and the implantation angle is 7 degrees to 20 degrees. 11. The method for manufacturing a semiconductor structure according to claim 9, wherein the step of annealing the substrate comprises: simultaneously annealing the first lightly doped ion region and the second lightly doped ion region An annealing process is performed on the third lightly doped ion region to activate the ions. 12. A semiconductor structure, characterized in that, comprising: a substrate having fins; an isolation structure located on the substrate between the fins, wherein the fin protruding from the isolation structure serves as a first region of the fin; a gate structure spanning the fin and covering a portion of the top surface and sidewall surfaces of the first region of the fin; The first lightly doped ion region is located on one side of the first region of the fin, and the doping ions in the first lightly doped ion region are first ions; The second lightly doped ion region is located on the other side of the first region of the fin, and the dopant ions in the second lightly doped ion region are second ions, wherein the second ion type is the same as the second ion type. The same type of the first ion, the atomic mass of the second ion is less than the atomic mass of the first ion. 13. The semiconductor structure according to claim 12, wherein the semiconductor structure is an N-type device, and the first ions and the second ions are N-type ions. 14. The semiconductor structure according to claim 12, wherein the first ions are As ions, and the second ions are P ions. 15. The semiconductor structure according to claim 14, wherein the ion concentration of the first lightly doped ion region is 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter. 16. The semiconductor structure according to claim 14, wherein the ion concentration of the second lightly doped ion region is 1E19 atoms per cubic centimeter to 5E20 atoms per cubic centimeter. 17 . The semiconductor structure according to claim 12 , further comprising: source-drain doped regions located in the fins on both sides of the gate structure. 18. The semiconductor structure according to claim 12, wherein the substrate comprises a first region and a second region, the semiconductor structure in the first region is an N-type device, and the semiconductor structure in the second region It is a P-type device; The fins located on the substrate in the first region are first fins, and the fins located on the substrate in the second region are second fins; The first fin protruding from the first region isolation structure is the first fin portion first region, and the second fin portion protruding from the second region isolation structure is the second fin portion first region; The first lightly doped ion region is located on one side of the first region of the first fin; The second lightly doped ion region is located on the other side in the first region of the first fin; The semiconductor structure further includes: a third lightly doped ion region located in the first region of the second fin. 19. The semiconductor structure according to claim 18, wherein the dopant ions in the third lightly doped ion region include boron ions, and the ion concentration of the third lightly doped ion region is 8E13 atoms per cubic meter cm to 5E14 atoms per cubic centimeter.