CN103681507A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN103681507A CN103681507A CN201210356107.0A CN201210356107A CN103681507A CN 103681507 A CN103681507 A CN 103681507A CN 201210356107 A CN201210356107 A CN 201210356107A CN 103681507 A CN103681507 A CN 103681507A
- Authority
- CN
- China
- Prior art keywords
- fin
- metal material
- work function
- material layer
- function metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title abstract description 3
- 239000007769 metal material Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 101
- 239000002019 doping agent Substances 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 2
- 238000002360 preparation method Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 238000002513 implantation Methods 0.000 description 9
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 4
- 238000009415 formwork Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
- H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明涉及一种半导体器件及其制备方法，所述方法包括提供半导体衬底，所述衬底上至少包含第一鳍片和第二鳍片；在所述衬底上沉积高功函金属材料层，以覆盖所述第一鳍片和所述第二鳍片；在所述第二鳍片及两侧的所述高功函金属材料层上形成低功函金属材料层，以在所述第二鳍片上形成功函金属材料叠层；沉积栅极图案掩膜层，蚀刻所述低功函金属材料层和所述高功函金属材料层，以在所述第一鳍片和所述第二鳍片上形成栅极结构。本发明所述方法制备得到的器件中阈值电压（Vth）可控的，而且所述方法制备得到的双金属栅极之间没有节点，为独立的双栅极FinFET，使半导体器件的阈值电压（Vth）更加稳定，增强了SRAM单元的性能。
The invention relates to a semiconductor device and a manufacturing method thereof. The method includes providing a semiconductor substrate, the substrate at least including a first fin and a second fin; depositing a high work function metal material on the substrate layer to cover the first fin and the second fin; a low work function metal material layer is formed on the second fin and the high work function metal material layer on both sides to cover the A work function metal material stack is formed on the second fin; a gate pattern mask layer is deposited, and the low work function metal material layer and the high work function metal material layer are etched to form the first fin and the high work function metal material layer. A gate structure is formed on the second fin. The threshold voltage (Vth) of the device prepared by the method of the present invention is controllable, and there is no node between the double metal gates prepared by the method, which is an independent double gate FinFET, so that the threshold voltage of the semiconductor device ( Vth) is more stable and enhances the performance of the SRAM cell.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of semiconductor device and preparation method thereof.
Background technology
To be mainly size by constantly dwindling integrated circuit (IC)-components realize with the speed that improves it in the raising of performance of integrated circuits.At present, because semi-conductor industry in pursuing high device density, high-performance and low cost has advanced to nanometer technology process node, particularly when dimensions of semiconductor devices drops to 22nm or when following, from manufacturing and the challenge of design aspect has caused three dimensional design as the development of FinFET (FinFET).
With respect to existing planar transistor, described FinFET device is controlled and reduced the aspects such as shallow channel effect at raceway groove has more superior performance; Planar gate is arranged at described raceway groove top, and in gate loop described in FinFET around described fin setting, therefore can control static from three faces, the performance aspect electrostatic control is also more outstanding.In FinFET, the length of grid obtains by measuring the parallel length of fin, the width of described grid is twice and the wide sum of fin of described fin height, the limitation in height of fin the electric current of device and the electric capacity of grid, the width of fin can affect the threshold voltage of device and short channel is controlled.
Threshold voltage in currently available technology (Vth) controlled, independently bigrid FinFET's is introduced in semiconductor device preparation, be used for the stability of the sram cell performance that strengthens, in order further to reduce threshold voltage (Vth), to strengthen the current driving ability when compared with low supply voltage, can select the FinFET of double-metal grid to realize described effect, Metal Phase counterdiffusion technology (Metal inter-diffusion technology) becomes the key of preparing double-metal grid FinFET.
The cylindrical transistor without node (junction-less) has been proposed at present, preparation technology has been simplified in described transistorized preparation greatly, in this process, can omit the step that the ring of light/expansion and source/leakage is injected, having avoided forming described gate stack carries out activating the step of annealing after Implantation, thereby reduce, produce heat budget, more possibility is provided simultaneously in the selection of gate metal and gate dielectric layer material.
The method of preparing at present the FinFET of double-metal grid is in Semiconductor substrate, to form fin, then deposit metallic material layer and hard mask layer on described substrate, then patterning, to form, be positioned at all around gate on described fin, two grid structures in double-metal grid interconnect, have node simultaneously, have identical threshold voltage (Vth), the stability of threshold voltage in the device that makes to prepare (Vth) is not ideal enough.
Therefore, although there is the transistor without node (junction-less) in prior art, but also do not have method preparation not contain the FinFET of the double-metal grid of node, need prior art to do further improvement simultaneously, to make the threshold voltage (Vth) of semiconductor device more stable, make two grids in described double-metal grid there is different threshold voltage (Vth) simultaneously, and mutually more independent.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The preparation method who the invention provides a kind of semiconductor device, comprising:
Semiconductor substrate is provided, on described substrate, at least comprises the first fin and the second fin;
On described substrate, deposit high work function metal material layer, to cover described the first fin and described the second fin;
On the described high work function metal material layer of described the second fin and both sides, form low work function metal material layer, to form work function metal material laminate on described the second fin;
Deposition gate pattern mask layer, low work function metal material layer and described high work function metal material layer described in etching, to form grid structure on described the first fin and described the second fin.
As preferably, form after described grid structure, carry out annealing steps, so that the low work function metal in the described low work function metal material layer on described the second fin diffuses in described high work function metal material layer.
As preferably, form after described grid structure, also comprise the step of deposition interlayer dielectric layer planarization.
As preferably, when described interlayer dielectric layer is removed in described planarization, remove remaining described high work function metal material layer and described low work function metal material layer on described fin, to form independently bigrid without junction structure.
As preferably, low work function metal material layer and described high work function metal material layer described in dry etching, to form grid structure.
As preferably, described dry etching is selected Cl
2and O
2combination, or CHF
3and O
2combination.
As preferably, described method is further comprising the steps of:
Before the high work function metal material layer of deposition, on described the first fin region and described the second fin region, carry out dissimilar doping.
As preferably, described the first fin both sides doping P type dopant, to form PMOS.
As preferably, described the second fin both sides doped N-type dopant, to form NMOS.
As preferably, described high work function metal material layer is Mo.
As preferably, described low work function metal material layer is Ta.
As preferably, on described substrate, deposit after high work function metal material layer, in described the first fin both sides, carry out same type or dissimilar Implantation, to form identical or different threshold voltages.
As preferably, on described the second fin, deposit after low work function metal material layer, in described the second fin both sides, carry out same type or dissimilar Implantation, to form identical or different threshold voltages.
The present invention also provides a kind of and has had independent double-metal grid without the semiconductor device of junction structure, and it comprises:
Semiconductor substrate;
Be positioned at the first fin and the second fin in described Semiconductor substrate;
Uniform doped with dissimilar dopant in described the first fin both sides and described the second fin both sides substrate;
Be positioned at the high work function metal material layer of described the first fin both sides, to form independently bigrid in described the first fin region without junction structure,
Be positioned at high work function metal material layer and the low work function metal material layer of described the second fin both sides, to form independently bigrid in described the second fin region without junction structure.
As preferably, described high work function metal material layer is Mo.
As preferably, described low work function metal material layer is Ta.
As preferably, the dopant of described the second fin both sides is N-type dopant, to form NMOS.
As preferably, the dopant of described the second fin both sides is P type dopant, to form PMOS.
As preferably, between the high work function metal material layer on described the first fin and the high work function metal material layer on described the second fin, mutually isolate.
(Vth) is controlled for threshold voltage in the device that the method for the invention prepares, and there is no node between the double-metal grid for preparing of described method, for bigrid FinFET independently, make the threshold voltage (Vth) of semiconductor device more stable, strengthened the performance of sram cell.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1-4 for forming the preparation flow schematic diagram of metal material layer on described fin in the present invention;
Fig. 5 is the vertical view in PMOS region in Fig. 4;
Fig. 6 is the vertical view in territory, nmos area in Fig. 4;
Fig. 7 is for containing the process chart of the semiconductor device of highly controlled fin in preparation the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, by propose detailed description in following description, so that the preparation method of semiconductor device of the present invention to be described.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should give attention, the term that used is here only in order to describe specific embodiment, but not intention restriction is according to exemplary embodiment of the present invention.As used herein, unless context explicitly points out in addition, otherwise singulative is also intended to comprise plural form.In addition, it is to be further understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
Now, describe in more detail according to exemplary embodiment of the present invention with reference to the accompanying drawings.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.To should be understood that, to provide these embodiment of the present inventionly to disclose thoroughly and complete in order making, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and used the identical Reference numeral to represent identical element, thereby will omit description of them.
Preparation method below in conjunction with Fig. 1-6 pair semiconductor device containing highly controlled fin of the present invention is described further:
As shown in Figure 1, provide Semiconductor substrate, on described substrate, at least comprise the first fin and the second fin;
Particularly, described Semiconductor substrate 101 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In Semiconductor substrate, can be defined active area.On this active area, can also include other active device, in order to simplify accompanying drawing, shown in do not indicate in figure.
Described Semiconductor substrate is divided into territory, nmos area and PMOS region in the present invention.
Then in described Semiconductor substrate, form fin, at least in described PMOS region and territory, nmos area, form respectively the first fin 20 and the second fin 10.The formation method of described the first fin and the second fin can be selected ability common method, for example in the present invention can be on described substrate epitaxial growth semiconductor material layer, then on described semiconductor material layer, form fin pattern mask layer, the photoresist mask layer that for example comprises fin CD, pattern, then take described fin pattern mask layer as semiconductor material layer described in mask etch, to described substrate, form the first fin 20 and the second fin 10, then remove described mask layer.
With reference to Fig. 2, on described substrate, deposit high work function metal material layer, to cover described the first fin and described the second fin;
Particularly, after forming described the first fin 20 and the second fin 10, on described substrate, carry out uniformly ion doping, for example on substrate, N-type doping is carried out in territory, nmos area, to form N-type transistor, carries out the doping of P type in PMOS region, to form P transistor npn npn, described N-type dopant comprises P, As, Sb, and described P type dopant comprises B and BF and In, and described doping method can be following any method:
First method is Implantation (Nitrogen implantation), and the ion energy of described injection is 1kev-10kev, and the ion dose of injection is 5 * 10
14-5 * 10
16atom/cm
2.Be preferably in the present invention below 400 ℃, and can comparatively independently control Impurity Distribution (ion energy) and impurity concentration (ion current density and injection length) by described method, the method more easily obtains the doping of high concentration, and be anisotropy doping, independently controlling depth and concentration.
The present invention also can select plasma doping (plasma doping), when adopting the method, generally selects higher temperature, generally selects in the present invention 900-1200 ℃, and described method is isotropism.
Then on described substrate, deposit high work function metal material layer, preferred Mo in the present invention, described deposition process can be selected a kind of in sputter (Sputtering), physical vapor deposition (PVD) method, and its thickness can be 40-100nm.
Then in the both sides of fin described in described PMOS region, carry out Implantation, wherein said injection ionic type can be identical or different, to form identical or different threshold voltages in described fin both sides, preferably carry out in the present invention dissimilar Implantation, form different threshold voltages, the ion of wherein said injection can select this area to commonly use kind, at this, will not enumerate.
Then on described the second fin and both sides, deposit low work function metal material layer, to cover described the second fin, and form work function metal material laminate on described the second fin;
Particularly, at the low work function metal material layer of the upper deposition of described high work function metal material layer (Mo material layer), preferred Ta in the present invention, then on described the second fin region, form mask layer, etching is removed and is positioned at the described low work function metal material layer on the first fin region, then remove mask layer, only on described the second fin region, form low work function metal material layer, in conjunction with the Mo material layer that is positioned at below, form work function metal material laminate, wherein said Ta selects physical vapor deposition (PVD) method to form, and its thickness can be 20-50nm.In this step, the high work function metal material layer on the high work function metal material layer on described the first fin region and described the second fin region is formed to isolation, to form separately independently grid structure simultaneously.
Then in the both sides of the second fin described in territory, described nmos area, carry out Implantation, wherein said injection ionic type can be identical or different, to form identical or different threshold voltages in described fin both sides, preferably carry out in the present invention dissimilar Implantation, form different threshold voltages, the ion of wherein said injection can select this area to commonly use kind, at this, will not enumerate.
With reference to Fig. 4, on described the first fin and described the second fin, form grid structure;
Particularly, can first on described metal material layer, form grid structure patterned mask layer, the described grid structure patterned mask layer of take is metal material layer described in mask etch, comprises Mo and Ta material layer, forms grid structure.
As preferably, described in etching, selecting Cl during metal material layer
2and O
2combination, or CHF
3and O
2combination, wherein gas flow is 10-400sccm, described etching pressure is 20-300mTorr, etching period is 5-120s, is preferably 5-60s, more preferably 5-30s.
After forming described grid structure, also comprise annealing steps; so that the described low work function metal material layer on described the second fin diffuses in described high work function metal material layer; wherein said annealing steps is generally that described substrate is placed under the protection of high vacuum or high-purity gas; being heated to certain temperature heat-treats; at high-purity gas of the present invention, be preferably nitrogen or inert gas; the temperature of described thermal anneal step is 900-1200 ℃, and the described thermal anneal step time is 1-200s.
As further preferred, can select rapid thermal annealing in the present invention, particularly, can select a kind of in following several mode: pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and incoherent wideband light source (as halogen lamp, arc lamp, graphite heating) short annealing etc.Those skilled in the art can select as required, are also not limited to examples cited.
After executing annealing steps, can also further comprise the step that deposits interlayer dielectric layer, described interlayer dielectric layer can be used such as SiO2, fluorocarbon (CF), carbon doped silicon oxide (SiOC) or carbonitride of silicium (SiCN) etc. in an embodiment of the present invention.Or, also can use film having formed SiCN film etc. on fluorocarbon (CF).It is main component that fluorocarbon be take fluorine (F) and carbon (C).Fluorocarbon also can be used the material with noncrystal (amorphism) structure.Interlayer dielectric layer can also be used such as Porous structures such as carbon doped silicon oxide (SiOC).
Then carry out planarisation step, in this step, remove remaining described high work function metal material layer and described low work function metal material layer on described the first fin and the second fin, to form independently bigrid without junction structure (Dual gate junctionless) simultaneously.
Fig. 5 be the bigrid that forms in described PMOS without the vertical view of junction structure, in the both sides of described the first fin, formed and there is certain thickness Mo material layer.
Fig. 6 be the bigrid that forms in described NMOS without the vertical view of junction structure, in the both sides of described the first fin, formed and there is certain thickness work function metal material laminate.
The present invention also provides a kind of and has had independent double-metal grid without the semiconductor device of junction structure, and it comprises:
Semiconductor substrate;
Be positioned at the first fin and the second fin in described Semiconductor substrate;
Uniform doped with dissimilar dopant in described the first fin both sides and described the second fin both sides substrate;
Be positioned at the high work function metal material layer of described the first fin both sides, to form independently bigrid in described the first fin region without junction structure,
Be positioned at high work function metal material layer and the low work function metal material layer of described the second fin both sides, to form independently bigrid in described the second fin region without junction structure.
(Vth) is controlled for threshold voltage in the device that the method for the invention prepares, and there is no node (junction) between the double-metal grid for preparing of described method, for bigrid FinFET independently, make the threshold voltage (Vth) of semiconductor device more stable, strengthened the performance of sram cell.
Fig. 7 is the process chart that preparation the present invention prepares semiconductor device, comprises the following steps:
Step 201 provides Semiconductor substrate, at least comprises the first fin and the second fin on described substrate;
Step 202 deposits high work function metal material layer on described substrate, to cover described the first fin and described the second fin;
Step 203 forms low work function metal material layer on the described high work function metal material layer of described the second fin and both sides, to form work function metal material laminate on described the second fin;
Step 204 deposition gate pattern mask layer, low work function metal material layer and described high work function metal material layer described in etching, to form grid structure on described the first fin and described the second fin.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (19)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210356107.0A CN103681507B (en) | 2012-09-20 | 2012-09-20 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210356107.0A CN103681507B (en) | 2012-09-20 | 2012-09-20 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103681507A true CN103681507A (en) | 2014-03-26 |
| CN103681507B CN103681507B (en) | 2017-02-01 |
Family
ID=50318644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210356107.0A Active CN103681507B (en) | 2012-09-20 | 2012-09-20 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103681507B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979198A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin type field effect transistor |
| CN106409767A (en) * | 2015-07-31 | 2017-02-15 | 台湾积体电路制造股份有限公司 | Multi-threshold voltage field effect transistor and manufacturing method thereof |
| CN107492496A (en) * | 2016-06-12 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1476093A (en) * | 2002-08-15 | 2004-02-18 | 联华电子股份有限公司 | Dual work function CMOS transistor and method of fabricating the same |
| US20090200616A1 (en) * | 2008-02-13 | 2009-08-13 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102222693A (en) * | 2010-04-15 | 2011-10-19 | 中国科学院微电子研究所 | FinFET device and manufacturing method thereof |
| CN102237399A (en) * | 2010-04-22 | 2011-11-09 | 联华电子股份有限公司 | Semiconductor element with metal gate and manufacturing method thereof |
-
2012
- 2012-09-20 CN CN201210356107.0A patent/CN103681507B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1476093A (en) * | 2002-08-15 | 2004-02-18 | 联华电子股份有限公司 | Dual work function CMOS transistor and method of fabricating the same |
| US20090200616A1 (en) * | 2008-02-13 | 2009-08-13 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102222693A (en) * | 2010-04-15 | 2011-10-19 | 中国科学院微电子研究所 | FinFET device and manufacturing method thereof |
| CN102237399A (en) * | 2010-04-22 | 2011-11-09 | 联华电子股份有限公司 | Semiconductor element with metal gate and manufacturing method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979198A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin type field effect transistor |
| CN104979198B (en) * | 2014-04-02 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin formula field effect transistor |
| CN106409767A (en) * | 2015-07-31 | 2017-02-15 | 台湾积体电路制造股份有限公司 | Multi-threshold voltage field effect transistor and manufacturing method thereof |
| CN106409767B (en) * | 2015-07-31 | 2020-02-21 | 台湾积体电路制造股份有限公司 | Multi-threshold voltage field effect transistor and method of making the same |
| CN107492496A (en) * | 2016-06-12 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
| CN107492496B (en) * | 2016-06-12 | 2019-12-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103681507B (en) | 2017-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9450078B1 (en) | Forming punch-through stopper regions in finFET devices | |
| TWI493630B (en) | Method and structure for forming fin-type field effect transistors having various dopings on the same wafer | |
| CN104576331B (en) | Doping Method of Fin Field Effect Transistor | |
| US8853008B1 (en) | Counter-doped low-power FinFET | |
| CN104752214B (en) | The forming method of fin field effect pipe | |
| US20160197085A1 (en) | Semiconductor structure and fabrication method thereof, and static random access memory cell | |
| TWI503991B (en) | P-type field effect transistor structure and forming method thereof | |
| US9666682B2 (en) | Reverse conduction insulated gate bipolar transistor (IGBT) manufacturing method | |
| CN104916539B (en) | A method of making semiconductor devices | |
| CN104167391A (en) | Method for manufacturing CMOS structure | |
| CN103187297A (en) | Manufacturing method of fin type field effect transistor | |
| CN106601678B (en) | A kind of semiconductor device and its preparation method, electronic device | |
| TWI523085B (en) | Method of forming a semiconductor device embedding a semiconductor material as a source/drain region using a reduced number of spacers | |
| CN103681507A (en) | Semiconductor device and manufacturing method thereof | |
| CN104752213A (en) | Semiconductor structure forming method | |
| CN103515205B (en) | A kind of FinFET channel doping process | |
| CN103811420A (en) | Preparation method of semiconductor device | |
| CN109285778B (en) | Semiconductor device and method of forming the same | |
| TW201732937A (en) | Semiconductor component and manufacturing method thereof | |
| TWI287856B (en) | Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method | |
| CN104347508A (en) | Semiconductor structure and formation method thereof | |
| CN104347413B (en) | A kind of method making FinFET semiconductor device | |
| CN104576728B (en) | A kind of semiconductor devices and its manufacturing method | |
| EP3291291B1 (en) | Semiconductor device and fabrication method thereof | |
| TWI504557B (en) | Method of adjusting the structure of the nanowire |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |