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CN1126167C - 半导体芯片贴装板及贴片方法 - Google Patents

半导体芯片贴装板及贴片方法 Download PDF

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CN1126167C
CN1126167C CN97117455A CN97117455A CN1126167C CN 1126167 C CN1126167 C CN 1126167C CN 97117455 A CN97117455 A CN 97117455A CN 97117455 A CN97117455 A CN 97117455A CN 1126167 C CN1126167 C CN 1126167C
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semiconductor chip
mounting board
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chip mounting
mounts
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CN1181629A (zh
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大谷博之
八木能彦
山本宪一
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Panasonic Holdings Corp
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Abstract

半导体芯片贴装板(104)上形成与半导体芯片(1)上的不工作电极(105)对应的增强区(103)。增强区和不工作电极相互粘接，由此提高半导体芯片与半导体芯片贴装板之间的粘接强度。

Description

半导体芯片贴装板及贴片方法
技术领域
本发明涉及半导体芯片贴装板，其中，用倒装贴片法使半导体芯片连接到半导体芯片贴装面，形成在与半导体芯片贴装面相对的电路板贴装面上的电极电连接到电路板上的电极，并涉及半导体芯片贴装到半导体芯片贴装板上的方法。
背景技术
用金属丝的引线连接已广泛用于如半导体芯片等与电路板上的电极引出端部件的电子微电路元件的电连接。但是，近年来，趋于有更高集成度的芯片，引出端数量增加以及连接节距变窄。同时，个人用计算机、便携式遥控终端等需要有效地利用半导体芯片上的安装面积。为此，近来采用倒装式贴片法，因此，在半导体芯片上形成凸点(突出端)并用连接材料直接与电路板上的电极连接，此外，具有低价性能的树脂电路板需要用瞬时连接安装技术。
以下将说明按常规倒装式贴片法贴装有半导体芯片的半导体芯片贴装板及半导体芯片贴装到半导体芯片贴装板上的方法。
图6是其上贴有半导体芯片1的常规半导体芯片贴装板4的平面图。图7是沿图6中III-III线的截面图；图8是沿图6中线IV-IV的截面图。图6中数字20是贯穿半导体芯片贴装板4的半导体芯片贴装面4a和电路板贴装面4b电连接半导体芯片与电路板用的通孔。
半导体芯片1的电路形成面1a上经半导体芯片1的周边部分中间隔120μm形成电极端B。对具有凸点6的半导体芯片的总功能而言必须要有电极端13，每个凸点6有大直径部分6a和小直径部分6b两个突台。凸点6用金构成75μm的较大直径，其高度为45μm。
另一方面，用热膨胀系数为13ppm，玻璃转换点为115-120℃的玻璃环氧树脂构成常规半导体芯片贴装板4。在半导体芯片贴装板4的芯片贴装面4a相当于半导体芯片1上形成的电极端13的位置，每120μm形成一个条形连接区2。连接区的宽度W2是50μm。如图8所示，连接区2从其接触点6c朝半导体芯片1的中心部分延伸到凸点6的长度L2。L2通常为35μm。而且，如图9所示，在贴装板4的半导体芯片贴装面4a与半导体芯片1的端面1b隔开距离r2处形成焊料光刻胶9。r2通常为200μm。
将说明把半导体芯片1贴装到常规半导体芯片贴装板4的方法。
在第1处，在半导体芯片1的电极端13形成满足正常工作功能所需的上述凸点6，即，经贴装板4对电路板输入/输出信号所需的引出端。把以银为主要成份的导电树脂浆料的粘接材料7预先加到凸点6上，其厚度约为10μm。
而且，按以后将会说明的表面贴装技术(SMT)把半导体芯片贴装板4贴装到电路板上。
之后，图6中，加有粘接材料7的有凸点6的半导体芯片用粘接材料7经凸点6电连接到贴装板4的半导体芯片贴装面4a处形成的粘接区2。粘接材料7在120℃干燥两小时固化后，由此，在半导体芯片1与半导体芯片贴装面4a之间注入密封树脂8，并在120℃加热2小时固化。图10展示出其上贴装有多个半导体芯片1的半导体芯片贴装板4。用配料器从半导体芯片1的一边按箭头所指方向加密封树脂8。根据半导体芯片1的形状或至周边区的距离选择适于注入密封树脂8的地方。
常规半导体芯片贴装板4的结构和贴装方法有以下缺点。
由于半导体芯片1的凸点6与贴装板4上的粘接区2之间的粘接强度是每个凸点约3克那么小，因此，具有少量电极端13的半导体芯片1与贴装板4的粘接强度差。而且，电子粘接区2的面积小，因此，粘接材料7不能构成足够的凸起，而是在半导体芯片贴装面4a上散开，其宽度Wf2大于粘接区2的宽度W2，如图7所示，长度Lf2大于粘接区2的长度L2，如图8所示。这会造成短路和绝缘电阻变坏。所述宽度Wf2是100μm，长度Lf2是50μm。
而且，由于常规贴装板4的热膨胀系数大于作为半导体芯片1的硅材料的热膨胀系数，当半导体芯片1贴装到贴装板4上密封树脂8受热并固化之后，由于贴装板4与半导体芯片1的热膨胀系数不同，而产生应力。该应力对凸点6与粘接区2之间粘接部分中如上述的粘接强度小的地方作用，因而，使粘接部分中的电阻增大，或使粘接部分断开。
如上所述，用主要成分为玻璃环氧树脂的材料制造半导体芯片贴装板4。因此，当半导体芯片贴装板4的温度上升到不低于玻璃转化点(Tg)时，在玻璃转化点的贴装板4的热膨胀系数α2比其玻璃转化点前的热膨胀系数α1增大了5至7倍，如图11所清楚示出的，因此，贴装板4的损坏量变大。
贴装半导体芯片1的半导体芯片贴装板4在120℃经过2小时干燥/固化处理，以使在凸点6构成的上述粘接材料7干燥和固化。此时，粘接材料7固化后，温度从120℃下降时，半导体芯片贴装板4会翘曲成图12所示的半导体芯片贴装板4’。
而且，经上述干燥/固化处理之后，注入贴装板4与半导体芯片1之间的密封树脂8在120℃经2小时固化处理。密封树脂8固化后，从120℃降温时，半导体芯片贴装板4翘曲成图13所示半导体芯片贴装板4”。
在上述粘接材料7和密封树脂8固化处理之前，用SMT把贴装板4贴装到电路板上时，贴装板4的温度在该温度升到230℃的最高温度。即，在SMT贴装时贴装板4也会随之翘曲。
由于常规半导体芯片贴装板4的玻璃转化点低于粘接材料7或密封树脂8的干燥/固化温度，因此，扩大了因热膨胀系数不同造成的贴装板4的上述翘曲。因此，粘接部分的电阻值会增大并会使粘接部分断开。
常规半导体芯片贴装板4中，在半导体芯片1的端面16附近设置焊料光胶9。因此，密封树脂8不会形成足够的凸起。此外，由于密封树脂8在焊料光刻胶9上的粘接强度小，因此，在环境试验中，在其界面处焊料光刻胶会与密封树脂8分开，从产品质量考虑，它是重要的关键问题。
检查密封树脂8的密封性时，由于在常规贴装方法中很难找到构成密封树脂注入开口的位置，因此，要用大量的时间用自动检查装置来识别注入开口并检查密封树脂8形成的凸起，因而使生产率下降。
如果适于SMT的无引线半导体芯片和常规的有引线元件混合排列在贴装板上，由于首先执行SMT，在对其进行热处理时半导体芯片贴装板4翘曲。因此，在粘接部分的粘接电阻增大。同时，由于粘有灰尘和残留的溶剂，会使粘接部分的可靠性降低，因此，大大影响产品质量。为除去上述的灰尘，就需要有附加的工艺，从而造成生产率下降和成本增大。
发明内容
为克服上述缺陷，本发明的目的是，提供能以高生产率高质量贴装半导体芯片的半导体芯片贴装板，和把半导体芯片贴装到半导体芯片贴装板上的方法。
为实现这些目的和其它目的，按本发明第1方案，提供了一种半导体芯片贴装板，包括半导体芯片贴装面，该半导体芯片贴装面上构成有粘接区，并按倒装式芯片贴装法与半导体芯片的电路形成面上构成的电极电连接；和对着半导体芯片贴装面、并与电路板电连接的电路板贴装面，其中，在半导体芯片贴装面还设置增强区，通过凸点用粘接材料把增强区连接到电路形成面上形成的不工作电极，增强区在功能上与半导体芯片无关，只是增大半导体芯片与半导体芯片贴装板之间的连接强度；其特征在于，所述半导体芯片贴装板有一个超过粘接材料的干燥和固化温度的玻璃转化点。
优选地在上述半导体芯片贴装板中，电极和半导体芯片的不工作电极设置有凸点，用粘接材料经凸点使电极和粘接区，不工作电极和增强区相互电连接。
优选地在上述半导体芯片贴装板中，半导体芯片贴装面上形成的粘接区和增强区是条形的径向延伸到贴装的半导体芯片，在长度上防止粘接材料扩散到半导体芯片贴装表面的宽度之外，在方向上从接触点到凸点到半导体芯片的中心部分。
优选地在上述半导体芯片贴装板中，贴装板包含热膨胀系数不小于硅的热膨胀系数的材料。
优选地在上述半导体芯片贴装板中，半导体芯片贴装到半导体芯片贴装板上之后，半导体芯片与半导体芯片贴装板之间注入密封树脂，贴装板的玻璃转化点超过密封树脂的固化温度。
优选地在上述半导体芯片贴装板中，用与半导体芯片的电路形成面上的电极相同的材料和相同的形成方法，构成不工作电极。
根据本发明的另一个方面，还提供了一种把半导体芯片贴装到半导体芯片贴装板的方法，该半导体芯片贴装面上构成有粘接区，并按倒装式芯片贴装法与半导体芯片的电路形成面上构成的电极电连接；和对着半导体芯片贴装面、并与电路板电连接的电路板贴装面，该方法包括以下步骤：
把半导体芯片的电路形成面面对半导体芯片贴装面；通过凸点用粘接材料，把增强区连接到电路形成面上形成的不工作电极；
其特征在于，所述半导体芯片贴装板有一个超过粘接材料的干燥和固化温度的玻璃转化点。
优选地，在上述的半导体芯片贴装方法中，包括：在半导体芯片贴装到半导体芯片贴装板上之后，在半导体芯片贴装面上的部分处形成焊料光刻胶，从半导体芯片侧面，按对着半导体芯片的方向，它从凸起位置到半导体芯片贴装面隔开的距离不小于半导体芯片的厚度和半导体芯片贴装面与电路构成面之间的间隙之和。
优选地，在上述的半导体芯片贴装方法中，当半导体芯片与半导体芯片贴装板之间加密封树脂时，在半导体芯片贴装面上构成能识别密封树脂开始注入位置的注入开始标记。
优选地，在上述的半导体芯片贴装方法中，半导体芯片贴装板包含其热膨胀系数不小于硅的热膨胀系数的材料，它的玻璃转化点超过粘接材料的干燥和固化温度，由此，在半导体芯片贴装到半导体芯片贴装板之后，半导体芯片与半导体芯片贴装板之间加密封树脂，半导体芯片贴装板的玻璃转化点超过密封树脂的干燥和固化温度。
优选地，在上述的半导体芯片贴装方法中，加了密封树脂后，按SMT用焊料把半导体芯片贴装板贴装到电路板上。
根据以下参见附图结合优选实施例对本发明的说明，本发明的这些特征和其它特征将是显而易见的。
附图说明
图1是按本发明一个实施例的其上贴有半导体芯片的半导体芯片贴装板的平面图；
图2是沿图1中线I-I的剖视图；
图3是沿图1中线II-II的剖视图；
图4是按本发明实施例的指示半导体芯片贴装板注入密封树脂的位置的示意图；
图5是按本发明实施例的，指示半导体芯片贴装板中密封树脂的注入起始位置和注入方向的示意图；
图6是其上贴有半导体芯片的常规半导体芯片贴装板的平面图；
图7是沿图6中线III-III的剖视图；
图8是沿图6中线IV-IV的剖视图；
图9是加有密封树脂的常规半导体芯片贴装板的示意图；
图10是常规半导体芯片贴装板中密封树脂注入方向的示意图；
图11是温度与半导体芯片贴装板的热膨胀/变形量之间的关系曲线；
图12是粘接材料固化处理中半导体芯片贴装板的变形示意图；
图13是密封树脂固化处理中半导体芯片贴装板的变形示意图。
具体实施方式
说明本发明方法之前，应注意，在全部附图中相同的参考数字指示相同的零部件。
以下将参见附图说明按本发明一个实施例的半导体芯片贴装板和把半导体芯片贴装到半导体芯片贴装板的方法。附图中相同的参考数字表示相同的零部件或功能相同的零部件。首先说明半导体芯片贴装板。
图1相当于上述的图6，图2和3分别是沿图1中线I-I和II-II的剖视图。
半导体芯片1的电路形成面1a上设置不工作的电极105，例如，是在贴装半导体芯片之后，通常用于测试半导体芯片单体并且在功能上与半导体芯片1无关的测试电极。如果没有不工作电极105，或具有的不工作电极105的数量不够，当构成半导体芯片1功能上必需的电极13时，可用与电极13相同的材料构成不工作电极105。
在贴装板104的半导体芯片贴装面4a构成相当于不工作电极105的增强区103。增强区103不与安装半导体芯片贴装板104的电路板上的布线电连接。如图1所示，增强区103构成为条形，在该实施例中，条的宽度W1是50μm。电极端13与半导体芯片1的不工作电极105之间的每个间隔为120μm，同上述的宽度相同。
这样构成的半导体芯片贴装板104和半导体芯片1中，不工作电极105和增强区103用粘接材料7经凸点6按与以下情况相同的方式粘接在一起，即，在半导体芯片1的电路形成面1a上形成的、并是半导体芯片1功能上必需的电极端13用粘接材料7经带粘接区102的凸点6粘接，粘接区102在贴装板104的半导体芯片贴装面4a上构成，相应于电极端13，并与电路板上的布线电连接。用的凸点6与参见图7所述的凸点相同。
如上所述，半导体芯片1和半导体芯片贴装板104的粘接点数量增加，使之间的粘接强度提高。甚至当半导体芯片贴装板104的热膨胀系数大于用作半导体芯片1的材料硅的热膨胀系数时，例如加到电极端13和粘接区102的粘接部分的粘接材料7在120℃被加热2小时而固定时，所产生的热应力会减小。因此，能高质量地把半导体芯片1贴装到实施例的半导体芯片贴装板104，获得高生产率。能用常用的树脂材料构成半导体芯片贴装板104，能降低生产成本。
如图3所示，在电路板104的半导体芯片贴装面40形成的每个粘接区102和增强区103从接触点6C朝半导体芯片1的中心部分107延长到凸点6的长度比现有技术长。更具体地说，如参见图8所述，在现有技术中，粘接区2从粘接区2与凸点6之间的接触点6c延伸到半导体芯片1的中心部分的长度L2是35μm。另一方面，如图3所示，按实施例，从接触点6c至粘接区102和增强区103的端部的距离中的每一个均约为85μm。
由于从接触点6c至粘接区102和增强区103的端部的距离做得比现有技术大，粘接材料7能构成按粘接区102和增强区103之每一个的长度方向延伸的凸起，如图3中Lf1所示。因此，即使粘接区102和增强区103的宽度W1与现有技术的宽度大小相同，粘接区7也能防止形成的凸起在贴装面4a上散开而超出粘接区102和增强区103之每一个的宽度W1。因此，粘接材料7的宽度Wf1不会大于粘接区102和增强区103之每一个的宽度W1。上述的Lf1例如是约50μm。
甚至在经过规定的窄距离在半导体芯片1上构成电极端13时，当获得足够的凸起时，也能防止半导体芯片贴装面4a上相邻粘接区102之间出现短路或绝缘电阻变坏。因此，能高质量的在半导体芯片贴装板104上贴装半导体芯片1，由此获得高生产率。
以下将说明为用更高质量贴装半导体芯片1而对半导体芯片贴装板104所用材料的改进。
如参见图11-13所述、常规半导体芯片贴装板4的玻璃转化点是115-120℃，即，低于粘接材料7或密封树脂8的固化温度120℃，上述问题是现有技术中存在的实质问题。
另一方面，实施例的半导体芯片贴装板104用玻璃转化点为170℃的玻璃环氧树脂。热膨胀系数与现有技术相同，为13ppm。
用上述半导体芯片贴装板104时，由于贴装板104的玻璃转化点高于粘接材料7和密封树脂8的固化温度，粘接材料7和密封树脂8在固化时的热膨胀系数之差会减小，因此，能精确测到的贴装板104的翘曲是100μm/100mm。作用于凸点与粘接区之间的粘接部分的应力会减小。即，粘接可靠性提高。
按实施例，用SMT把半导体芯片板104贴装到电路板之前，半导体芯片1贴装并密封到半导体芯片贴装板104。用该方法、由于能防止半导体芯片贴装到如现有技术的热翘曲的半导体芯片贴装板上，因此，能提高粘接的零部件质量。而且，因在SMT贴装之前，贴装并密封半导体芯片1，因此不会把灰尘粘到半导体芯片1上或有残留的溶剂。能相应地提高粘接件的可靠性，而且，不需进行清洁处理。能提高生产率，降低生产成本。
按实施例的半导体芯片贴装板104中，设计出贴装板104的半导体芯片贴装面4a上设置焊料光刻胶的位置。
具体地说，如图4所示，半导体芯片1粘接到半导体芯片贴装面4a，在半导体芯片1与半导体芯片贴装板104之间加密封树脂8。在安装面104a上的与半导体芯片1的端面1b相距r1的部分109，在贴装面4a的凸起位置108，按对着半导体芯片的方向，构成焊料光刻胶9。距离r1不小于贴装面4a与半导体芯片1之间的间隙d2与半导体芯片1的厚度d1之和。
为了用配料器注入密封树脂8，在半导体芯片贴装面4a形成注入开始标记，以指示注入密封树脂8开始的位置。图5中展示出有在一个半导体芯片贴装板上贴装多个半导体芯片1的多芯片组件(MCM)。从注入起始标记11开始沿箭头12指示的方向给每张半导体芯片1注入密封树脂8。
如上所述，由于在合适位置设置了焊料光刻胶9，从半导体芯片1的上表面构成密封树脂8的凸起，而不会叠置在焊料光刻胶9上。而且，形成足够的密封树脂8的凸起，由此，提高质量可靠性。
注入起始标记11能清楚地识别注入起始位置和密封树脂8的注入方向。因此，检查密封时，能用自动检查装置在短时间里检查凸起的形成，因此，提高了生产率。
正如以上完全说明的，按本发明第1方案的半导体芯片贴装板，和按本发明第8方案的半导体芯片贴装方法，不仅贴装板上的粘接区与半导体芯片上的电极粘接，而且，要与半导体芯片上的不工作电极连接的贴装板上还设置有增强区并连接在其中。因此，半导体芯片与半导体芯片贴装板之间的连接点数量增大，由此，其间的粘接强度能增大。由半导体芯片与半导体芯片贴装板之间的热膨胀系数之差造成的应力能减小，并能减小对电极与粘接区之间粘接件的影响。因此，能高质量地把半导体芯片贴装到半导体芯片贴装板上，获得高生产率。
日本特许公开平8-190505，申请日为1996年7月19日，包括说明书，权利要求书，附图和摘要的全部公开，在此作为一个整体引作参考。
尽管参见本发明的附图结合本发明的优选实施例充分说明了本发明，但本领域的技术人员会注意到，本发明还有各种变化和改进。这些变化和改进应认为包括在由所附权利要求所规定的要求保护的范围内。而不脱离要求保护的范围。

Claims (11)

1、半导体芯片贴装板，包括半导体芯片贴装面(4a)，该半导体芯片贴装面(4a)上构成有粘接区(2)，并按倒装式芯片贴装法与半导体芯片(1)的电路形成面(1a)上构成的电极(13)电连接；和对着半导体芯片贴装面、并与电路板电连接的电路板贴装面(4b)，
其中，在半导体芯片贴装面还设置增强区(103)，通过凸点(6)用粘接材料(7)把增强区连接到电路形成面上形成的不工作电极(105)，增强区在功能上与半导体芯片无关，只是增大半导体芯片与半导体芯片贴装板之间的连接强度；
其特征在于，所述半导体芯片贴装板有一个超过粘接材料的干燥和固化温度的玻璃转化点。
2、按权利要求1的半导体芯片贴装板，其特征在于，电极和半导体芯片的不工作电极设置有凸点(6)，用粘接材料经凸点使电极和粘接区，不工作电极和增强区相互电连接。
3、按权利要求2的半导体芯片贴装板，其特征在于，半导体芯片贴装面上形成的粘接区和增强区是条形的径向延伸到贴装的半导体芯片，在长度上防止粘接材料扩散到半导体芯片贴装表面的宽度之外，在方向上从接触点(6c)到凸点到半导体芯片的中心部分(107)。
4、按权利要求1至3中任一项的半导体芯片贴装板，其特征在于，贴装板包含热膨胀系数不小于硅的热膨胀系数的材料。
5、按权利要求1至3中任一项的半导体芯片贴装板，其特征在于，半导体芯片贴装到半导体芯片贴装板上之后，半导体芯片与半导体芯片贴装板之间注入密封树脂(8)，贴装板的玻璃转化点超过密封树脂的固化温度。
6、按权利要求1至3中任一项的半导体芯片贴装板，其特征在于，用与半导体芯片的电路形成面上的电极相同的材料和相同的形成方法，构成不工作电极。
7、把半导体芯片(1)贴装到半导体芯片贴装板的方法，该半导体芯片贴装面(4a)上构成有粘接区(2)，并按倒装式芯片贴装法与半导体芯片(1)的电路形成面(1a)上构成的电极(13)电连接；和对着半导体芯片贴装面、并与电路板电连接的电路板贴装面(4b)，该方法包括以下步骤：
半导体芯片的电路形成面(1a)面对半导体芯片贴装面；
通过凸点(6)用粘接材料(7)，把增强区连接到电路形成面上形成的不工作电极(105)；
其特征在于，所述半导体芯片贴装板有一个超过粘接材料的干燥和固化温度的玻璃转化点。
8、按权利要求7的半导体芯片贴装方法，包括：半导体芯片贴装到半导体芯片贴装板上之后，在半导体芯片贴装面上的部分(109)处形成焊料光刻胶(9)，从半导体芯片侧面，按对着半导体芯片的方向，它从凸起位置(108)到半导体芯片贴装面隔开的距离不小于半导体芯片的厚度和半导体芯片贴装面与电路构成面之间的间隙之和。
9、按权利要求7或8的半导体芯片贴装方法，其特征在于，当半导体芯片与半导体芯片贴装板之间加密封树脂(8)时，在半导体芯片贴装面上构成能识别密封树脂开始注入位置的注入开始标记(11)。
10、按权利要求7或8的半导体芯片贴装方法，其特征在于，半导体芯片贴装板包含其热膨胀系数不小于硅的热膨胀系数的材料，它的玻璃转化点超过粘接材料的干燥和固化温度，由此，在半导体芯片贴装到半导体芯片贴装板之后，半导体芯片与半导体芯片贴装板之间加密封树脂，半导体芯片贴装板的玻璃转化点超过密封树脂的干燥和固化温度。
11、按权利要求10的半导体芯片贴装方法，其特征在于，加了密封树脂后，按SMT用焊料把半导体芯片贴装板贴装到电路板上。
CN97117455A 1996-07-19 1997-07-19 半导体芯片贴装板及贴片方法 Expired - Fee Related CN1126167C (zh)

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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69835747T2 (de) * 1997-06-26 2007-09-13 Hitachi Chemical Co., Ltd. Substrat zur montage von halbleiterchips
JP3849277B2 (ja) * 1998-01-26 2006-11-22 ソニー株式会社 半導体装置
WO2000002244A1 (fr) * 1998-07-01 2000-01-13 Seiko Epson Corporation Dispositif a semi-conducteur, procede de fabrication associe, carte imprimee et dispositif electronique
US6528890B1 (en) 1998-12-01 2003-03-04 Micron Technology, Inc. Circuit, method of adhering an integrated circuit device to a substrate, and method of forming a circuit
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
US6546620B1 (en) 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
US20030066679A1 (en) * 2001-10-09 2003-04-10 Castro Abram M. Electrical circuit and method of formation
US6770822B2 (en) * 2002-02-22 2004-08-03 Bridgewave Communications, Inc. High frequency device packages and methods
CN2706865Y (zh) * 2004-05-13 2005-06-29 鸿富锦精密工业（深圳）有限公司 散热器扣具
WO2006008701A2 (en) * 2004-07-13 2006-01-26 Koninklijke Philips Electronics N.V. Assembly and method of placing the assembly on an external board
JP2007116039A (ja) * 2005-10-24 2007-05-10 Alps Electric Co Ltd 回路基板
CN101611490B (zh) * 2007-02-16 2011-07-27 住友电木株式会社 电路板的制造方法、半导体制造装置、电路板和半导体器件
US8581113B2 (en) 2007-12-19 2013-11-12 Bridgewave Communications, Inc. Low cost high frequency device package and methods
JP5599276B2 (ja) * 2010-09-24 2014-10-01 新光電気工業株式会社 半導体素子、半導体素子実装体及び半導体素子の製造方法
US9659893B2 (en) 2011-12-21 2017-05-23 Mediatek Inc. Semiconductor package
US8633588B2 (en) 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
JP6626349B2 (ja) * 2016-01-20 2019-12-25 ローム株式会社 半導体集積回路装置およびその製造方法
CN106132086A (zh) * 2016-07-08 2016-11-16 广东小天才科技有限公司 一种电路板结构及电子元件焊接方法
FR3080972B1 (fr) * 2018-05-07 2021-12-31 Continental Automotive France Procede d'assemblage d'un composant sur une carte de circuit imprime par collage

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
JPS5853837A (ja) * 1981-09-25 1983-03-30 Sharp Corp 電子回路部品の接続方法
JPS6150353A (ja) * 1984-08-20 1986-03-12 Oki Electric Ind Co Ltd Ｅｐｒｏｍ装置
US5326794A (en) * 1990-05-08 1994-07-05 Industrial Technology Research Institute Barbituric acid-modified bismaleimide with diamine and polyisocyanate-modified epoxy resin
US5186383A (en) * 1991-10-02 1993-02-16 Motorola, Inc. Method for forming solder bump interconnections to a solder-plated circuit trace
JPH05259626A (ja) * 1992-03-16 1993-10-08 Matsushita Electric Ind Co Ltd プリント配線板への部品実装方法
US5269453A (en) * 1992-04-02 1993-12-14 Motorola, Inc. Low temperature method for forming solder bump interconnections to a plated circuit trace
US5576362A (en) * 1992-04-20 1996-11-19 Denki Kagaku Kogyo Kabushiki Kaisha Insulating material and a circuit substrate in use thereof
JP3194159B2 (ja) * 1992-04-20 2001-07-30 カシオ計算機株式会社 半導体装置およびその製造方法
JP2652107B2 (ja) * 1992-06-18 1997-09-10 セイコーエプソン株式会社 電気的接続構造
CA2138032A1 (en) * 1992-06-19 1994-01-06 Allen D. Hertz Self-aligning electrical contact array
EP0620594A3 (en) 1993-04-13 1995-01-18 Shinko Electric Ind Co Semiconductor device having connection pins.
US5346118A (en) * 1993-09-28 1994-09-13 At&T Bell Laboratories Surface mount solder assembly of leadless integrated circuit packages to substrates
JPH07153798A (ja) * 1993-11-30 1995-06-16 Sony Corp 半導体製造方法及び半導体製造装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices

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