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CN112489922B - Inductive device - Google Patents

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CN112489922B
CN112489922B CN202010825100.3A CN202010825100A CN112489922B CN 112489922 B CN112489922 B CN 112489922B CN 202010825100 A CN202010825100 A CN 202010825100A CN 112489922 B CN112489922 B CN 112489922B
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CN112489922A (en
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颜孝璁
陈建祐
陈家源
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Realtek Semiconductor Corp
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00Resistors, capacitors or inductors
    • H10D1/20Inductors

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Abstract

一种电感装置,其包括第一走线、第二走线、第三走线、第四走线、第一电容及第二电容。第一走线包括至少两个子走线,至少两个子走线的一端耦接于第一节点。第二走线包括至少两个子走线,至少两个子走线的一端耦接于第二节点。第三走线的一端耦接于第二走线,第三走线的另一端耦接于第一输入输出端。第四走线的一端耦接于第一走线,第四走线的另一端耦接于第二输入输出端。第一电容耦接于第一节点及第二节点之间。第二电容耦接于第一节点及第一输入输出端之间,或于第一节点及第二输入输出端之间,或于第一输入输出端及第二输入输出端之间。

Figure 202010825100

An inductive device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first capacitor and a second capacitor. The first trace includes at least two sub traces, and one ends of the at least two sub traces are coupled to the first node. The second trace includes at least two sub traces, and one ends of the at least two sub traces are coupled to the second node. One end of the third wire is coupled to the second wire, and the other end of the third wire is coupled to the first input and output terminals. One end of the fourth wire is coupled to the first wire, and the other end of the fourth wire is coupled to the second input and output end. The first capacitor is coupled between the first node and the second node. The second capacitor is coupled between the first node and the first input-output terminal, or between the first node and the second input-output terminal, or between the first input-output terminal and the second input-output terminal.

Figure 202010825100

Description

电感装置Inductive device

技术领域technical field

本公开涉及一种电子装置,且特别涉及一种电感装置。The present disclosure relates to an electronic device, and in particular, to an inductive device.

背景技术Background technique

射频(Radio frequency,RF)装置于运行时会产生两倍频谐波(harmonic)、三倍频谐波…等等,上述谐波会对其余电路产生不良影响。例如2.4GHz电路的两倍频谐波会产生5GHz信号进而于集成电路(SOC)产生不良影响。Radio frequency (RF) devices will generate double harmonics (harmonic), triple harmonics, etc. during operation, and the above harmonics will have adverse effects on the rest of the circuit. For example, the double frequency harmonics of a 2.4GHz circuit will generate a 5GHz signal and have an adverse effect on the integrated circuit (SOC).

一般解决上述谐波对电路产生影响的方式,是在电路外部设置滤波器以感应相邻元件的高频信号并可自行设计选择需要的频率以及不需要被滤除的频率。然而,设置于电路外部的滤波器会影响到电路本身的性能和额外的费用,例如:设置于印刷电路板(Printed circuit board,PCB)的费用。Generally, the way to solve the influence of the above harmonics on the circuit is to set up a filter outside the circuit to sense the high-frequency signal of the adjacent components and design and select the required frequency and the frequency that does not need to be filtered out. However, the filter provided outside the circuit will affect the performance of the circuit itself and additional costs, such as the cost of being provided on a printed circuit board (PCB).

发明内容SUMMARY OF THE INVENTION

本公开内容的一技术实施方式涉及一种电感装置,其包括第一走线、第二走线、第三走线、第四走线、第一电容及第二电容。第一走线包括至少两个子走线,且至少两个子走线的一端耦接于第一节点。第二走线包括至少两个子走线,且至少两个子走线的一端耦接于第二节点。第三走线与第一走线配置于第一侧,第三走线的一端耦接于第二走线的至少两个子走线其中一者,第三走线的另一端耦接于第一输入输出端。第四走线与第二走线配置于第二侧,第四走线的一端耦接于第一走线的至少两个子走线其中一者,第四走线的另一端耦接于第二输入输出端。第一电容耦接于第一节点及第二节点之间。第二电容耦接于第一节点及第一输入输出端之间,或耦接于第一节点及第二输入输出端之间,或耦接于第一输入输出端及第二输入输出端之间。A technical embodiment of the present disclosure relates to an inductive device including a first trace, a second trace, a third trace, a fourth trace, a first capacitor, and a second capacitor. The first trace includes at least two sub traces, and one ends of the at least two sub traces are coupled to the first node. The second trace includes at least two sub traces, and one ends of the at least two sub traces are coupled to the second node. The third trace and the first trace are disposed on the first side, one end of the third trace is coupled to one of the at least two sub traces of the second trace, and the other end of the third trace is coupled to the first trace input and output. The fourth trace and the second trace are arranged on the second side, one end of the fourth trace is coupled to one of the at least two sub traces of the first trace, and the other end of the fourth trace is coupled to the second trace input and output. The first capacitor is coupled between the first node and the second node. The second capacitor is coupled between the first node and the first input/output terminal, or between the first node and the second input/output terminal, or between the first input/output terminal and the second input/output terminal between.

因此,根据本公开的技术内容,本公开实施例所示的电感装置中的电容可形成一个低频阻隔的功能,以使于电感装置感应的低频信号无法通过而高频信号能直接通过。低频信号举例而言,如2.4GHz主要操作频率,通过电感装置的曲折的电感架构(foldedinductor)对主要操作频率的感应信号进行相消,所以曲折的电感架构并不会影响电感操作频率的特性,并且感应在曲折二线上的信号会因反向而相消,而若中央电感架构有高频信号,例如2倍谐波5GHz,则因高频信号电容为导通之故,使得高频信号由曲折的电感架构通过电容而形成一个绕围一圈的感应电感,进而在本公开主张的电感架构感应出相对应2.4GHz十倍以上的5GHz谐波信号。使用者再把此5GHz信号于电路中应用,例如放大信号之后再把操作频率的5GHz谐波进行相消,另外其应用放大电路可为熟知电路设计者最佳化调整而定。如此,即可降低对5GHz的电路所产生的不良影响。Therefore, according to the technical content of the present disclosure, the capacitor in the inductive device shown in the embodiment of the present disclosure can form a low-frequency blocking function, so that the low-frequency signal induced by the inductive device cannot pass but the high-frequency signal can directly pass. For example, the low frequency signal, such as the main operating frequency of 2.4GHz, cancels the induced signal of the main operating frequency through the folded inductor structure of the inductor device, so the folded inductor structure does not affect the characteristics of the operating frequency of the inductor. And the signal induced on the zigzag second line will be cancelled due to the reverse direction. If the central inductor structure has high-frequency signals, such as 2 times the harmonic 5GHz, because the high-frequency signal capacitor is turned on, the high-frequency signal is caused by The zigzag inductance structure forms an inductive inductance around a circle through the capacitance, and then the inductive structure claimed in the present disclosure induces a 5GHz harmonic signal that is more than ten times corresponding to 2.4GHz. The user then applies the 5GHz signal in the circuit, for example, after amplifying the signal, cancels the 5GHz harmonics of the operating frequency, and the application of the amplifier circuit can be optimized and adjusted by a well-known circuit designer. In this way, the adverse effect on the 5GHz circuit can be reduced.

再者,由于本公开将滤波器设置于电感装置内,因此,不需于电感装置外部设置滤波器,从而避免外部滤波器影响到电路本身的性能或是增加额外的费用。另外,本公开实施例的电感装置中的电容除可形成一个低频滤除的功能(例如滤除二阶谐波)外,还可通过多个电容间的配置以将更高频的信号(例如四阶谐波)通过短路的方式导引滤除,以避免原先电路四阶谐波的不良影响。Furthermore, since the present disclosure disposes the filter in the inductive device, there is no need to dispose the filter outside the inductive device, so as to prevent the external filter from affecting the performance of the circuit itself or adding extra cost. In addition, the capacitors in the inductive device of the embodiments of the present disclosure can not only form a function of filtering out low frequency (for example, filtering out second-order harmonics), but also can configure a plurality of capacitors to filter higher-frequency signals (for example, filtering out second-order harmonics). Fourth-order harmonics) are guided and filtered out by means of a short circuit to avoid the adverse effects of the fourth-order harmonics of the original circuit.

附图说明Description of drawings

为让本公开的上述和其他目的、特征、优点与实施例能更明显易懂,附图的说明如下:In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the descriptions of the accompanying drawings are as follows:

图1是依照本公开一实施例示出一种电感装置的示意图。FIG. 1 is a schematic diagram illustrating an inductive device according to an embodiment of the present disclosure.

图2是依照本公开一实施例示出一种电感装置的示意图。FIG. 2 is a schematic diagram illustrating an inductive device according to an embodiment of the present disclosure.

图3是依照本公开一实施例示出一种电感装置的示意图。FIG. 3 is a schematic diagram illustrating an inductive device according to an embodiment of the present disclosure.

图4是依照本公开一实施例示出一种电感装置的示意图。FIG. 4 is a schematic diagram illustrating an inductive device according to an embodiment of the present disclosure.

图5是依照本公开一实施例示出一种电感装置的示意图。FIG. 5 is a schematic diagram illustrating an inductive device according to an embodiment of the present disclosure.

图6是依照本公开一实施例示出一种电感装置的示意图。FIG. 6 is a schematic diagram illustrating an inductive device according to an embodiment of the present disclosure.

图7是依照本公开一实施例示出一种电感装置的实验数据示意图。FIG. 7 is a schematic diagram illustrating experimental data of an inductive device according to an embodiment of the present disclosure.

根据惯常的作业方式,图中各种特征与元件并未依比例绘制,其绘制方式是为了以最佳的方式呈现与本公开相关的具体特征与元件。此外,在不同附图间,以相同或相似的元件符号来指称相似的元件/部件。In accordance with common practice, the various features and elements in the figures are not drawn to scale, but are drawn in a manner that best represents the specific features and elements relevant to the present disclosure. Furthermore, the same or similar reference numerals are used to refer to similar elements/components among the different drawings.

符号说明Symbol Description

1000、1000A~1000D:电感装置1000, 1000A~1000D: Inductive device

1100、1100A~1100C:第一走线1100, 1100A~1100C: the first wiring

1110、1110A~1110C:第一子走线1110, 1110A~1110C: The first sub-line

1120、1120A~1120C:第二子走线1120, 1120A~1120C: The second sub wiring

1200、1200A~1200C:第二走线1200, 1200A~1200C: the second wiring

1210、1210A~1210C:第三子走线1210, 1210A~1210C: The third sub wiring

1220、1220A~1220C:第四子走线1220, 1220A~1220C: the fourth sub-line

1300、1300A~1300C:第三走线1300, 1300A~1300C: the third wiring

1310、1310A~1310C:第五子走线1310, 1310A~1310C: Fifth sub-line

1320、1320A~1320C:第六子走线1320, 1320A~1320C: The sixth sub-line

1400、1400A~1400C:第四走线1400, 1400A~1400C: the fourth wiring

1410、1410A~1410C:第七子走线1410, 1410A~1410C: the seventh sub-line

1420、1420A~1420C:第八子走线1420, 1420A~1420C: Eighth sub-line

1500、1500A~1500C:中央抽头端1500, 1500A~1500C: Center tap end

5000C、5000D:电感5000C, 5000D: Inductance

C1、C2、C3:电容C1, C2, C3: Capacitors

E1、E2:曲线E1, E2: Curve

IO1、IO2:输入输出端IO1, IO2: input and output terminals

N1:第一节点N1: the first node

N2:第二节点N2: second node

具体实施方式Detailed ways

图1是依照本公开一实施例示出一种电感装置1000的示意图。为使图1的电感装置1000易于理解,兹将图1的电感装置1000的结构设计图简化为图2的电感装置1000的示意图。FIG. 1 is a schematic diagram illustrating an inductive device 1000 according to an embodiment of the present disclosure. In order to make the inductance device 1000 in FIG. 1 easier to understand, the structural design diagram of the inductance device 1000 in FIG. 1 is simplified as a schematic diagram of the inductance device 1000 in FIG. 2 .

请同时参阅图1及图2,电感装置1000包括第一走线1100、第二走线1200、第三走线1300、第四走线1400、第一电容C1及第二电容C2。再者,第一走线1100包括至少两个子走线1110、1120。第二走线1200包括至少两个子走线1210、1220。Please refer to FIG. 1 and FIG. 2 at the same time, the inductive device 1000 includes a first trace 1100 , a second trace 1200 , a third trace 1300 , a fourth trace 1400 , a first capacitor C1 and a second capacitor C2 . Furthermore, the first trace 1100 includes at least two sub traces 1110 and 1120 . The second trace 1200 includes at least two sub traces 1210 and 1220 .

于一实施例中,至少两个子走线1110、1120的一端(如下端)耦接于第一节点N1。至少两个子走线1210、1220的一端(如下端)耦接于第二节点N2。第一电容C耦接于第一节点N1及第二节点N2之间。In one embodiment, one end (the lower end) of the at least two sub-wires 1110 and 1120 is coupled to the first node N1. One end (the lower end) of the at least two sub-wires 1210 and 1220 is coupled to the second node N2. The first capacitor C is coupled between the first node N1 and the second node N2.

此外,第一走线1100与第三走线1300配置于电感装置1000的第一侧。举例而言,第一走线1100与第三走线1300皆配置于电感装置1000的左侧,且第三走线1300设置于第一走线1100的外侧。第三走线1300的一端耦接于第二走线1200的至少两个子走线1210、1220其中一者,第三走线1300的另一端耦接于第一输入输出端IO1。In addition, the first trace 1100 and the third trace 1300 are disposed on the first side of the inductance device 1000 . For example, the first trace 1100 and the third trace 1300 are both disposed on the left side of the inductive device 1000 , and the third trace 1300 is disposed outside the first trace 1100 . One end of the third trace 1300 is coupled to one of the at least two sub traces 1210 and 1220 of the second trace 1200 , and the other end of the third trace 1300 is coupled to the first input and output terminal IO1 .

另外,第二走线1200与第四走线1400配置于电感装置1000的第二侧。举例而言,第二走线1200与第四走线1400皆配置于电感装置1000的右侧,且第四走线1400设置于第二走线1200的外侧。此外,第四走线1400的一端耦接于第一走线1100的至少两个子走线1110、1120其中一者,第四走线1400的另一端耦接于第二输入输出端IO2。在一实施例中,上述第一侧与第二侧位于电感装置1000的相对两侧。In addition, the second trace 1200 and the fourth trace 1400 are disposed on the second side of the inductor device 1000 . For example, both the second trace 1200 and the fourth trace 1400 are disposed on the right side of the inductive device 1000 , and the fourth trace 1400 is disposed outside the second trace 1200 . In addition, one end of the fourth trace 1400 is coupled to one of the at least two sub traces 1110 and 1120 of the first trace 1100, and the other end of the fourth trace 1400 is coupled to the second input and output terminal IO2. In one embodiment, the first side and the second side are located on opposite sides of the inductor device 1000 .

再者,第一电容C1耦接于第一节点N1及第二节点N2之间。第二电容C2则耦接于第一节点N1及第一输入输出端IO1之间。如此一来,当低频信号欲由第一节点N1往第二节点N2传输时,将被第一电容C1所阻挡,例如2.4GHz的信号会被第一电容C1所阻挡。此外,当高频信号欲由第一节点N1往第二节点N2传输时,则可通过第一电容C1进行传输,例如5GHz的信号可由第一节点N1通过第一电容C1传输到第二节点N2。再者,若更高频的信号欲由第一节点N1往第二节点N2传输,则会通过第二电容C2形成短路,而将更高频的信号导引到第一输入输出端IO1滤除,例如10GHz的信号会被第二电容C2导引滤除。Furthermore, the first capacitor C1 is coupled between the first node N1 and the second node N2. The second capacitor C2 is coupled between the first node N1 and the first input and output terminal IO1. In this way, when a low frequency signal is to be transmitted from the first node N1 to the second node N2, it will be blocked by the first capacitor C1, for example, a 2.4 GHz signal will be blocked by the first capacitor C1. In addition, when the high-frequency signal is to be transmitted from the first node N1 to the second node N2, it can be transmitted through the first capacitor C1. For example, a 5GHz signal can be transmitted from the first node N1 to the second node N2 through the first capacitor C1. . Furthermore, if a higher frequency signal is to be transmitted from the first node N1 to the second node N2, a short circuit will be formed through the second capacitor C2, and the higher frequency signal will be guided to the first input and output terminal IO1 for filtering. , for example, the 10GHz signal will be filtered out by the second capacitor C2.

于一实施例中,第一走线1100的至少两个子走线1110、1120的每一者包括U型子走线。举例而言,子走线1110、1120皆为U型的子走线。此外,第二走线1200的至少两个子走线1210、1220的每一者亦包括U型子走线。举例而言,子走线1210、1220皆为U型的子走线。此外,第三走线1300包括U型走线,第四走线1400包括U型走线。然本公开不以图2的实施例为限,在其余实施例中,走线及子走线亦可为其它适当的形状,端视实际需求而定。In one embodiment, each of the at least two sub-traces 1110, 1120 of the first trace 1100 includes a U-shaped sub-trace. For example, the sub-lines 1110 and 1120 are both U-shaped sub-lines. In addition, each of the at least two sub-traces 1210, 1220 of the second trace 1200 also includes a U-shaped sub-trace. For example, the sub-lines 1210 and 1220 are both U-shaped sub-lines. In addition, the third wire 1300 includes a U-shaped wire, and the fourth wire 1400 includes a U-shaped wire. However, the present disclosure is not limited to the embodiment shown in FIG. 2 , and in other embodiments, the traces and sub-traces may also be in other appropriate shapes, depending on actual requirements.

于另一实施例中,第一走线1100、第二走线1200、第三走线1300及第四走线1400于第三侧(如上侧)交错耦接(crossing)。于一实施例中,第一电容C1及第二电容C2位于第四侧(如下侧)。此外,上述第三侧与第四侧是位于电感装置1000相对的两侧。In another embodiment, the first traces 1100 , the second traces 1200 , the third traces 1300 and the fourth traces 1400 are crossed on the third side (eg, the upper side). In one embodiment, the first capacitor C1 and the second capacitor C2 are located on the fourth side (the following side). In addition, the third side and the fourth side are located on opposite sides of the inductor device 1000 .

于一实施例中,如图1及图2所示,电感装置1000还包括第三电容C3。第三电容C3耦接于第二节点N2及第二输入输出端IO2之间。如此一来,当低频信号欲由第二节点N2往第一节点N1传输时,将被第一电容C1所阻挡。当高频信号欲由第二节点N2往第一节点N1传输时,则可通过第一电容C1进行传输。再者,若更高频的信号欲由第二节点N2往第一节点N1传输,则会通过第三电容C3形成短路,而将更高频的信号导引到第二输入输出端IO2滤除,例如10GHz的信号会被第三电容C3导引滤除。In one embodiment, as shown in FIG. 1 and FIG. 2 , the inductive device 1000 further includes a third capacitor C3 . The third capacitor C3 is coupled between the second node N2 and the second input and output terminal IO2. In this way, when the low frequency signal is to be transmitted from the second node N2 to the first node N1, it will be blocked by the first capacitor C1. When the high frequency signal is to be transmitted from the second node N2 to the first node N1, it can be transmitted through the first capacitor C1. Furthermore, if the higher frequency signal is to be transmitted from the second node N2 to the first node N1, a short circuit will be formed through the third capacitor C3, and the higher frequency signal will be guided to the second input and output terminal IO2 for filtering. , for example, the 10GHz signal will be filtered out by the third capacitor C3.

请同时参阅图1及图2,第一走线1100包括第一子走线1110及第二子走线1120。再者,第一子走线1110及第二子走线1120皆包括第一端及第二端。如图所示,第一子走线1110的第二端(如下端)耦接于第二子走线1120的第二端(如下端)。Please refer to FIG. 1 and FIG. 2 at the same time, the first wiring 1100 includes a first sub wiring 1110 and a second sub wiring 1120 . Furthermore, the first sub-line 1110 and the second sub-line 1120 both include a first end and a second end. As shown in the figure, the second end (the lower end) of the first sub-wire 1110 is coupled to the second end (the lower end) of the second sub-wire 1120 .

此外,第二走线1200包括第三子走线1210及第四子走线1220。再者,第三子走线1210及第四子走线1220皆包括第一端及第二端。如图所示,第三子走线1210的第二端(如下端)耦接于第四子走线1220的第二端(如下端)。In addition, the second trace 1200 includes a third sub trace 1210 and a fourth sub trace 1220 . Furthermore, the third sub-line 1210 and the fourth sub-line 1220 both include a first end and a second end. As shown in the figure, the second end (lower end) of the third sub-wire 1210 is coupled to the second end (lower end) of the fourth sub-wire 1220 .

请同时参阅图1及图2,第三走线1300包括第五子走线1310及第六子走线1320。再者,第五子走线1310及第六子走线1320皆包括第一端及第二端。如图所示,第五子走线1310的第一端(如上端)耦接于第四子走线1220的第一端(如上端)。第六子走线1320的第一端(如上端)耦接于第三子走线1210的第一端(如上端)。此外,第六子走线1320的第二端(如下端)耦接于第一输入输出端IO1。再者,第六子走线1320的第二端(如下端)通过第二电容C2耦接于第一节点N1。在一实施例中,第一输入输出端IO1不耦接于第五子走线1310。Please refer to FIG. 1 and FIG. 2 at the same time, the third wiring 1300 includes a fifth sub wiring 1310 and a sixth sub wiring 1320 . Furthermore, the fifth sub-line 1310 and the sixth sub-line 1320 both include a first end and a second end. As shown in the figure, the first end (eg, the upper end) of the fifth sub-wire 1310 is coupled to the first end (eg, the upper end) of the fourth sub-wire 1220 . The first end (eg, the upper end) of the sixth sub-wire 1320 is coupled to the first end (eg, the upper end) of the third sub-wire 1210 . In addition, the second end (the lower end) of the sixth sub-wire 1320 is coupled to the first input and output end IO1. Furthermore, the second end (the lower end) of the sixth sub-wire 1320 is coupled to the first node N1 through the second capacitor C2. In one embodiment, the first input/output terminal IO1 is not coupled to the fifth sub-wire 1310 .

请同时参阅图1及图2,第四走线1400包括第七子走线1410及第八子走线1420。再者,第七子走线1410及第八子走线1420皆包括第一端及第二端。如图所示,第七子走线1410的第一端(如上端)耦接于第二子走线1120的第一端(如上端),第七子走线1410的第二端(如下端)耦接于第二输入输出端IO2。再者,第七子走线1410的第二端(如下端)通过第三电容C3耦接于第二节点N2。第八子走线1420的第一端(如上端)耦接于第一子走线1110的第一端(如上端),第八子走线1420的第二端(如下端)耦接于第五子走线1310的第二端(如下端)。在一实施例中,第二输入输出端IO2不耦接于第八子走线1420。Please refer to FIG. 1 and FIG. 2 at the same time, the fourth trace 1400 includes a seventh sub trace 1410 and an eighth sub trace 1420 . Furthermore, the seventh sub-line 1410 and the eighth sub-line 1420 both include a first end and a second end. As shown in the figure, the first end (such as the upper end) of the seventh sub-line 1410 is coupled to the first end (such as the upper end) of the second sub-line 1120, and the second end (such as the lower end) of the seventh sub-line 1410 ) is coupled to the second input and output terminal IO2. Furthermore, the second end (the lower end) of the seventh sub-wire 1410 is coupled to the second node N2 through the third capacitor C3. The first end (such as the upper end) of the eighth sub-line 1420 is coupled to the first end (such as the upper end) of the first sub-line 1110, and the second end (such as the lower end) of the eighth sub-line 1420 is coupled to the first end (such as the upper end) of the eighth sub-line 1420. The second end (the end below) of the five sub-wires 1310 . In one embodiment, the second input/output terminal IO2 is not coupled to the eighth sub-wire 1420 .

在另一实施例中,电感装置1000还包括中央抽头端1500。中央抽头端1500设置并耦接于第三走线1300及第四走线1400的交界处。需说明的是,本公开不以图2所示的结构为限,其仅用以例示性地示出本公开的实现方式之一。In another embodiment, the inductive device 1000 further includes a center tap terminal 1500 . The center tap terminal 1500 is disposed and coupled to the junction of the third trace 1300 and the fourth trace 1400 . It should be noted that the present disclosure is not limited to the structure shown in FIG. 2 , which is only used to illustrate one of the implementation manners of the present disclosure.

图3是依照本公开一实施例示出一种电感装置1000A的示意图。相较于图2所示的电感装置1000,图3的电感装置1000A的第二电容C2及第三电容C3的耦接方式不同。如图3所示,第二电容C2耦接于第一节点N1及第二输入输出端IO2之间,且第三电容C3耦接于第二节点N2及第一输入输出端IO1之间。需说明的是,于图3的实施例中,元件标号类似于图2中的元件标号者,具备类似的结构特征,为使说明书简洁,于此不作赘述。此外,本公开不以图3所示的结构为限,其仅用以例示性地示出本公开的实现方式之一。FIG. 3 is a schematic diagram illustrating an inductive device 1000A according to an embodiment of the present disclosure. Compared with the inductive device 1000 shown in FIG. 2 , the coupling manner of the second capacitor C2 and the third capacitor C3 of the inductive device 1000A of FIG. 3 is different. As shown in FIG. 3 , the second capacitor C2 is coupled between the first node N1 and the second input/output terminal IO2 , and the third capacitor C3 is coupled between the second node N2 and the first input/output terminal IO1 . It should be noted that, in the embodiment of FIG. 3 , the element numbers are similar to those in FIG. 2 , and have similar structural features, so that the description is not repeated here. In addition, the present disclosure is not limited to the structure shown in FIG. 3 , which is only used to exemplarily show one of the implementation manners of the present disclosure.

图4是依照本公开一实施例示出一种电感装置1000B的示意图。相较于图2所示的电感装置1000,图4的电感装置1000B的第二电容C2耦接方式不同。如图4所示,第二电容C2耦接于第一输入输出端IO1及第二输入输出端IO2之间。需说明的是,于图4的实施例中,元件标号类似于图2中的元件标号者,具备类似的结构特征,为使说明书简洁,于此不作赘述。此外,本公开不以图4所示的结构为限,其仅用以例示性地示出本公开的实现方式之一。FIG. 4 is a schematic diagram illustrating an inductive device 1000B according to an embodiment of the present disclosure. Compared with the inductive device 1000 shown in FIG. 2 , the coupling manner of the second capacitor C2 of the inductive device 1000B in FIG. 4 is different. As shown in FIG. 4 , the second capacitor C2 is coupled between the first input/output terminal IO1 and the second input/output terminal IO2 . It should be noted that, in the embodiment of FIG. 4 , the component numbers are similar to the component numbers in FIG. 2 , and have similar structural features. For the sake of brevity of the description, details are not repeated here. In addition, the present disclosure is not limited to the structure shown in FIG. 4 , which is only used to exemplarily show one of the implementation manners of the present disclosure.

图5是依照本公开一实施例示出一种电感装置1000C的示意图。相较于图1所示的电感装置1000,图5的电感装置1000C的内部可配置一个电感5000C。需说明的是,于图5的实施例中,元件标号类似于图1中的元件标号者,具备类似的结构特征,为使说明书简洁,于此不作赘述。再者,本公开不以图5的实施例为限,在其余实施例中,电感装置1000C的内部可配置其余形态、种类的电感装置,端视实际需求而定。此外,本公开不以图5所示的结构为限,其仅用以例示性地示出本公开的实现方式之一。FIG. 5 is a schematic diagram illustrating an inductive device 1000C according to an embodiment of the present disclosure. Compared with the inductor device 1000 shown in FIG. 1 , an inductor 5000C can be configured inside the inductor device 1000C of FIG. 5 . It should be noted that, in the embodiment of FIG. 5 , the component numbers are similar to the component numbers in FIG. 1 , and have similar structural features. For the sake of brevity of the description, detailed descriptions are not repeated here. Furthermore, the present disclosure is not limited to the embodiment shown in FIG. 5 . In other embodiments, other forms and types of inductance devices can be configured inside the inductance device 1000C, depending on actual needs. In addition, the present disclosure is not limited to the structure shown in FIG. 5 , which is only used to illustrate one of the implementations of the present disclosure.

图6是依照本公开一实施例示出一种电感装置的示意图。相较于图5将电感5000C配置于电感装置1000C之内,图6是将电感装置1000D配置于电感5000D之内。需说明的是,于图6的实施例中,元件标号类似于图5中的元件标号者,具备类似的结构特征,为使说明书简洁,于此不作赘述。再者,本公开不以图6的实施例为限,在其余实施例中,电感5000D的内部可配置其余形态、种类的电感装置,例如配置图1至图4所示的电感装置1000~1000B,端视实际需求而定。此外,本公开不以图6所示的结构为限,其仅用以例示性地示出本公开的实现方式之一。FIG. 6 is a schematic diagram illustrating an inductive device according to an embodiment of the present disclosure. Compared to FIG. 5 where the inductor 5000C is arranged inside the inductor device 1000C, the inductor device 1000D is arranged inside the inductor 5000D in FIG. 6 . It should be noted that, in the embodiment of FIG. 6 , the component numbers are similar to the component numbers in FIG. 5 , and have similar structural features. For the sake of brevity of the description, detailed descriptions are not repeated here. Furthermore, the present disclosure is not limited to the embodiment shown in FIG. 6 . In other embodiments, other types and types of inductance devices can be configured inside the inductor 5000D, such as the inductor devices 1000 to 1000B shown in FIGS. 1 to 4 . , depending on the actual needs. In addition, the present disclosure is not limited to the structure shown in FIG. 6 , which is only used to exemplarily show one of the implementation manners of the present disclosure.

图7是依照本公开一实施例示出一种电感装置的实验数据示意图。如图所示,采用本公开的架构配置,其S参数(散射参数)的实验曲线为E1、E2,曲线E1为电感装置采用相同电容值的电容的实验曲线,举例而言,电感装置的所有电容等皆采用330fF(法拉)。曲线E2则为电感装置采用不同电容值的电容的实验曲线,举例而言,电感装置的部分电容采用330fF,而部分电容采用150fF。由图中可知,无论是曲线E1或曲线E2,均可有效滤除2.4GHz处的信号,并让5GHz处的信号通过。再者,如图所示,无论是曲线E1或曲线E2,于8GHz以上的信号均往下降,因此,采用本公开的架构配置可进一步滤除8GHz以上的信号,例如可有效滤除10GHz处的信号。FIG. 7 is a schematic diagram illustrating experimental data of an inductive device according to an embodiment of the present disclosure. As shown in the figure, using the structure configuration of the present disclosure, the experimental curves of the S parameters (scattering parameters) are E1 and E2, and the curve E1 is the experimental curve of the inductive device using capacitors with the same capacitance value. Capacitors, etc. are all used 330fF (farad). Curve E2 is an experimental curve of the inductive device using capacitors with different capacitance values. For example, part of the inductive device uses 330fF, and part of the capacitor uses 150fF. As can be seen from the figure, whether it is the curve E1 or the curve E2, the signal at 2.4GHz can be effectively filtered out, and the signal at 5GHz can be passed through. Furthermore, as shown in the figure, whether it is the curve E1 or the curve E2, the signals above 8 GHz all decrease. Therefore, the architecture configuration of the present disclosure can further filter out the signals above 8 GHz, for example, it can effectively filter out the signals above 10 GHz. Signal.

由上述本公开实施方式可知,应用本公开具有下列优点。本公开实施例所示的电感装置可感应中央电感(如图5的电感5000C)的高频信号,例如二阶谐波,于额外的电路放大后,以相消原先电路二阶谐波的不良影响。举例而言,通过电感装置的电容主要使用于让高频通过和阻挡低频的技术效果,如此,即可让同一个电感装置相对于高低频有两种种不同的信号感应方式。As can be seen from the above-described embodiments of the present disclosure, the application of the present disclosure has the following advantages. The inductance device shown in the embodiment of the present disclosure can induce high-frequency signals of a central inductor (such as the inductor 5000C in FIG. 5 ), such as second-order harmonics, after additional circuit amplification, so as to cancel the defects of the second-order harmonics of the original circuit influences. For example, the capacitance through the inductive device is mainly used for the technical effect of allowing high frequencies to pass through and blocking low frequencies. In this way, the same inductive device can have two different signal sensing methods relative to high and low frequencies.

再者,由于本公开将滤波器设置于集成电路(integrated circuit,IC)内,因此,不需于电感装置外部设置滤波器,从而避免外部滤波器影响到电路本身的性能以及其额外的费用。另外,本公开实施例的电感装置中的电容除可形成一个低频滤除的功能(例如滤除二阶谐波)外,还可通过多个电容间的配置以将更高频的信号(例如四阶谐波)通过短路的方式导引滤除,以避免原先电路四阶谐波的不良影响。Furthermore, since the present disclosure disposes the filter in an integrated circuit (IC), there is no need to dispose the filter outside the inductance device, so as to avoid the external filter affecting the performance of the circuit itself and its extra cost. In addition, the capacitors in the inductive device of the embodiments of the present disclosure can not only form a function of filtering out low frequency (for example, filtering out second-order harmonics), but also can configure a plurality of capacitors to filter higher-frequency signals (for example, filtering out second-order harmonics). Fourth-order harmonics) are guided and filtered out by means of a short circuit to avoid the adverse effects of the fourth-order harmonics of the original circuit.

Claims (10)

1.一种电感装置,包括:1. An inductive device comprising: 一第一走线,包括至少两个子走线,其中所述至少两个子走线的一端耦接于一第一节点;a first trace, including at least two sub traces, wherein one end of the at least two sub traces is coupled to a first node; 一第二走线,包括至少两个子走线,其中所述至少两个子走线的一端耦接于一第二节点;a second wiring, including at least two sub wirings, wherein one end of the at least two sub wirings is coupled to a second node; 一第三走线,与该第一走线配置于一第一侧,其中该第三走线的一端耦接于该第二走线的所述至少两个子走线其中一者,该第三走线的另一端耦接于一第一输入输出端;A third trace is disposed on a first side with the first trace, wherein one end of the third trace is coupled to one of the at least two sub traces of the second trace, the third trace The other end of the trace is coupled to a first input and output end; 一第四走线,与该第二走线配置于一第二侧,其中该第四走线的一端耦接于该第一走线的所述至少两个子走线其中一者,该第四走线的另一端耦接于一第二输入输出端;A fourth trace and the second trace are disposed on a second side, wherein one end of the fourth trace is coupled to one of the at least two sub traces of the first trace, the fourth trace is The other end of the trace is coupled to a second input and output end; 一第一电容,耦接于该第一节点及该第二节点之间;及a first capacitor coupled between the first node and the second node; and 一第二电容,耦接于该第一节点及该第一输入输出端之间,或耦接于该第一节点及该第二输入输出端之间,或耦接于该第一输入输出端及该第二输入输出端之间。a second capacitor, coupled between the first node and the first input and output terminals, or between the first node and the second input and output terminals, or coupled to the first input and output terminals and between the second input and output terminals. 2.如权利要求1所述的电感装置,还包括:2. The inductive device of claim 1, further comprising: 一第三电容,耦接于该第二节点及该第一输入输出端之间,或耦接于该第二节点及该第二输入输出端之间,其中该第二电容耦接于该第一节点及该第一输入输出端之间,且该第三电容耦接于该第二节点及该第二输入输出端之间。a third capacitor, coupled between the second node and the first input and output terminals, or between the second node and the second input and output terminals, wherein the second capacitor is coupled to the first input and output terminals between a node and the first input and output terminals, and the third capacitor is coupled between the second node and the second input and output terminals. 3.如权利要求2所述的电感装置,其中该第一走线的所述至少两个子走线包括:3. The inductive device of claim 2, wherein the at least two sub-traces of the first trace comprise: 一第一子走线,包括:A first sub-trace, including: 一第一端;及a first end; and 一第二端;以及a second end; and 一第二子走线,包括:A second sub-trace, including: 一第一端;及a first end; and 一第二端,与该第一子走线的该第二端耦接于该第一节点;a second end coupled to the first node with the second end of the first sub-wire; 其中该第二走线的所述至少两个子走线包括:Wherein the at least two sub-lines of the second track include: 一第三子走线,包括:A third sub-trace, including: 一第一端;及a first end; and 一第二端;以及a second end; and 一第四子走线,包括:A fourth sub-trace, including: 一第一端;及a first end; and 一第二端,与该第三子走线的该第二端耦接于该第二节点。a second end coupled to the second node with the second end of the third sub-wire. 4.如权利要求3所述的电感装置,其中该第三走线包括:4. The inductive device of claim 3, wherein the third trace comprises: 一第五子走线,包括:A fifth sub-line, including: 一第一端,耦接于该第四子走线的该第一端;及a first end coupled to the first end of the fourth sub-wire; and 一第二端;以及a second end; and 一第六子走线,包括:A sixth sub-line, including: 一第一端,耦接于该第三子走线的该第一端;及a first end coupled to the first end of the third sub-wire; and 一第二端,耦接于该第一输入输出端,并通过该第二电容耦接于该第一节点;a second end, coupled to the first input and output end, and coupled to the first node through the second capacitor; 其中该第四走线的至少两个子走线包括:The at least two sub-lines of the fourth track include: 一第七子走线,包括:A seventh sub-line, including: 一第一端,耦接于该第二子走线的该第一端;及a first end coupled to the first end of the second sub-wire; and 一第二端,耦接于该第二输入输出端,并通过该第三电容耦接于该第二节点;以及a second end, coupled to the second input and output end, and coupled to the second node through the third capacitor; and 一第八子走线,包括:One and eighth sub-lines, including: 一第一端,耦接于该第一子走线的该第一端;及a first end coupled to the first end of the first sub-wire; and 一第二端,耦接于该五子走线的该第二端。a second end coupled to the second end of the five sub-wires. 5.如权利要求1所述的电感装置,还包括:5. The inductive device of claim 1, further comprising: 一第三电容,耦接于该第二节点及该第一输入输出端之间,或耦接于该第二节点及该第二输入输出端之间,其中该第二电容耦接于该第一节点及该第二输入输出端之间,且该第三电容耦接于该第二节点及该第一输入输出端之间。a third capacitor coupled between the second node and the first input/output terminal, or between the second node and the second input/output terminal, wherein the second capacitor is coupled to the first input/output terminal between a node and the second input and output terminal, and the third capacitor is coupled between the second node and the first input and output terminal. 6.如权利要求5所述的电感装置,其中该第一走线的所述至少两个子走线包括:6. The inductive device of claim 5, wherein the at least two sub-traces of the first trace comprise: 一第一子走线,包括:A first sub-trace, including: 一第一端;及a first end; and 一第二端;以及a second end; and 一第二子走线,包括:A second sub-trace, including: 一第一端;及a first end; and 一第二端,与该第一子走线的该第二端耦接于该第一节点;a second end coupled to the first node with the second end of the first sub-wire; 其中该第二走线的所述至少两个子走线包括:Wherein the at least two sub-lines of the second track include: 一第三子走线,包括:A third sub-trace, including: 一第一端;及a first end; and 一第二端;以及a second end; and 一第四子走线,包括:A fourth sub-trace, including: 一第一端;及a first end; and 一第二端,与该第三子走线的该第二端耦接于该第二节点。a second end coupled to the second node with the second end of the third sub-wire. 7.如权利要求6所述的电感装置,其中该第三走线包括:7. The inductive device of claim 6, wherein the third trace comprises: 一第五子走线,包括:A fifth sub-line, including: 一第一端,耦接于该第四子走线的该第一端;及a first end coupled to the first end of the fourth sub-wire; and 一第二端;以及a second end; and 一第六子走线,包括:A sixth sub-line, including: 一第一端,耦接于该第三子走线的该第一端;及a first end coupled to the first end of the third sub-wire; and 一第二端,耦接于该第一输入输出端,并通过该第三电容耦接于该第二节点;a second terminal, coupled to the first input and output terminal, and coupled to the second node through the third capacitor; 其中该第四走线的至少两个子走线包括:The at least two sub-lines of the fourth track include: 一第七子走线,包括:A seventh sub-line, including: 一第一端,耦接于该第二子走线的该第一端;及a first end coupled to the first end of the second sub-wire; and 一第二端,耦接于该第二输入输出端,并通过该第二电容耦接于该第一节点;以及a second end coupled to the second input and output end and coupled to the first node through the second capacitor; and 一第八子走线,包括:One and eighth sub-lines, including: 一第一端,耦接于该第一子走线的该第一端;及a first end coupled to the first end of the first sub-wire; and 一第二端,耦接于该五子走线的该第二端。a second end coupled to the second end of the five sub-wires. 8.如权利要求1所述的电感装置,其中该第一走线的所述至少两个子走线的每一者包括U型子走线,其中该第二走线的所述至少两个子走线的每一者包括U型子走线,其中该第三走线包括U型走线,其中该第四走线包括U型走线。8. The inductive device of claim 1, wherein each of the at least two sub-traces of the first trace comprises a U-shaped sub-trace, wherein the at least two sub-traces of the second trace Each of the wires includes a U-shaped sub-trace, wherein the third trace includes a U-shaped trace, and wherein the fourth trace includes a U-shaped trace. 9.如权利要求1所述的电感装置,其中该第三走线设置于该第一走线的外侧,其中该第四走线设置于该第二走线的外侧,其中该第一侧与该第二侧是位于该电感装置相对的两侧。9 . The inductive device of claim 1 , wherein the third trace is disposed outside the first trace, wherein the fourth trace is disposed outside the second trace, and the first side and the The second side is on opposite sides of the inductive device. 10.如权利要求1所述的电感装置,其中该第一走线、该第二走线、该第三走线及该第四走线于一第三侧交错耦接,其中该第一电容及该第二电容位于一第四侧,其中该第三侧与该第四侧是位于该电感装置相对的两侧。10. The inductive device of claim 1, wherein the first trace, the second trace, the third trace and the fourth trace are alternately coupled on a third side, wherein the first capacitor and the second capacitor is located on a fourth side, wherein the third side and the fourth side are located on opposite sides of the inductance device.
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