CN112490360A

CN112490360A - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN112490360A
Application number: CN202010748865.1A
Authority: CN
Inventors: 颜孝璁; 陈家源
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-09-11
Filing date: 2020-07-30
Publication date: 2021-03-12
Anticipated expiration: 2040-07-30
Also published as: TWI715513B; CN112489922B; TW202111737A; CN112490360B; CN112489922A; TW202111740A; TWI722946B

Abstract

A semiconductor device includes a first coil, a second coil, and a third coil. The second coil is disposed opposite the first coil. The third coil is used for inducing the signal of the first coil. The first overlapping area of the third coil and the first coil on a projection plane is larger than the second overlapping area of the third coil and the second coil on the projection plane.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

Embodiments described in this disclosure relate to semiconductor technology, and more particularly, to a semiconductor device.

Background

With the development of semiconductor technology, inductors/transformers have been applied to many electronic devices. In the case of a transformer, the number of turns of the two coils may be different. And the number of turns of the coil will affect the coupling of the signal.

Disclosure of Invention

Some embodiments of the present disclosure relate to a semiconductor device. The semiconductor device includes a first coil, a second coil and a third coil. The second coil is disposed opposite the first coil. The third coil is used for inducing the signal of the first coil. The first overlapping area of the third coil and the first coil on a projection plane is larger than the second overlapping area of the third coil and the second coil on the projection plane.

Some embodiments of the present disclosure relate to a semiconductor device. The semiconductor device includes a first coil, a second coil and a third coil. The third coil is used for sensing the signal of the first coil. A first capacitance value between the third coil and the first coil is larger than a second capacitance value between the third coil and the second coil.

In summary, in the semiconductor device of the present disclosure, the overlapping area between the induction coil (e.g., the third coil) and one of the coils (e.g., the first coil) is larger. Therefore, the coupling between the induction coil and the one coil (for example, the first coil) can be strengthened without influencing other coils (for example, the second coil).

Drawings

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the following description is given:

FIG. 1 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of two coils of FIG. 1, shown in accordance with some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a coil of FIG. 1, according to some embodiments of the present disclosure;

FIG. 4 is an exploded view of the coil of FIG. 3 shown in accordance with some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

FIG. 6 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

FIG. 8A is a graph of signal strength versus frequency for some related art techniques; and

fig. 8B is a graph of signal strength versus frequency, in accordance with some embodiments of the present disclosure.

Description of the symbols

100: semiconductor structure

120: first coil

121: first wire

1211: first end

1212: second end

122: second routing

1221: first end

1222: second end

123: third routing

1231: first end

1232: second end

140: second coil

141: first wire

1411: first end

1412: second end

142: second routing

1421: first end

1422: second end

143: third routing

1431: first end

1432: second end

144: fourth wire

1441: first end

1442: second end

160: third coil

161: first wire

1611: first routing

1612: second routing

162: second routing

163: third routing

164: fourth wire

1641: first routing

1642: second routing

165: fifth wire

166: sixth wire

167: seventh wire

500: semiconductor structure

560: third coil

561: first wire

562: second routing

600: semiconductor structure

660: third coil

661: first wire

662: second routing

700: semiconductor structure

720: first coil

740: second coil

760: third coil

761: main wiring

762: projection part

C1: connecting piece

C2: connecting piece

C3: connecting piece

C4: connecting piece

V1: connecting through hole

V2: connecting through hole

V3: connecting through hole

V4: connecting through hole

V5: connecting through hole

W1: line width

X: direction of rotation

Y: direction of rotation

Detailed Description

The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are not provided to limit the scope of the disclosure, and the description of the structure operation is not intended to limit the execution sequence thereof, and any structure resulting from the rearrangement of elements to produce an apparatus with equivalent technical effect is included in the scope of the disclosure. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described with the same reference numerals in the following description.

Refer to fig. 1. Fig. 1 is a schematic diagram of a semiconductor structure 100 shown in accordance with some embodiments of the present disclosure. For the example of fig. 1, the semiconductor structure 100 includes a first coil 120, a second coil 140, and a third coil 160. The second coil 140 is disposed opposite to the first coil 120. The third coil 160 is disposed below the first coil 120 and the second coil 140.

In some embodiments, the first coil 120 may operate as a transformer in conjunction with the second coil 140. In some embodiments, the first coil 120 and the second coil 140 may each operate as two inductors.

In some embodiments, the number of turns of the first coil 120 is different from the number of turns of the second coil 140. For example, the number of turns of the first coil 120 is smaller than that of the second coil 140. For the example of fig. 1, the first coil 120 includes a first trace 121, a second trace 122 and a third trace 123. The second coil 140 includes a first trace 141, a second trace 142, a third trace 143, and a fourth trace 144.

Refer to fig. 2. Fig. 2 is a schematic diagram of the first coil 120 and the second coil 140 of fig. 1, shown in accordance with some embodiments of the present disclosure.

For the example of fig. 2, the first end 1211 of the first trace 121 can be used as a signal input/output end. The second end 1212 of the first trace 121 is coupled to the first end 1221 of the second trace 122 through a connector C1 and a plurality of via (via) V1. The second end 1222 of the second trace 1222 is coupled to the first end 1231 of the third trace 123 through the connecting via V2. The second end 1232 of the third trace 123 can be used as a signal input/output end.

The first end 1411 of the first trace 141 can be used as a signal input/output end. The second end 1412 of the first trace 141 is coupled to the first end 1421 of the second trace 142 through a connector C2 and a plurality of connecting vias V3. The second end 1422 of the second trace 142 is coupled to the first end 1431 of the third trace 143 by a connector C3 and a plurality of connecting vias V4. The second end 1432 of the third trace 143 is coupled to the first end 1441 of the fourth trace 144 by the connector C4 and the plurality of connecting vias V5. The second end 1442 of the fourth trace 144 can serve as a signal input/output end.

The above-described arrangement of the first coil 120 and the second coil 140 is merely an example, and various applicable arrangements are within the scope of the present disclosure.

Refer to fig. 3 and 4. Fig. 3 is a schematic diagram of the third coil 160 of fig. 1, shown in accordance with some embodiments of the present disclosure. Fig. 4 is an exploded view of the third coil 160 of fig. 3, shown in accordance with some embodiments of the present disclosure. Third coil 160 may operate as an induction coil to induce (couple) a signal on first coil 120 or second coil 140.

For the example of fig. 3, the third coil 160 includes a first trace 161, a second trace 162, a third trace 163, a fourth trace 164, a fifth trace 165, a sixth trace 166, and a seventh trace 167. The third trace 163 is coupled between the first trace 161 and the second trace 162. The sixth trace 166 is coupled between the fourth trace 164 and the fifth trace 165. The seventh trace 167 is coupled to the first trace 161 and the fourth trace 164.

In some embodiments, the first trace 161, the second trace 162, the third trace 163, the fourth trace 164, the fifth trace 165, and the sixth trace 166 are disposed on a metal layer (e.g., M6 metal layer). The seventh trace 167 is disposed on another metal layer (e.g., the M5 metal layer).

In some embodiments, each of the first trace 161, the second trace 162, the third trace 163, the fourth trace 164, the fifth trace 165, and the sixth trace 166 may be a multi-layer structure. In other words, each of the first trace 161, the second trace 162, the third trace 163, the fourth trace 164, the fifth trace 165, and the sixth trace 166 may be formed by stacking a plurality of metal layers. In some embodiments, each of the first trace 161, the second trace 162, the third trace 163, the fourth trace 164, the fifth trace 165, and the sixth trace 166 may be a single-layer structure.

In some embodiments, the second trace 162, the third trace 163, the fifth trace 165, and the sixth trace 166 have a line width W1. In some embodiments, the first trace 161 includes a first sub-trace 1611 and a second sub-trace 1612. The fourth trace 164 includes a first trace 1641 and a second trace 1642. In some embodiments, the first trace 1611, the second trace 1612, the first trace 1641 and the second trace 1642 also have a line width W1.

In some embodiments, the first trace 1611, the second trace 1612, the first trace 1641 and the second trace 1642 of the third coil 160 are disposed corresponding to the first coil 120. For example, referring to fig. 1 again, the first trace 1611 and the second trace 1612 of the first trace 161 of the third coil 160 are disposed on the lower side of the first trace 121 or the third trace 123 of the first coil 120. The first trace 1641 and the second trace 1642 of the fourth trace 164 of the third coil 160 are disposed on the lower side of the first trace 121 or the third trace 123 of the first coil 120. In this case, an overlapping area of the third coil 160 and the first coil 120 on a projection plane (a plane formed by the direction X and the direction Y) is larger than an overlapping area of the third coil 160 and the second coil 140 on the projection plane. Equivalently, the capacitance value between the third coil 160 and the first coil 120 is larger than the capacitance value between the third coil 160 and the second coil 140.

As previously described, the third coil 160 may be used to induce (couple) a signal on the first coil 120 or the second coil 140. In some related arts, if a general induction coil is used, the coupling between the induction coil and the coil having a larger number of turns is larger, and the coupling between the induction coil and the coil having a smaller number of turns is smaller.

Compared to the related arts, in the present disclosure, the overlapping area of the third coil 160 and the first coil 120 (with fewer turns) is larger, so that the coupling between the third coil 160 and the first coil 120 (with fewer turns) can be strengthened without affecting the second coil 140. Accordingly, the semiconductor device 100 of the present disclosure may be applied to some specific applications.

Taking the example of fig. 1, the overlapping area between the third coil 160 and the first coil 120 includes a plurality of overlapping areas. In some embodiments, the ratio of the overlapping area between third coil 160 and first coil 120 to the overlapping area between third coil 160 and second coil 140 is greater than or equal to 1.5, although the disclosure is not so limited. In some embodiments, when the third coil 160 does not overlap the second coil 140, the overlapping area between the third coil 160 and the first coil 120 is greater than a predetermined area. The predetermined area is, for example, substantially 10 square microns, but the disclosure is not limited thereto.

In some embodiments, there may be no gap between the first sub-trace 1611 and the second sub-trace 1612 of the first trace 161. That is, the first trace 1611 and the second trace 1612 can be integrated into a single component. Similarly, in some embodiments, there may be no gap between the first trace 1641 and the second trace 1642 of the fourth trace 164. That is, the first trace 1641 and the second trace 1642 can be integrated into a single component.

Refer to fig. 5. Fig. 5 is a schematic diagram of a semiconductor device 500 shown in accordance with some embodiments of the present disclosure. For simplicity and ease of understanding, fig. 5 shows only the third coil 560 and omits the first and second coils, which respectively operate as two inductors or as a transformer in common. As described above, there may be no gap between the first trace 1611 and the second trace 1612 in fig. 3 to form the first trace 561 in fig. 5. There may be no gap between the first trace 1641 and the second trace 1642 in fig. 3 to form the second trace 562 in fig. 5. For example, in fig. 5, the first trace 561 and the second trace 562 in the third coil 560 are disposed outside the third coil 560. The first trace 561 and the second trace 562 have a first line width, and other traces in the third coil 560 have a second line width, and the first line width is greater than the second line width.

Refer to fig. 6. Fig. 6 is a schematic diagram of a semiconductor device 600 shown in accordance with some embodiments of the present disclosure. For simplicity and ease of understanding, fig. 6 shows only the third coil 660 and omits the first and second coils, which respectively operate as two inductors or as a transformer in common. For simplicity and ease of understanding, fig. 6 shows only the third coil 660 and omits the first and second coils, which respectively operate as two inductors or as a transformer in common. The main difference between the semiconductor device 600 of fig. 6 and the semiconductor device 500 of fig. 5 is that in the semiconductor device 600 of fig. 6, the first trace 611 and the second trace 612 having wider line widths in the third coil 660 are disposed inside the third coil 660.

Refer to fig. 7. Fig. 7 is a schematic diagram of a semiconductor device 700 shown in accordance with some embodiments of the present disclosure. In the example of fig. 7, the semiconductor device 700 includes a first coil 720, a second coil 740, and a third coil 760. In some embodiments, the first coil 720 may operate as a transformer in conjunction with the second coil 740. In some embodiments, the first coil 720 and the second coil 740 may operate as two inductors, respectively.

In the semiconductor device 700, the third coil 760 is provided around the first coil 720 and the second coil 740. In other words, the third coil 760 is disposed outside the first coil 720 and the second coil 740.

For simplicity and ease of understanding, the first coil 720/second coil 740 in fig. 7 only shows a single winding. In fact, in this example, the number of turns of the first coil 720/the second coil 740 is plural, and the number of turns of the first coil 720 is smaller than that of the second coil 740.

In some embodiments, third coil 760 includes a main trace 761 and a tab 762. The protrusion 762 may connect the main trace 761 through the connection through hole. The protruding part 762 overlaps the first coil 720 (having fewer turns) on a projection plane (a plane formed by the direction X and the direction Y) to reinforce the coupling between the third coil 760 and the first coil 720 (having fewer turns).

In the above embodiments, the third coil 760 is disposed below the first coil 720, and the main trace 761 of the third coil 760 is disposed outside the first coil 720 and the second coil 740. However, the disclosure is not so limited. In some other embodiments, the third coil 760 may be disposed on other sides of the first coil 720 and the second coil 740.

Refer to fig. 8A. Fig. 8A is a graph of signal strength versus frequency for some related art techniques. As described above, in some related art, a general induction coil is used, and the coupling (signal strength) between the induction coil and the coil having a larger number of turns is larger, and the coupling (signal strength) between the induction coil and the coil having a smaller number of turns is smaller.

Refer to fig. 8B. Fig. 8B is a graph of signal strength versus frequency, in accordance with some embodiments of the present disclosure. Compared with the related arts, in the present disclosure, the overlapping area between the induction coil (e.g., the third coil) and the coil with fewer turns is larger, so that the coupling (signal strength) between the induction coil (e.g., the third coil) and the coil with fewer turns can be strengthened without affecting the coil with more turns, and a stronger coupling result with fewer coils can be obtained.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that of the appended claims.

Claims

1. A semiconductor device comprising:

a first coil;

a second coil disposed relative to the first coil; and

a third coil for sensing the signal of the first coil, wherein a first overlapping area of the third coil and the first coil on a projection plane is larger than the third coil and the second coil on the projection plane a second overlapping area.

2. The semiconductor device of claim 1, wherein the number of turns of the first coil is smaller than the number of turns of the second coil.

3. The semiconductor device of claim 2, wherein a ratio of the first overlapping area to the second overlapping area is greater than or equal to 1.5.

4. The semiconductor device of claim 1, wherein the third coil comprises:

a first line;

a second line;

a third wiring, coupled between the first wiring and the second wiring;

a fourth line;

a fifth line;

a sixth trace coupled between the fourth trace and the fifth trace; and

A seventh trace is coupled between the first trace and the fourth trace.

5. The semiconductor device of claim 4, wherein the second trace, the third trace, the fifth trace and the sixth trace have a one-line width, the first trace and the fourth trace Each of the lines has a first run and a second run, the first run and the second run have the line width, and the first run and the second run The line overlaps the first coil on the projection plane.

6. The semiconductor device of claim 4, wherein the first trace, the second trace, the third trace, the fourth trace, the fifth trace and the sixth trace are disposed on A first metal layer, and the seventh wiring is disposed on a second metal layer.

7 . The semiconductor device of claim 4 , wherein the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring and the sixth wiring are multiple. 8 . layer structure.

8 . The semiconductor device of claim 1 , wherein the first portion of the wiring in the third coil has a first line width, and the second portion of the wiring in the third coil has a second line width, wherein the first portion of the wiring has a second line width. 9 . The line width is greater than the second line width.

9. The semiconductor device of claim 1, wherein the third coil surrounds the first coil and the second coil.

10. A semiconductor device comprising:

a first coil;

a second coil disposed relative to the first coil; and

a third coil for sensing the signal of the first coil, wherein a first capacitance value between the third coil and the first coil is greater than a second capacitance between the third coil and the second coil value.