TW202111737A - Inductor device - Google Patents
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Description
本案係有關於一種電子裝置,且特別是有關於一種電感裝置。This case is related to an electronic device, and in particular to an inductive device.
射頻(Radio frequency, RF)裝置於運作時會產生兩倍頻諧波(harmonic)、三倍頻諧波…等等,上述諧波會對其餘電路產生不良影響。例如2.4GHz電路的兩倍頻諧波會產生5GHz訊號進而於集成電路(SOC)產生不良影響。Radio frequency (RF) devices will produce double-frequency harmonics (harmonic), triple-frequency harmonics... etc., and the above-mentioned harmonics will have an adverse effect on the rest of the circuit. For example, the double-frequency harmonics of the 2.4GHz circuit will generate a 5GHz signal and then have an adverse effect on the integrated circuit (SOC).
一般解決上述諧波對電路產生影響的方式,是在電路外部設置濾波器以感應相鄰元件的高頻訊號並可自行設計選擇需要的頻率以及不需要被濾除的頻率。然而,設置於電路外部的濾波器會影響到電路本身的性能和額外的費用,例如:設置於印刷電路板(Printed circuit board, PCB)的費用。Generally, the way to solve the above-mentioned harmonics' influence on the circuit is to set a filter outside the circuit to sense the high-frequency signals of adjacent components and to design and select the required frequency and the frequency that does not need to be filtered. However, the filter installed outside the circuit will affect the performance of the circuit itself and additional costs, such as the cost of installing it on a printed circuit board (PCB).
本案內容之一技術態樣係關於一種電感裝置,其包括第一走線、第二走線、第三走線、第四走線、第一電容及第二電容。第一走線包括至少兩個子走線,且至少兩個子走線的一端耦接於第一節點。第二走線包括至少兩個子走線,且至少兩個子走線的一端耦接於第二節點。第三走線與第一走線配置於第一側,第三走線之一端耦接於第二走線之至少兩個子走線其中一者,第三走線之另一端耦接於第一輸入輸出端。第四走線與第二走線配置於第二側,第四走線之一端耦接於第一走線之至少兩個子走線其中一者,第四走線之另一端耦接於第二輸入輸出端。第一電容耦接於第一節點及第二節點之間。第二電容耦接於第一節點及第一輸入輸出端之間,或耦接於第一節點及第二輸入輸出端之間,或耦接於第一輸入輸出端及第二輸入輸出端之間。One technical aspect of this case relates to an inductive device, which includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first capacitor, and a second capacitor. The first wire includes at least two sub wires, and one end of the at least two sub wires is coupled to the first node. The second wire includes at least two sub wires, and one end of the at least two sub wires is coupled to the second node. The third trace and the first trace are arranged on the first side, one end of the third trace is coupled to one of the at least two sub traces of the second trace, and the other end of the third trace is coupled to the second trace An input and output terminal. The fourth trace and the second trace are arranged on the second side, one end of the fourth trace is coupled to one of the at least two sub traces of the first trace, and the other end of the fourth trace is coupled to the first trace Two input and output terminals. The first capacitor is coupled between the first node and the second node. The second capacitor is coupled between the first node and the first input/output terminal, or between the first node and the second input/output terminal, or between the first input/output terminal and the second input/output terminal between.
因此,根據本案之技術內容,本案實施例所示之電感裝置中的電容可形成一個低頻阻隔的功能,以使於電感裝置感應的低頻訊號無法通過而高頻訊號能直接通過。低頻訊號舉例而言,如2.4GHz主要操作頻率,藉由電感裝置之曲折的電感架構(folded inductor)對主要操作頻率的感應訊號進行相消,所以曲折的電感架構並不會影響電感操作頻率的特性,並且感應在曲折二線上的訊號會因反向而相消而若中央電感架構有高頻訊號,例如2倍諧波5GHz,則因高頻訊號電容為導通之故,使得高頻訊號由曲折的電感架構通過電容而形成一個繞圍一圈的感應電感,進而在本案主張之電感架構感應出相對應2.4GHz十倍以上的5GHz諧波訊號。使用者再把此5GHz訊號於電路中應用,例如放大訊號之後再把操作頻率的5GHz諧波進行相消,另其應用放大電路可為熟知電路設計者最佳化調整而定。如此,即可降低對5GHz之電路所產生的不良影響。Therefore, according to the technical content of the present case, the capacitor in the inductive device shown in the embodiment of the present case can form a low-frequency blocking function, so that the low-frequency signal induced by the inductive device cannot pass but the high-frequency signal can pass directly. For example, for low-frequency signals, such as the main operating frequency of 2.4GHz, the folded inductor of the inductive device cancels the induced signal at the main operating frequency, so the tortuous inductor structure does not affect the operating frequency of the inductor. Characteristics, and the signal induced on the second zigzag line will be canceled due to the reverse. If the central inductance structure has a high-frequency signal, such as 2 times the harmonic 5GHz, the high-frequency signal capacitor is turned on, making the high-frequency signal from The tortuous inductance structure forms an inductive inductance around the circle through the capacitor, and then the inductance structure proposed in this case induces a 5GHz harmonic signal corresponding to more than ten times the 2.4GHz. The user then applies the 5GHz signal in the circuit, for example, after amplifying the signal, cancels the 5GHz harmonics of the operating frequency. In addition, the application of the amplifier circuit can be optimized and adjusted by the well-known circuit designer. In this way, the adverse effects on the 5GHz circuit can be reduced.
再者,由於本案將濾波器設置於電感裝置內,因此,不需於電感裝置外部設置濾波器,從而避免外部濾波器影響到電路本身的性能或是增加額外的費用。另外,本案實施例之電感裝置中的電容除可形成一個低頻濾除的功能(例如濾除二階諧波)外,更可藉由多個電容間的配置以將更高頻的訊號(例如四階諧波)藉由短路的方式導引濾除,以避免原先電路四階諧波的不良影響。Furthermore, since the filter is arranged in the inductance device in this case, it is not necessary to install the filter outside the inductance device, so as to prevent the external filter from affecting the performance of the circuit itself or adding extra costs. In addition, the capacitors in the inductance device of the embodiment of the present case can not only form a low-frequency filtering function (such as filtering second-order harmonics), but can also configure multiple capacitors to remove higher frequency signals (such as four First-order harmonics) are guided and filtered by a short circuit to avoid the adverse effects of the fourth-order harmonics of the original circuit.
第1圖係依照本揭露一實施例繪示一種電感裝置1000的示意圖。為使第1圖之電感裝置1000易於理解,茲將第1圖之電感裝置1000的結構設計圖簡化為第2圖之電感裝置1000的示意圖。FIG. 1 is a schematic diagram of an
請同時參閱第1圖及第2圖,電感裝置1000包括第一走線1100、第二走線1200、第三走線1300、第四走線1400、第一電容C1及第二電容C2。再者,第一走線1100包括至少兩個子走線1110、1120。第二走線1200包括至少兩個子走線1210、1220。Please refer to FIGS. 1 and 2 at the same time. The
於一實施例中,至少兩個子走線1110、1120的一端(如下端)耦接於第一節點N1。至少兩個子走線1210、1220的一端(如下端)耦接於第二節點N2。第一電容C耦接於第一節點N1及第二節點N2之間。In one embodiment, one end (the lower end) of the at least two
此外,第一走線1100與第三走線1300配置於電感裝置1000的第一側。舉例而言,第一走線1100與第三走線1300皆配置於電感裝置1000的左側,且第三走線1300設置於第一走線1100之外側。第三走線1300之一端耦接於第二走線1200之至少兩個子走線1210、1220其中一者,第三走線1300之另一端耦接於第一輸入輸出端IO1。In addition, the
另外,第二走線1200與第四走線1400配置於電感裝置1000的第二側。舉例而言,第二走線1200與第四走線1400皆配置於電感裝置1000的右側,且第四走線1400設置於第二走線1200之外側。此外,第四走線1400之一端耦接於第一走線1100之至少兩個子走線1110、1120其中一者,第四走線1400之另一端耦接於第二輸入輸出端IO2。在一實施例中,上述第一側與第二側位於電感裝置1000的相對兩側。In addition, the
再者,第一電容C1耦接於第一節點N1及第二節點N2之間。第二電容C2則耦接於第一節點N1及第一輸入輸出端IO1之間。如此一來,當低頻訊號欲由第一節點N1往第二節點N2傳輸時,將被第一電容C1所阻擋,例如2.4GHz之訊號會被第一電容C1所阻擋。此外,當高頻訊號欲由第一節點N1往第二節點N2傳輸時,則可透過第一電容C1進行傳輸,例如5GHz之訊號可由第一節點N1透過第一電容C1傳輸到第二節點N2。再者,若更高頻的訊號欲由第一節點N1往第二節點N2傳輸,則會透過第二電容C2形成短路,而將更高頻的訊號導引到第一輸入輸出端IO1濾除,例如10GHz之訊號會被第二電容C2導引濾除。Furthermore, the first capacitor C1 is coupled between the first node N1 and the second node N2. The second capacitor C2 is coupled between the first node N1 and the first input/output terminal IO1. In this way, when the low-frequency signal is to be transmitted from the first node N1 to the second node N2, it will be blocked by the first capacitor C1, for example, a 2.4 GHz signal will be blocked by the first capacitor C1. In addition, when the high frequency signal is to be transmitted from the first node N1 to the second node N2, it can be transmitted through the first capacitor C1. For example, a 5GHz signal can be transmitted from the first node N1 to the second node N2 through the first capacitor C1. . Furthermore, if a higher frequency signal is to be transmitted from the first node N1 to the second node N2, a short circuit is formed through the second capacitor C2, and the higher frequency signal is directed to the first input and output terminal IO1 to filter out For example, the signal of 10 GHz will be guided and filtered by the second capacitor C2.
於一實施例中,第一走線1100之至少兩個子走線1110、1120的每一者包括U型子走線。舉例而言,子走線1110、1120皆為U型之子走線。此外,第二走線1200的至少兩個子走線1210、1220的每一者亦包括U型子走線。舉例而言,子走線1210、1220皆為U型之子走線。此外,第三走線1300包括U型走線,第四走線1400包括U型走線。然本案不以第2圖之實施例為限,在其餘實施例中,走線及子走線亦可為其它適當之形狀,端視實際需求而定。In one embodiment, each of the at least two
於另一實施例中,第一走線1100、第二走線1200、第三走線1300及第四走線1400於第三側(如上側)交錯耦接(crossing)。於一實施例中,第一電容C1及第二電容C2位於第四側(如下側)。此外,上述第三側與第四側係位於電感裝置1000相對之兩側。In another embodiment, the
於一實施例中,如第1圖及第2圖所示,電感裝置1000更包括第三電容C3。第三電容C3耦接於第二節點N2及第二輸入輸出端IO2之間。如此一來,當低頻訊號欲由第二節點N2往第一節點N1傳輸時,將被第一電容C1所阻擋。當高頻訊號欲由第二節點N2往第一節點N1傳輸時,則可透過第一電容C1進行傳輸。再者,若更高頻的訊號欲由第二節點N2往第一節點N1傳輸,則會透過第三電容C3形成短路,而將更高頻的訊號導引到第二輸入輸出端IO2濾除,例如10GHz之訊號會被第三電容C3導引濾除。In one embodiment, as shown in FIG. 1 and FIG. 2, the
請同時參閱第1圖及第2圖,第一走線1100包括第一子走線1110及第二子走線1120。再者,第一子走線1110及第二子走線1120皆包括第一端及第二端。如圖所示,第一子走線1110的第二端(如下端)耦接於第二子走線1120的第二端(如下端)。Please refer to FIG. 1 and FIG. 2 at the same time. The
此外,第二走線1200包括第三子走線1210及第四子走線1220。再者,第三子走線1210及第四子走線1220皆包括第一端及第二端。如圖所示,第三子走線1210的第二端(如下端)耦接於第四子走線1220的第二端(如下端)。In addition, the
請同時參閱第1圖及第2圖,第三走線1300包括第五子走線1310及第六子走線1320。再者,第五子走線1310及第六子走線1320皆包括第一端及第二端。如圖所示,第五子走線1310的第一端(如上端)耦接於第四子走線1220之第一端(如上端)。第六子走線1320的第一端(如上端)耦接於第三子走線1210之第一端(如上端)。此外,第六子走線1320的第二端(如下端)耦接於第一輸入輸出端IO1。再者,第六子走線1320的第二端(如下端)透過第二電容C2耦接於第一節點N1。在一實施例中,第一輸入輸出端IO1不耦接於第五子走線1310。Please refer to FIG. 1 and FIG. 2 at the same time. The
請同時參閱第1圖及第2圖,第四走線1400包括第七子走線1410及第八子走線1420。再者,第七子走線1410及第八子走線1420皆包括第一端及第二端。如圖所示,第七子走線1410的第一端(如上端)耦接於第二子走線1120之第一端(如上端),第七子走線1410的第二端(如下端)耦接於第二輸入輸出端IO2。再者,第七子走線1410的第二端(如下端)透過第三電容C3耦接於第二節點N2。第八子走線1420的第一端(如上端)耦接於第一子走線1110之第一端(如上端),第八子走線1420的第二端(如下端)耦接於第五子走線1310之第二端(如下端)。在一實施例中,第二輸入輸出端IO2不耦接於第八子走線1420。Please refer to FIG. 1 and FIG. 2 at the same time. The
在另一實施例中,電感裝置1000更包括中央抽頭端1500。中央抽頭端1500設置並耦接於於第三走線1300及第四走線1400之交界處。需說明的是,本案不以第2圖所示之結構為限,其僅用以例示性地繪示本案的實現方式之一。In another embodiment, the
第3圖係依照本揭露一實施例繪示一種電感裝置1000A的示意圖。相較於第2圖所示之電感裝置1000,第3圖之電感裝置1000A的第二電容C2及第三電容C3之耦接方式不同。如第3圖所示,第二電容C2耦接於第一節點N1及第二輸入輸出端IO2之間,且第三電容C3耦接於第二節點N2及第一輸入輸出端IO1之間。需說明的是,於第3圖之實施例中,元件標號類似於第2圖中的元件標號者,具備類似的結構特徵,為使說明書簡潔,於此不作贅述。此外,本案不以第3圖所示之結構為限,其僅用以例示性地繪示本案的實現方式之一。FIG. 3 is a schematic diagram of an
第4圖係依照本揭露一實施例繪示一種電感裝置1000B的示意圖。相較於第2圖所示之電感裝置1000,第4圖之電感裝置1000B的第二電容C2耦接方式不同。如第4圖所示,第二電容C2耦接於第一輸入輸出端IO1及第二輸入輸出端IO2之間。需說明的是,於第4圖之實施例中,元件標號類似於第2圖中的元件標號者,具備類似的結構特徵,為使說明書簡潔,於此不作贅述。此外,本案不以第4圖所示之結構為限,其僅用以例示性地繪示本案的實現方式之一。FIG. 4 is a schematic diagram of an
第5圖係依照本揭露一實施例繪示一種電感裝置1000C的示意圖。相較於第1圖所示之電感裝置1000,第5圖之電感裝置1000C的內部可配置一個電感5000C。需說明的是,於第5圖之實施例中,元件標號類似於第1圖中的元件標號者,具備類似的結構特徵,為使說明書簡潔,於此不作贅述。再者,本案不以第5圖之實施例為限,在其餘實施例中,電感裝置1000C的內部可配置其餘型態、種類之電感,端視實際需求而定。此外,本案不以第5圖所示之結構為限,其僅用以例示性地繪示本案的實現方式之一。FIG. 5 is a schematic diagram of an
第6圖係依照本揭露一實施例繪示一種電感裝置的示意圖。相較於第5圖將電感5000C配置於電感裝置1000C之內,第6圖係將電感裝置1000D配置於電感5000D之內。需說明的是,於第6圖之實施例中,元件標號類似於第5圖中的元件標號者,具備類似的結構特徵,為使說明書簡潔,於此不作贅述。再者,本案不以第6圖之實施例為限,在其餘實施例中,電感5000D的內部可配置其餘型態、種類之電感裝置,例如配置第1圖至第4圖所示之電感裝置1000~1000B,端視實際需求而定。此外,本案不以第6圖所示之結構為限,其僅用以例示性地繪示本案的實現方式之一。FIG. 6 is a schematic diagram of an inductance device according to an embodiment of the disclosure. Compared with the
第7圖係依照本揭露一實施例繪示一種電感裝置的實驗數據示意圖。如圖所示,採用本案之架構配置,其S參數(散射參數)之實驗曲線為E1、E2,曲線E1為電感裝置採用相同電容值之電容的實驗曲線,舉例而言,電感裝置的所有電容等皆採用330fF(法拉)。曲線E2則為電感裝置採用不同電容值之電容的實驗曲線,舉例而言,電感裝置的部分電容採用330fF,而部分電容採用150fF。由圖中可知,無論是曲線E1或曲線E2,均可有效濾除2.4GHz處之訊號,並讓5GHz處之訊號通過。再者,如圖所示,無論是曲線E1或曲線E2,於8GHz以上之訊號均往下降,因此,採用本案之架構配置可進一步濾除8GHz以上之訊號,例如可有效濾除10GHz處之訊號。FIG. 7 is a schematic diagram of experimental data of an inductance device according to an embodiment of the present disclosure. As shown in the figure, with the architecture configuration of this case, the experimental curves of the S parameters (scattering parameters) are E1 and E2, and the curve E1 is the experimental curve of the inductive device using the same capacitance value. For example, all the capacitors of the inductive device All use 330fF (Farad). Curve E2 is an experimental curve of inductance devices using capacitors with different capacitance values. For example, part of the capacitance of the inductance device uses 330fF, and some of the capacitors use 150fF. It can be seen from the figure that whether it is curve E1 or curve E2, the signal at 2.4GHz can be effectively filtered out and the signal at 5GHz can be passed through. Furthermore, as shown in the figure, regardless of the curve E1 or the curve E2, the signal above 8GHz is going down. Therefore, the architecture configuration of this case can further filter the signal above 8GHz, for example, it can effectively filter the signal at 10GHz. .
由上述本案實施方式可知,應用本案具有下列優點。本案實施例所示之電感裝置可感應中央電感(如第5圖之電感5000C)的高頻訊號,例如二階諧波,於額外的電路放大後,以相消原先電路二階諧波的不良影響。舉例而言,藉由電感裝置之電容主要使用於讓高頻通過和阻擋低頻的功效,如此,即可讓同一個電感裝置相對於高低頻有二種不同的訊號感應方式。It can be seen from the above implementation of this case that the application of this case has the following advantages. The inductance device shown in the embodiment of this case can induce the high frequency signal of the central inductor (such as the
再者,由於本案將濾波器設置於積體電路(integrated circuit,IC)內,因此,不需於電感裝置外部設置濾波器,從而避免外部濾波器影響到電路本身的性能以及其額外的費用。另外,本案實施例之電感裝置中的電容除可形成一個低頻濾除的功能(例如濾除二階諧波)外,更可藉由多個電容間的配置以將更高頻的訊號(例如四階諧波)藉由短路的方式導引濾除,以避免原先電路四階諧波的不良影響。Furthermore, since the filter is arranged in an integrated circuit (IC) in this case, it is not necessary to install a filter outside the inductance device, thereby preventing the external filter from affecting the performance of the circuit itself and its extra cost. In addition, the capacitors in the inductance device of the embodiment of the present case can not only form a low-frequency filtering function (such as filtering second-order harmonics), but can also configure multiple capacitors to remove higher frequency signals (such as four First-order harmonics) are guided and filtered by a short circuit to avoid the adverse effects of the fourth-order harmonics of the original circuit.
1000、1000A~1000D:電感裝置
1100、1100A~1100C:第一走線
1110、1110A~1110C:第一子走線
1120、1120A~1120C:第二子走線
1200、1200A~1200C:第二走線
1210、1210A~1210C:第三子走線
1220、1220A~1220C:第四子走線
1300、1300A~1300C:第三走線
1310、1310A~1310C:第五子走線
1320、1320A~1320C:第六子走線
1400、1400A~1400C:第四走線
1410、1410A~1410C:第七子走線
1420、1420A~1420C:第八子走線
1500、1500A~1500C:中央抽頭端
5000C、5000D:電感
C1、C2、C3:電容
E1、E2:曲線
IO1、IO2:輸入輸出端
N1:第一節點
N2:第二節點1000, 1000A~1000D:
為讓本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下: 第1圖係依照本揭露一實施例繪示一種電感裝置的示意圖。 第2圖係依照本揭露一實施例繪示一種電感裝置的示意圖。 第3圖係依照本揭露一實施例繪示一種電感裝置的示意圖。 第4圖係依照本揭露一實施例繪示一種電感裝置的示意圖。 第5圖係依照本揭露一實施例繪示一種電感裝置的示意圖。 第6圖係依照本揭露一實施例繪示一種電感裝置的示意圖。 第7圖係依照本揭露一實施例繪示一種電感裝置的實驗數據示意圖。 根據慣常的作業方式,圖中各種特徵與元件並未依比例繪製,其繪製方式是為了以最佳的方式呈現與本揭露相關的具體特徵與元件。此外,在不同圖式間,以相同或相似的元件符號來指稱相似的元件/部件。In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows: FIG. 1 is a schematic diagram of an inductance device according to an embodiment of the disclosure. FIG. 2 is a schematic diagram of an inductance device according to an embodiment of the disclosure. FIG. 3 is a schematic diagram of an inductance device according to an embodiment of the disclosure. FIG. 4 is a schematic diagram of an inductance device according to an embodiment of the disclosure. FIG. 5 is a schematic diagram of an inductance device according to an embodiment of the disclosure. FIG. 6 is a schematic diagram of an inductance device according to an embodiment of the disclosure. FIG. 7 is a schematic diagram of experimental data of an inductance device according to an embodiment of the present disclosure. According to the usual operation method, the various features and components in the figure are not drawn to scale, and the drawing method is to best present the specific features and components related to the present disclosure. In addition, between different drawings, the same or similar element symbols are used to refer to similar elements/components.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無Domestic deposit information (please note in the order of deposit institution, date and number) no Foreign hosting information (please note in the order of hosting country, institution, date, and number) no
1000:電感裝置1000: Inductive device
1100:第一走線1100: First trace
1110、1120:子走線1110, 1120: sub-wiring
1200:第二走線1200: second trace
1210、1220:子走線1210, 1220: sub-wiring
1300:第三走線1300: third trace
1310、1320:子走線1310, 1320: sub-wiring
1400:第四走線1400: fourth line
1410、1420:子走線1410, 1420: sub-wiring
1500:中央抽頭端1500: Center tapped end
C1、C2、C3:電容C1, C2, C3: Capacitance
IO1、IO2:輸入輸出端IO1, IO2: input and output terminals
N1:第一節點N1: the first node
N2:第二節點N2: second node
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US201962898618P | 2019-09-11 | 2019-09-11 | |
US62/898,618 | 2019-09-11 | ||
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US62/904,750 | 2019-09-24 |
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