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CN111696970A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN111696970A
CN111696970A CN201910806790.5A CN201910806790A CN111696970A CN 111696970 A CN111696970 A CN 111696970A CN 201910806790 A CN201910806790 A CN 201910806790A CN 111696970 A CN111696970 A CN 111696970A
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ground
semiconductor
conductor layer
layer
power supply
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CN111696970B (zh
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大塚靖夫
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

根据一个实施方式，实施方式的半导体装置(1)具备：配线基板(2)；间隔基板(3)，其搭载在配线基板(2)上，内设有电源导体层(7)与接地导体层(8)；至少一个第1半导体芯片(4)，其安装在间隔基板(3)上，具有与电源导体层(7)电连接的电源层及与接地导体层(8)电连接的接地层；及第2半导体芯片(5)，其安装在配线基板(2)上。

Description

半导体装置
関連申请案的引用
本申请案是基于2019年3月14申请的先前的日本专利申请案第2019-046938号的优先权的利益，且请求其利益，并将其内容全体通过引用而包含于此。
技术领域
此处说明的多个实施方式全体涉及半导体装置。
背景技术
在内置有NAND型闪速存储器等存储器芯片的半导体存储装置中，小型化与高容量化快速发展。在如半导体存储装置那样的半导体装置中应用如下构成，即，为了兼顾小型化与高容量化，例如将多个存储器芯片等半导体芯片的积层体隔着间隔件安装在配线基板上，并且将存储器芯片的控制器芯片等半导体芯片安装在配线基板上，且以树脂层密封这些多个半导体芯片。该半导体装置中，随着存储器芯片的高速化，要求进一步抑制电源-接地间的电压变动噪声。
例如，提出如下方案，即，在安装在配线基板上的多个半导体芯片间配置导体涂层芯片，并且将导体涂层芯片与半导体芯片的接地、导体涂层芯片与配线基板的接地分别以较短的导线连接，由此降低接地的电阻及电感。进而，通过导体涂层芯片的接地导体层与半导体芯片的电源导体层来增加电源-接地间的电容，由此使电源-接地间的阻抗降低。
在抑制半导体装置的电源-接地间的电压变动噪声时，随着半导体装置的高速化，需要变小的电源-接地间的阻抗的频率范围向高频区域扩大。为了降低高频的电源-接地间的阻抗，需要增加电源-接地间的电容。然而，上述的先前构造中，为了在导体涂层芯片的接地导体层与半导体芯片的电源导体层增加电容，电源层与接地层之间的距离受芯片的厚度限制，难以进一步增加电容。因此，存在无法充分获得所期待的电源-接地间的电压变动噪声的抑制效果的问题。
发明内容
本发明的实施方式，提供通过降低高频的电源-接地间的阻抗而可抑制电源一接地间的电压变动噪声的半导体装置。
根据实施方式的半导体装置，具备：配线基板；间隔基板，其搭载在所述配线基板上，内设有电源导体层与接地导体层；至少一个第1半导体芯片，其等安装在所述间隔基板上，具有与所述电源导体层电连接的电源层及与所述接地导体层电连接的接地层；及第2半导体芯片，其安装在所述配线基板上。
根据上述构成，可提供通过降低高频的电源-接地间的阻抗而能够抑制电源-接地间的电压变动噪声的半导体装置。
附图说明
图1是表示第1实施方式的半导体装置的截面图。
图2是表示第2实施方式的半导体装置的截面图。
图3是表示第3实施方式的半导体装置的截面图。
具体实施方式
以下，参照图式对实施方式的半导体装置进行说明。另外，各实施方式中，存在对实质上相同的构成部位附上相同符号，并省略其一部分说明的情况。图式为示意性的图，厚度与平面尺寸的关系、各部的厚度的比率等存在与实物不同的情况。说明中的表示上下等方向的用语，在未特别明示的情况下，均表示以后述的配线基板的半导体芯片的搭载面为上的情况下的相对性的方向，存在与以重力加速度方向为基准的现实方向不同的情况。
(第1实施方式)图1是表示第1实施方式的半导体装置的构成的截面图。图1所示的半导体装置1具备：配线基板2；间隔基板3，其搭载在配线基板2上；多个第1半导体芯片4(4A、4B)，其等安装在间隔基板3上；第2半导体芯片5，其安装在通过间隔基板3确保安装空间的配线基板2上；及密封树脂层6，其密封第1及第2半导体芯片4、5。间隔基板3如下文详述那样，内设有电源导体层7与接地导体层8。
作为配线基板2，使用例如在绝缘树脂基板的表面或内部设置有配线网(未图示)的配线基板，具体而言使用印刷配线板(多层印刷基板等)，该印刷配线板使用玻璃-环氧树脂或BT树脂(双马来酰亚胺三嗪树脂)等。印刷配线板等配线基板2，通常具有作为配线网的Cu层(未图示)。配线基板2具有成为外部端子的形成面的第1表面2a、及成为第1及第2半导体芯片4、5的安装面的第2表面2b。
在配线基板2的第1面2a设置有多个外部电极9。在配线基板2的第2面2b设置有多个内部电极10，这些多个内部电极10成为间隔基板3的电源导体层7与接地导体层8或第1及第2半导体芯片4、5的电连接部，并且利用省略图示的内部配线与外部电极9电连接。在配线基板2的外部电极9上形成有外部端子11。在以BGA(Ball Grid Array，球栅阵列)封装的形式使用半导体装置1的情况下，外部端子11由使用焊料球或焊料镀覆等的连接端子(球电极)构成。在以LGA(Land Grid Array，栅格阵列)封装的形式使用半导体装置1的情况下，作为外部端子11，应用使用镀Au等的金属焊盘。
在搭载在配线基板2的第2面2b的间隔基板3上，配置有多个第1半导体芯片4A、4B。第1半导体芯片4A、4B分别具有多个电极焊垫12(12A、12B)。第1半导体芯片4A、4B以各自的电极焊垫12A、12B露出的方式积层为阶梯状。作为第1半导体芯片4的具体例，可列举NAND型闪速存储器等存储器芯片，但并不限定于这些。图1表示将2个第1半导体芯片4A、4B积层为阶梯状的构造，第1半导体芯片4的相对于配线基板2的安装数或安装构造并不限定于此。第1半导体芯片4的安装数并不限定于2个，也可为1个或3个以上的多个的任一者。第1半导体芯片4的多个电极焊垫12中，信号焊垫在它们之间以导线13连接，进而以导线14与配线基板2的内部电极10连接。
在配线基板2的第2面2b上，进而搭载有第2半导体芯片5。第2半导体芯片5的至少一部分，配置在包含有在间隔基板3升高、且阶梯状积层的多个半导体芯片4A、4B的从间隔基板3突出的部分的下侧的空间。第2半导体芯片5具有多个电极焊垫15，这些电极焊垫15经由导线16与配线基板2的内部电极10电连接。作为第2半导体芯片5，可列举在作为第1半导体芯片4的存储器芯片与外部设备之间接收发送数字信号的控制器芯片或接口芯片、逻辑芯片、RF(radio frequency，射频)芯片等系统LSI(large scale integration，大规模集成电路)芯片。通过将第2半导体芯片5搭载在配线基板2的第2面2b上，可缩短从控制器芯片或系统LSI芯片等第2半导体芯片5至配线基板2为止的配线长度，从而可应对半导体装置1的高速化。
作为间隔基板3，使用例如硅酮间隔件，但并不限定于此，也可使用通常的配线基板作为间隔基板3。间隔基板3为了如上述那样确保第2半导体芯片5的安装空间，将第1半导体芯片4的位置升高来使之向上方移动。实施方式的半导体装置1中，在该间隔基板3的内部设置有电源导体层7与接地导体层8。进而，间隔基板3具有多个电极焊垫17，在其内部设置有多个通孔18。电源导体层7经由至少一个通孔18而与至少一个电极焊垫17连接，进而电极焊垫17以导线19与配线基板2的内部电极10的电源电极连接。接地导体层8经由其他通孔18而与其他电极焊垫17连接，进而电极焊垫17以导线19与配线基板2的内部电极10的接地电极连接。电源导体层7及接地导体层8分别在间隔基板3内设置有多个。
第1半导体芯片4A、4B的多个电极焊垫12A、12B中，电源焊垫在它们之间以导线13连接，进而以导线20与和间隔基板3的电源导体层7连接的电极焊垫17连接。第1半导体芯片4A、4B的多个电极焊垫12A、12B中，接地焊垫在它们之间以导线13连接，进而以导线20与和间隔基板3的接地导体层8连接的电极焊垫17连接。即，设置在第1半导体芯片4内的电源层，与间隔基板3的电源导体层7连接，进而与配线基板2的电源电极连接。设置在第1半导体芯片4内的接地层，与间隔基板3的接地导体层8连接，进而与配线基板2的接地电极连接。
如此，通过将第1半导体芯片4的电源层(未图示)与间隔基板3的电源导体层7电连接，并且将第1半导体芯片4的接地层(未图示)与间隔基板3的接地导体层8电连接，可在间隔基板3的电源导体层7与接地导体层8之间增加电容。电源导体层7与接地导体层8之间的距离，虽受间隔基板3的厚度的限制，但可设定为所需的距离，可增加电源-接地间的电容。进而，可缩短第1半导体芯片4的电源层及接地层与电源导体层7及接地导体层8的距离。因此，即便在第1半导体芯片4A、4B高频化的情况下，仍可降低高频的电源-接地间的阻抗。
阻抗Z相对于频率f、电感L及容量C以下式表示。
[数1]
|z|＝|2πfL-(1/2πfC)|如上所述，即便在频率f高频化的情况下，仍可使容量C增加，并且可使电感L减少，由此可使阻抗Z变小。电感L在其他条件相同的情况下，一般是配线距离越长则变得越大，因此需要尽量缩短配线。通过使阻抗Z变小，可抑制电源-接地间的电压变动噪声。由此，随着半导体装置1的高速化，即便在电源-接地间的阻抗高频化的情况下，仍可增加电源-接地间的电容而降低阻抗，由此可抑制电源-接地间的电压变动噪声。因此，可提高具备高速化及高频化的第1半导体芯片(存储器芯片)4的半导体装置1的动作特性或可靠性等，并且可抑制对外部设备的不良影响等。进而，通过增加电源-接地间的电容，可省去搭载芯片电容器，从而可实现半导体装置1的小型化或低成本化等。
(第2实施方式)图2是表示第2实施方式的半导体装置的构成的截面图。图2所示的半导体装置1具有搭载在配线基板2上的2个间隔基板3A、3B。在2个间隔基板3A、3B上，分别安装有2个第1半导体芯片4A(4A1、4A2)、4B(4B1、4B2)。间隔基板3A及安装在其上的第1半导体芯片4A1、4B1、与间隔基板3B及安装在其上的第1半导体芯片4A2，4B2，除在配线基板2上左右反转之外，具有相同构造，此外除它们之间的连接构造及与配线基板2的连接构造也左右反转之外，具有相同构造。
进而，间隔基板3A、3B、第1半导体芯片4A1、4B1、4A2、4B2及配线基板2的连接构造，除间隔基板3B及第1半导体芯片4A2、4B2的左右反转状态以外，与第1实施方式的连接构造相同，分别使用导线13、14、19、20连接。第2实施方式的半导体装置1，在配线基板2的2个间隔基板3A、3B间安装有第2半导体芯片5。即，在包含有阶梯状积层的第1半导体芯片4A1、4B1的从间隔基板3A突出的部分的下侧、及阶梯状积层的第1半导体芯片4A2、4B2的从间隔基板3B突出的部分的下侧的空间，配置第2半导体芯片5。2个间隔基板3A、3B分别具有电源导体层7A、7B及接地导体层8A、8B。
将上述间隔基板3A的电源导体层7A及接地导体层8A与设置在第1半导体芯片4A1、4B1的电源层及接地层连接，并且将间隔基板3B的电源导体层7B及接地导体层8B与设置在第1半导体芯片4A2、4B2内的电源层及接地层连接，由此可增加各个电源-接地间的电容，进而可缩短第1半导体芯片4A1、4B1、4A2、4B2的电源层及接地层与电源导体层7A、7B及接地导体层8A、8B的距离。因此，即便在第1半导体芯片4A1、4B1、4A2、4B2高频化的情况下，仍可降低高频的电源-接地间的阻抗。由此，可抑制电源-接地间的电压变动噪声。因此，可提高具备高速化及高频化的第1半导体芯片(存储器芯片)4的半导体装置1的动作特性或可靠性等，并且可抑制对外部设备的不良影响等。
(第3实施方式)图3是表示第3实施方式的半导体装置的构成的截面图。图3所示的半导体装置1，在将间隔基板3搭载在配线基板2上的接着层21内配置第2半导体芯片5。即，第3实施方式的半导体装置1应用薄膜上芯片构造，将间隔基板3隔着接着层21搭载在配线基板2上，并且将第2半导体芯片5埋入接着层21内。第3实施方式的半导体装置1，除将第2半导体芯片5埋入接着层21内的构造以外，具有与第1实施方式的半导体装置1相同的构成及连接构造等。
即，通过将间隔基板3的电源导体层7及接地导体层8与设置在第1半导体芯片4A、4B内的电源层及接地层连接，而增加电源-接地间的电容。进而，缩短第1半导体芯片4A、4B的电源层及接地层与电源导体层7及接地导体层8的距离。因此，即便在第1半导体芯片4A、4B高频化的情况下，仍可降低高频的电源-接地间的阻抗。由此，可抑制电源-接地间的电压变动噪声。因此，可提高具备高速化及高频化的第1半导体芯片(存储器芯片)4的半导体装置1的动作特性或可靠性等，并且可抑制对外部设备的不良影响等。
另外，上述各实施方式的构成可分别组合应用，此外也可置换一部分。此处，对本发明的几个实施方式进行了说明，但这些实施方式是作为例子提示的，并未意图限定发明的范围。这些新的实施方式能以其他各种方式实施，可在不脱离发明的要旨的范围，进行各种省略、替换、变更等。这些实施方式或其变化包含在发明的范围或要旨中，同时也包含在权利要求书中所记载的发明及其均等的范围。

Claims (5)

1.一种半导体装置，具备：配线基板；间隔基板，其搭载在所述配线基板上，且内设有电源导体层与接地导体层；至少一个第1半导体芯片，其等安装在所述间隔基板上，具有与所述电源导体层电连接的电源层及与所述接地导体层电连接的接地层；及第2半导体芯片，其安装在所述配线基板上。
2.根据权利要求1所述的半导体装置，其中在所述间隔基板上，积层安装有多个所述第1半导体芯片。
3.根据权利要求1或2所述的半导体装置，其中所述间隔基板具有与所述电源导体层电连接的电源焊垫、及与所述接地导体层电连接的电源焊垫，所述第1半导体芯片具有经由导线与所述间隔基板的所述电源焊垫电连接的电极焊垫、及经由导线与所述间隔基板的所述接地焊垫电连接的电极焊垫。
4.根据权利要求1至3中任一项所述的半导体装置，其中所述第2半导体芯片的至少一部分，位于从所述间隔基板突出的所述第1半导体芯片的一部分的下方。
5.根据权利要求1至3中任一项所述的半导体装置，其中所述第2半导体芯片埋入将所述间隔基板搭载在所述配线基板上的接着层内。
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