CN110504297A - Two-dimensional material transistor, fabrication method and application based on two-dimensional electron gas control back gate - Google Patents
Two-dimensional material transistor, fabrication method and application based on two-dimensional electron gas control back gate Download PDFInfo
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Abstract
Description
技术领域technical field
本发明特别涉及一种基于二维电子气调控背栅的二维材料晶体管、制法和应用，属于半导体电子器件技术领域。The invention particularly relates to a two-dimensional material transistor based on a two-dimensional electron gas control back gate, a manufacturing method and an application, and belongs to the technical field of semiconductor electronic devices.
背景技术Background technique
石墨烯等二维材料的出现和成功制备为各领域的发展注入了新的活力，二维材料种类包括金属、半导体及绝缘体，其中，具有半导体特性的二维材料在微电子器件方面有着广阔的应用前景。但受到二维材料本身材料的限制，并不适合制作高功率和高耐压器件。并且由于缺乏有效的性能表征手段，二维材料的发展受到了极大的限制。The emergence and successful preparation of two-dimensional materials such as graphene have injected new vitality into the development of various fields. The types of two-dimensional materials include metals, semiconductors and insulators. Among them, two-dimensional materials with semiconducting properties have broad application in microelectronic devices. application prospects. However, due to the limitation of the two-dimensional material itself, it is not suitable for making high-power and high-voltage devices. And due to the lack of effective performance characterization methods, the development of 2D materials has been greatly limited.
现有的二维材料场效应晶体管多利用二维材料作为沟道层制备场效应晶体管，其结构如图1所示，其自下而上依次有导电基底、绝缘介质层、二维材料、金属电极。该方法简化了二维材料场效应晶体管的制备工艺、提高制备效率和成品率。Existing two-dimensional material field effect transistors mostly use two-dimensional materials as the channel layer to prepare field effect transistors. electrode. The method simplifies the preparation process of the two-dimensional material field effect transistor, and improves the preparation efficiency and yield.
例如，CN107068745A公开了一种场效应晶体管的制备方法，其将两种不同的二维晶体组成异质结结构，利用该异质结结构作为导电沟道材料制备场效应晶体管，该器件适用于集成电路等领域；CN104078501A中公开了基于二维半导体材料的低压场效应晶体管，其包括：栅区、源区、漏区、沟道区和衬底。其栅介质为对电子绝缘、对离子导电的无机多孔材料，同时含有正、负两种离子。栅介质与沟道区的界面形成双电层电容，使得器件工作电压大大减低，同时采用少层二维半导体材料作为沟道区材料，使得器件可以同时实现电子导电和空穴导电。For example, CN107068745A discloses a method for preparing a field effect transistor. Two different two-dimensional crystals are formed into a heterojunction structure, and the heterojunction structure is used as a conductive channel material to prepare a field effect transistor. The device is suitable for integrated Circuits and other fields; CN104078501A discloses a low-voltage field effect transistor based on a two-dimensional semiconductor material, which includes a gate region, a source region, a drain region, a channel region and a substrate. The gate dielectric is an inorganic porous material that is insulating to electrons and conductive to ions, and contains both positive and negative ions. The interface between the gate dielectric and the channel region forms an electric double-layer capacitor, which greatly reduces the operating voltage of the device. At the same time, a few-layer two-dimensional semiconductor material is used as the channel region material, so that the device can realize both electron conduction and hole conduction.
然而，现有技术多采用导电基底作为背栅，与其他器件的集成度差，而且具有较大的寄生电容，以及实验可重复性差，工艺复杂，操作难度大，无法批量制备；并且现有晶体管对栅介质材料要求苛刻，难以达到理想的效果。因此，提供一种可调制背栅的二维材料晶体管仍是业界亟待解决的问题。However, the existing technology mostly uses a conductive substrate as the back gate, which has poor integration with other devices, large parasitic capacitance, poor experimental repeatability, complex process, and difficult operation, and cannot be fabricated in batches; and the existing transistors Strict requirements on gate dielectric materials make it difficult to achieve ideal results. Therefore, it is still an urgent problem to be solved in the industry to provide a two-dimensional material transistor with a tunable back gate.
发明内容SUMMARY OF THE INVENTION
本发明的主要目的在于提供一种基于二维电子气调控背栅的二维材料晶体管、制法和应用，以克服现有技术的不足。The main purpose of the present invention is to provide a two-dimensional material transistor based on a two-dimensional electron gas control back gate, a manufacturing method and an application, so as to overcome the deficiencies of the prior art.
为实现前述发明目的，本发明采用的技术方案包括：In order to realize the foregoing invention purpose, the technical scheme adopted in the present invention includes:
本发明实施例提方面提供了一种基于二维电子气调控背栅的二维材料晶体管，其包括：The embodiment of the present invention provides a two-dimensional material transistor based on a two-dimensional electron gas control back gate, which includes:
异质结，其包括第一半导体和形成于第一半导体上的第二半导体，所述第二半导体具有宽于第一半导体的带隙，且所述异质结中形成有二维电子气或二维空穴气；以及A heterojunction comprising a first semiconductor and a second semiconductor formed on the first semiconductor, the second semiconductor having a wider band gap than the first semiconductor, and a two-dimensional electron gas or two-dimensional hole gas; and
形成于所述异质结上的源极、漏极和栅极，所述源极、漏极分布在第二半导体上且彼此间隔设置，同时，所述源极与漏极之间经二维材料电连接，所述二维材料用作所述晶体管的导通沟道，所述栅极与所述二维电子气或二维空穴气电连接。A source electrode, a drain electrode and a gate electrode are formed on the heterojunction, the source electrode and the drain electrode are distributed on the second semiconductor and are spaced apart from each other. The material is electrically connected, the two-dimensional material is used as the conduction channel of the transistor, and the gate is electrically connected to the two-dimensional electron gas or the two-dimensional hole gas.
在一些实施方案中，还可在第二半导体上设置绝缘介质层，并将所述源极、漏极设置在绝缘介质层上。In some embodiments, an insulating dielectric layer may also be provided on the second semiconductor, and the source and drain electrodes may be provided on the insulating dielectric layer.
本发明实施例还提供了一种基于二维电子气调控背栅的二维材料晶体管的制作方法，其包括：The embodiment of the present invention also provides a method for fabricating a two-dimensional material transistor based on a two-dimensional electron gas control back gate, comprising:
提供异质结，所述异质结包含第一半导体和第二半导体，所述第二半导体形成在第一半导体上，且具有宽于所述第一半导体的带隙，所述异质结中形成有二维电子气或二维空穴气；providing a heterojunction comprising a first semiconductor and a second semiconductor, the second semiconductor formed on the first semiconductor and having a wider band gap than the first semiconductor, the heterojunction in A two-dimensional electron gas or two-dimensional hole gas is formed;
于所述异质结上制作栅极，并使所述栅极与所述二维电子气或二维空穴气电连接；forming a gate on the heterojunction, and electrically connecting the gate with the two-dimensional electron gas or two-dimensional hole gas;
于所述第二半导体上制作彼此间隔设置的源极和漏极；forming a source electrode and a drain electrode spaced apart from each other on the second semiconductor;
在所述源极和漏极之间设置二维材料，所述二维材料用作所述晶体管的导通沟道。A two-dimensional material is disposed between the source and drain, and the two-dimensional material serves as the conduction channel of the transistor.
本发明实施例还提供了所述基于二维电子气调控背栅的二维材料晶体管于制备二维材料传感装置或探测装置中的用途。The embodiment of the present invention also provides the use of the two-dimensional material transistor based on the two-dimensional electron gas control back gate in preparing a two-dimensional material sensing device or a detection device.
本发明实施例还提供了一种二维材料的特性变化检测方法，其包括：The embodiment of the present invention also provides a method for detecting a characteristic change of a two-dimensional material, which includes:
依据所述基于二维电子气调控背栅的二维材料晶体管的制作方法制作形成二维材料晶体管；A two-dimensional material transistor is fabricated and formed according to the method for fabricating a two-dimensional material transistor based on a two-dimensional electron gas control back gate;
在所述二维材料晶体管上加载电压或通入电流，测出其中二维材料的转移输出特性；Loading a voltage or passing a current on the two-dimensional material transistor, and measuring the transfer output characteristics of the two-dimensional material;
对所述二维材料晶体管中的二维材料进行特性变化处理，之后再次在所述二维材料晶体管上加载电压或通入电流，再次测得二维材料的转移输出特性，实现对二维材料的特性变化检测。The characteristic change processing is performed on the two-dimensional material in the two-dimensional material transistor, and then a voltage or current is applied to the two-dimensional material transistor again, and the transfer output characteristics of the two-dimensional material are measured again, so as to realize the transformation of the two-dimensional material. characteristic change detection.
与现有技术相比，本发明的优点包括：Compared with the prior art, the advantages of the present invention include:
(1)本发明实施例利用二维电子气的电子高迁移率特性，实现了可调制背栅的二维材料晶体管，由于采用二维材料作为沟道不需要对器件进行掺杂或离子注入，避免了因掺杂或离子注入工艺引入的均匀性、重复性和引入损伤问题，并且保证了与栅电极相连的二维电子气的高电子迁移率，降低了器件的导通损耗。此外，由于器件的整体结构生长得到简化，减少了刻蚀工艺，所以可以有效降低器件复杂性和制备成本；(1) The embodiment of the present invention utilizes the high electron mobility characteristics of the two-dimensional electron gas to realize a two-dimensional material transistor with a modulated back gate. Since the two-dimensional material is used as the channel, the device does not need to be doped or ion implanted. The problems of uniformity, repeatability and damage introduced by the doping or ion implantation process are avoided, the high electron mobility of the two-dimensional electron gas connected to the gate electrode is ensured, and the conduction loss of the device is reduced. In addition, since the overall structure growth of the device is simplified and the etching process is reduced, the device complexity and fabrication cost can be effectively reduced;
(2)由于本发明实施例的二维材料晶体管使用二维电子气作为背栅，可以更加灵敏的测试出二维材料的特性变化，适用于各类二维材料传感器及探测器，如光敏传感器、气敏传感器、光电探测器；也可适用于二维材料掺杂特性的研究。(2) Since the two-dimensional material transistor of the embodiment of the present invention uses two-dimensional electron gas as the back gate, the characteristic change of the two-dimensional material can be tested more sensitively, and it is suitable for various two-dimensional material sensors and detectors, such as photosensitive sensors , gas sensors, photodetectors; it can also be applied to the study of doping characteristics of two-dimensional materials.
附图说明Description of drawings
图1是现有技术中利用二维材料作为沟道层制备形成的场效应晶体管的结构示意图；1 is a schematic structural diagram of a field effect transistor prepared by utilizing a two-dimensional material as a channel layer in the prior art;
图2是本发明实施例1步骤1)中形成的材料结构示意图；2 is a schematic diagram of the material structure formed in step 1) of Example 1 of the present invention;
图3是本发明实施例1步骤2)中形成栅电极后的器件结构示意图；3 is a schematic diagram of the device structure after the gate electrode is formed in step 2) of Embodiment 1 of the present invention;
图4是本发明实施例1步骤3)中形成源电极和漏电极后的器件结构示意图；4 is a schematic diagram of the device structure after the source electrode and the drain electrode are formed in step 3) of Embodiment 1 of the present invention;
图5是本发明实施例1步骤4)中覆盖二维材料后的器件结构示意图；5 is a schematic diagram of the device structure after covering with two-dimensional material in step 4) of Example 1 of the present invention;
图6是本发明实施例1步骤5)中最终形成的一种基于二维电子气调控背栅的二维材料晶体管的器件结构示意图；6 is a schematic diagram of the device structure of a two-dimensional material transistor based on a two-dimensional electron gas control back gate finally formed in step 5) of Embodiment 1 of the present invention;
图7是本发明实施例2中一种基于二维电子气调控背栅的二维材料晶体管的器件又一结构示意图；7 is another structural schematic diagram of a device of a two-dimensional material transistor based on a two-dimensional electron gas control back gate in Embodiment 2 of the present invention;
图8是本发明实施例1中一种石墨烯晶体管的转移特性曲线；Fig. 8 is the transfer characteristic curve of a kind of graphene transistor in the embodiment of the present invention 1;
图9是本发明实施例1中一种石墨烯晶体管的输出特性曲线。FIG. 9 is an output characteristic curve of a graphene transistor in Embodiment 1 of the present invention.
具体实施方式Detailed ways
鉴于现有技术中的不足，本案发明人经长期研究和大量实践，得以提出本发明的技术方案。如下将对该技术方案、其实施过程及原理等作进一步的解释说明。In view of the deficiencies in the prior art, the inventor of the present application was able to propose the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.
本发明实施例一方面提供了一种基于二维电子气调控背栅的二维材料晶体管，其包括：One aspect of the embodiments of the present invention provides a two-dimensional material transistor based on a two-dimensional electron gas control back gate, which includes:
异质结，其包括第一半导体和形成于第一半导体上的第二半导体，所述第二半导体具有宽于第一半导体的带隙，且所述异质结中形成有二维电子气或二维空穴气；以及A heterojunction comprising a first semiconductor and a second semiconductor formed on the first semiconductor, the second semiconductor having a wider band gap than the first semiconductor, and a two-dimensional electron gas or two-dimensional hole gas; and
形成于所述异质结上的源极、漏极和栅极，所述源极、漏极分布在第二半导体上且彼此间隔设置，同时，所述源极与漏极之间经二维材料电连接，所述二维材料用作所述晶体管的导通沟道，所述栅极与所述二维电子气或二维空穴气电连接。A source electrode, a drain electrode and a gate electrode are formed on the heterojunction, the source electrode and the drain electrode are distributed on the second semiconductor and are spaced apart from each other. The material is electrically connected, the two-dimensional material is used as the conduction channel of the transistor, and the gate is electrically connected to the two-dimensional electron gas or the two-dimensional hole gas.
前述二维电子气(2DEG)是指可以自由在二维方向移动，而在第三维上受到限制的自由电子。在调制掺杂异质结中二维电子气沿着平面方向运动的迁移率将非常高并且在极低温度下都不会复合消失，故又称这些电子为高迁移率二维电子气。电子迁移率是影响器件工作频率的重要因素，高迁移率二维电子气的应用成为当前的研究热点并具有非常大的应用优势。The aforementioned two-dimensional electron gas (2DEG) refers to free electrons that can move freely in two-dimensional directions but are restricted in the third dimension. The mobility of the two-dimensional electron gas moving along the plane direction in the modulated doped heterojunction will be very high and will not recombine and disappear at extremely low temperature, so these electrons are also called high-mobility two-dimensional electron gas. Electron mobility is an important factor affecting the operating frequency of devices. The application of high mobility two-dimensional electron gas has become a current research hotspot and has great application advantages.
进一步的，所述栅极与所述二维电子气或二维空穴气之间形成欧姆接触。Further, an ohmic contact is formed between the gate and the two-dimensional electron gas or two-dimensional hole gas.
本发明实施例提供的二维材料晶体管的栅电极与二维电子气相连，而二维电子气存在于势垒层下面，构成了背栅调控，制备工艺简单，集成度好。而且还可以保证与栅电极相连的二维电子气的高电子迁移率。The gate electrode of the two-dimensional material transistor provided by the embodiment of the present invention is connected with the two-dimensional electron gas, and the two-dimensional electron gas exists under the potential barrier layer, which constitutes the back gate control, the preparation process is simple, and the integration degree is good. Also, high electron mobility of the two-dimensional electron gas connected to the gate electrode can be ensured.
进一步的，所述第一半导体选自III-V族化合物。Further, the first semiconductor is selected from group III-V compounds.
优选的，所述第一半导体的材质包括GaN或GaAs，但不限于此。Preferably, the material of the first semiconductor includes GaN or GaAs, but is not limited thereto.
进一步的，第二半导体选自选自III-V族化合物。Further, the second semiconductor is selected from the group III-V compounds.
优选的，所述第二半导体的材质包括AlGaN或AlGaAs，但不限于此。Preferably, the material of the second semiconductor includes AlGaN or AlGaAs, but is not limited thereto.
进一步的，所述栅极的厚度为10-1000nm。Further, the thickness of the gate is 10-1000 nm.
优选的，所述栅极的材质包括Ti、Al、Ni、Au、Cr、Pt、Mo、Pd中的任意一种或两种以上的组合，例如可以选自如下的组：Ti/Al/Ni/Au、Ti/Al/Ti/Au、Ti/Al/Cr/Au、Ti/Al/Pt/Au、Ti/Al/Mo/Au、Ti/Al/Pd/Au，但不限于此。Preferably, the material of the gate includes any one or a combination of two or more of Ti, Al, Ni, Au, Cr, Pt, Mo, and Pd, for example, can be selected from the following group: Ti/Al/Ni /Au, Ti/Al/Ti/Au, Ti/Al/Cr/Au, Ti/Al/Pt/Au, Ti/Al/Mo/Au, Ti/Al/Pd/Au, but not limited thereto.
进一步的，所述源极和/或漏极的厚度为10-1000nm。Further, the thickness of the source electrode and/or the drain electrode is 10-1000 nm.
优选的，所述源极和/或漏极的材质包括Au、Cr、Pt、Ag中的任意一种或两种以上形成的合金，但不限于此。Preferably, the material of the source electrode and/or the drain electrode includes an alloy formed by any one or two or more of Au, Cr, Pt, and Ag, but is not limited thereto.
进一步的，所述二维材料的层数为1-100层。Further, the number of layers of the two-dimensional material is 1-100 layers.
更进一步的，所述二维材料为单一种类的二维材料或二维材料异质结。Further, the two-dimensional material is a single type of two-dimensional material or a two-dimensional material heterojunction.
优选的，所述二维材料包括石墨烯、MoS2、WS2中的任意一种或两种以上的组合，但不限于此。Preferably, the two-dimensional material includes any one or a combination of two or more of graphene, MoS 2 , and WS 2 , but is not limited thereto.
在一些较为具体的实施方案中，所述异质结上还形成有绝缘介质层，所述源极、漏极设置于所述绝缘介质层上。In some specific implementations, an insulating dielectric layer is further formed on the heterojunction, and the source electrode and the drain electrode are disposed on the insulating dielectric layer.
优选的，所述绝缘介质层的厚度为1-1000nm。Preferably, the thickness of the insulating medium layer is 1-1000 nm.
优选的，所述绝缘介质层的材质包括SiO2、AlN、Si3N4中的任意一种或两种以上的组合，但不限于此。Preferably, the material of the insulating dielectric layer includes any one or a combination of two or more of SiO 2 , AlN, and Si 3 N 4 , but is not limited thereto.
在一些较为具体的实施方案中，所述异质结形成在基底上，并且所述异质结与基底之间还分布有缓冲层。In some specific embodiments, the heterojunction is formed on the substrate, and a buffer layer is further distributed between the heterojunction and the substrate.
本发明实施例另一方面还提供了一种基于二维电子气调控背栅的二维材料晶体管的制作方法，其包括：Another aspect of the embodiments of the present invention also provides a method for fabricating a two-dimensional material transistor based on a two-dimensional electron gas-regulated back gate, comprising:
提供异质结，所述异质结包含第一半导体和第二半导体，所述第二半导体形成在第一半导体上，且具有宽于所述第一半导体的带隙，所述异质结中形成有二维电子气或二维空穴气；providing a heterojunction comprising a first semiconductor and a second semiconductor, the second semiconductor formed on the first semiconductor and having a wider band gap than the first semiconductor, the heterojunction in A two-dimensional electron gas or two-dimensional hole gas is formed;
于所述异质结上制作栅极，并使所述栅极与所述二维电子气或二维空穴气电连接；forming a gate on the heterojunction, and electrically connecting the gate with the two-dimensional electron gas or two-dimensional hole gas;
于所述第二半导体上制作彼此间隔设置的源极和漏极；forming a source electrode and a drain electrode spaced apart from each other on the second semiconductor;
在所述源极和漏极之间设置二维材料，所述二维材料用作所述晶体管的导通沟道。A two-dimensional material is disposed between the source and drain, and the two-dimensional material serves as the conduction channel of the transistor.
本发明实施例提供的二维材料晶体管的制备方法中，由于不需要对器件进行掺杂或离子注入，避免了因掺杂或离子注入工艺引入的均匀性、重复性和引入损伤问题。In the preparation method of the two-dimensional material transistor provided by the embodiment of the present invention, since doping or ion implantation of the device is not required, the problems of uniformity, repeatability and introduced damage caused by the doping or ion implantation process are avoided.
进一步的，所述基于二维电子气调控背栅的二维材料晶体管的制备方法具体包括：于所述异质结上制作完成栅极之后，对形成的器件结构进行快速退火，退火温度为500-1000℃，时间为0.1-100min，使所述栅极与所述二维电子气或二维空穴气之间形成欧姆接触。Further, the preparation method of the two-dimensional material transistor based on the two-dimensional electron gas control back gate specifically includes: after the gate is formed on the heterojunction, the formed device structure is rapidly annealed, and the annealing temperature is 500 °C. -1000° C. for 0.1-100 min to form an ohmic contact between the gate electrode and the two-dimensional electron gas or two-dimensional hole gas.
进一步的，所述基于二维电子气调控背栅的二维材料晶体管的制备方法具体包括：先于所述第二半导体上形成绝缘介质层，之后在所述绝缘介质层上制作形成所述源极、漏极。Further, the preparation method of the two-dimensional material transistor based on the two-dimensional electron gas control back gate specifically includes: forming an insulating dielectric layer on the second semiconductor first, and then fabricating and forming the source on the insulating dielectric layer. pole, drain.
更进一步的，所述基于二维电子气调控背栅的二维材料晶体管的制备方法具体包括：Further, the preparation method of the two-dimensional material transistor based on the two-dimensional electron gas control back gate specifically includes:
将二维材料转移至源极和漏极之间，并使源极与漏极经二维材料电连接；transferring the two-dimensional material between the source electrode and the drain electrode, and electrically connecting the source electrode and the drain electrode through the two-dimensional material;
或者，在源极和漏极之间原位生长形成二维材料，并使源极与漏极经二维材料电连接。Alternatively, a two-dimensional material is formed in-situ between the source electrode and the drain electrode, and the source electrode and the drain electrode are electrically connected through the two-dimensional material.
进一步的，所述第一半导体选自III-V族化合物。例如，所述第一半导体的材质可以包括GaN或GaAs等，但不限于此。Further, the first semiconductor is selected from group III-V compounds. For example, the material of the first semiconductor may include GaN or GaAs, but is not limited thereto.
进一步的，第二半导体选自选自III-V族化合物。Further, the second semiconductor is selected from the group III-V compounds.
例如，所述第二半导体的材质可以包括AlGaN或AlGaAs等，但不限于此。For example, the material of the second semiconductor may include AlGaN or AlGaAs, but is not limited thereto.
进一步的，所述栅极的厚度为10-1000nm。Further, the thickness of the gate is 10-1000 nm.
优选的，所述栅极的材质包括Ti、Al、Ni、Au、Cr、Pt、Mo、Pd中的任意一种或两种以上的组合，例如可以选自如下的组：Ti/Al/Ni/Au、Ti/Al/Ti/Au、Ti/Al/Cr/Au、Ti/Al/Pt/Au、Ti/Al/Mo/Au、Ti/Al/Pd/Au，但不限于此。以其中的Ti/Al/Ni/Au为例，其是指依次层叠设置的Ti层、Al层、Ni层、Au层。Preferably, the material of the gate includes any one or a combination of two or more of Ti, Al, Ni, Au, Cr, Pt, Mo, and Pd, for example, can be selected from the following group: Ti/Al/Ni /Au, Ti/Al/Ti/Au, Ti/Al/Cr/Au, Ti/Al/Pt/Au, Ti/Al/Mo/Au, Ti/Al/Pd/Au, but not limited thereto. Taking Ti/Al/Ni/Au as an example, it refers to a Ti layer, an Al layer, a Ni layer, and an Au layer that are stacked in sequence.
进一步的，所述源极和/或漏极的厚度为10-1000nm。Further, the thickness of the source electrode and/or the drain electrode is 10-1000 nm.
优选的，所述源极和/或漏极的材质包括Au、Cr、Pt、Ag中的任意一种或两种以上形成的合金，但不限于此。Preferably, the material of the source electrode and/or the drain electrode includes an alloy formed by any one or two or more of Au, Cr, Pt, and Ag, but is not limited thereto.
进一步的，所述二维材料的层数为1-100层。Further, the number of layers of the two-dimensional material is 1-100 layers.
更进一步的，所述二维材料为单一种类的二维材料或二维材料异质结。Further, the two-dimensional material is a single type of two-dimensional material or a two-dimensional material heterojunction.
优选的，所述二维材料包括石墨烯、MoS2、WS2中的任意一种或两种以上的组合，但不限于此。Preferably, the two-dimensional material includes any one or a combination of two or more of graphene, MoS 2 , and WS 2 , but is not limited thereto.
在一些较为具体的实施方案中，还可以在所述异质结上设置绝缘介质层，并将所述源极、漏极设置于所述绝缘介质层上。In some specific embodiments, an insulating dielectric layer may also be provided on the heterojunction, and the source electrode and the drain electrode may be provided on the insulating dielectric layer.
优选的，所述绝缘介质层的厚度为1-1000nm。Preferably, the thickness of the insulating medium layer is 1-1000 nm.
优选的，所述绝缘介质层的材质包括SiO2、AlN、Si3N4中的任意一种或两种以上的组合，但不限于此。Preferably, the material of the insulating dielectric layer includes any one or a combination of two or more of SiO 2 , AlN, and Si 3 N 4 , but is not limited thereto.
本发明实施例提供的二维材料晶体管的制备方法中，由于器件的整体结构生长工艺得到简化，减少了刻蚀工艺，有效降低了器件的复杂性和制备成本。In the preparation method of the two-dimensional material transistor provided by the embodiment of the present invention, since the overall structure growth process of the device is simplified, the etching process is reduced, and the complexity and preparation cost of the device are effectively reduced.
本发明实施例还提供了所述基于二维电子气调控背栅的二维材料晶体管于制备二维材料传感装置或探测装置中的用途。The embodiment of the present invention also provides the use of the two-dimensional material transistor based on the two-dimensional electron gas control back gate in preparing a two-dimensional material sensing device or a detection device.
本发明实施例还提供了一种二维材料的特性变化检测方法，其包括：The embodiment of the present invention also provides a method for detecting a characteristic change of a two-dimensional material, which includes:
依据所述基于二维电子气调控背栅的二维材料晶体管的制作方法制作形成二维材料晶体管；A two-dimensional material transistor is fabricated and formed according to the method for fabricating a two-dimensional material transistor based on a two-dimensional electron gas control back gate;
在所述二维材料晶体管上加载电压或通入电流，测出其中二维材料的转移输出特性；Loading a voltage or passing a current on the two-dimensional material transistor, and measuring the transfer output characteristics of the two-dimensional material;
对所述二维材料晶体管中的二维材料进行特性变化处理，之后再次在所述二维材料晶体管上加载电压或通入电流，再次测得二维材料的转移输出特性，实现对二维材料的特性变化检测。The characteristic change processing is performed on the two-dimensional material in the two-dimensional material transistor, and then a voltage or current is applied to the two-dimensional material transistor again, and the transfer output characteristics of the two-dimensional material are measured again, so as to realize the transformation of the two-dimensional material. characteristic change detection.
进一步的，前述特性变化处理包括掺杂或等离子体处理等，但不限于此。Further, the aforementioned characteristic change treatment includes doping or plasma treatment, etc., but is not limited thereto.
例如，在一些实施例中，可以将所述二维材料晶体管中的二维材料与指定的化学物质、电磁波等接触，从而使其物理和/或化学特性发生变化。For example, in some embodiments, the two-dimensional material in the two-dimensional material transistor may be contacted with specified chemicals, electromagnetic waves, etc. to change its physical and/or chemical properties.
如下将结合附图与具体实施例对该技术方案、其实施过程及原理等作进一步的解释说明。The technical solution, its implementation process and principle will be further explained below with reference to the accompanying drawings and specific embodiments.
实施例1Example 1
该实施例提供的一种基于二维电子气调控背栅的二维材料晶体管的结构可以如图6所示，其可以包括于衬底上依次设置的缓冲层、沟道层(亦可称为第一半导体)、势垒层(亦可称为第二半导体)，所述势垒层上间隔设置有源极和漏极，源极与漏极之间经二维材料电连接，栅极与二维电子气电连接，该二维电子气形成于由沟道层和势垒层组成的异质结中。The structure of a two-dimensional material transistor based on a two-dimensional electron gas control back gate provided by this embodiment may be as shown in FIG. 6 , which may include a buffer layer and a channel layer (also referred to as a buffer layer and a channel layer (also referred to as A first semiconductor), a barrier layer (also called a second semiconductor), a source electrode and a drain electrode are arranged at intervals on the barrier layer, the source electrode and the drain electrode are electrically connected through a two-dimensional material, and the gate electrode and the drain electrode are electrically connected. The two-dimensional electron gas is electrically connected, and the two-dimensional electron gas is formed in a heterojunction consisting of a channel layer and a barrier layer.
该实施例提供的一种基于二维电子气调控背栅的二维材料晶体管的制备方法可以包括如下步骤：The preparation method of a two-dimensional material transistor based on a two-dimensional electron gas control back gate provided by this embodiment may include the following steps:
1)利用金属有机化合物化学气相沉积(MOCVD)或分子束外延(MBE)或氢化物气相外延(HVPE)等外延技术，生长基底/缓冲层/沟道层/势垒层的材料结构，其结构如图2所示；基底可以是硅片、蓝宝石等，沟道层的材质包括GaN或GaAs，势垒层的材质包括AlGaN或AlGaAs，在沟道层和势垒层之间形成有二维电子气或二维空穴气；势垒层的导电性较差，如AlGaN的电导率为10Ω/m或10Ω/m以上；1) Use metal organic compound chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE) and other epitaxy techniques to grow the material structure of the substrate/buffer layer/channel layer/barrier layer, and its structure As shown in Figure 2; the substrate can be silicon wafer, sapphire, etc., the material of the channel layer includes GaN or GaAs, the material of the barrier layer includes AlGaN or AlGaAs, and two-dimensional electrons are formed between the channel layer and the barrier layer gas or two-dimensional hole gas; the conductivity of the barrier layer is poor, such as the conductivity of AlGaN is 10Ω/m or more;
2)利用电子束蒸发或溅射等金属沉积技术，在步骤1)中的材料结构表面上制作栅电极，并用快速退火炉退火，退火温度为500-1000℃，时间为0.1-100min，使栅电极与步骤1)中的材料结构表面形成欧姆接触，且栅电极与二维电子气或二维空穴气电连接，制作形成栅电极后的器件结构如图3所示；栅电极的厚度为10-1000nm，栅电极的材质包括Ti/Al/Ni/Au、Ti/Al/Ti/Au、Ti/Al/Cr/Au、Ti/Al/Pt/Au、Ti/Al/Mo/Au、Ti/Al/Pd/Au中的任意一种；2) Using metal deposition techniques such as electron beam evaporation or sputtering, a gate electrode is fabricated on the surface of the material structure in step 1), and annealed in a rapid annealing furnace. The electrode forms ohmic contact with the surface of the material structure in step 1), and the gate electrode is electrically connected to the two-dimensional electron gas or two-dimensional hole gas. The device structure after the gate electrode is formed is shown in Figure 3; the thickness of the gate electrode is 10-1000nm, the material of gate electrode includes Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti/Al/Cr/Au, Ti/Al/Pt/Au, Ti/Al/Mo/Au, Ti Any of /Al/Pd/Au;
3)利用电子束蒸发或溅射等金属沉积技术，在步骤2)中的器件结构表面上制作源电极和漏电极，制作形成源电极、漏电极后的器件结构如图4所示；源电极和漏电极的厚度均为10-1000nm；源电极和漏电极的材质均包括Au、Cr、Pt、Ag中的任意一种金属或其他导电性良好的金属及其合金；3) Using metal deposition techniques such as electron beam evaporation or sputtering, a source electrode and a drain electrode are fabricated on the surface of the device structure in step 2), and the device structure after the source electrode and the drain electrode are fabricated is as shown in Figure 4; the source electrode The thickness of the drain electrode and the source electrode are both 10-1000nm; the material of the source electrode and the drain electrode includes any one of Au, Cr, Pt, Ag or other metals with good conductivity and their alloys;
4)利用机械剥离、化学气相沉积(CVD)等方法生长二维材料(如石墨烯、二硫化钼等)并转移到步骤3)中制作形成源电极、漏电极后的器件结构表面或者直接在步骤3)中制作形成源电极、漏电极后的器件结构表面生长二维材料，生长二维材料后的器件结构如图5所示；优选的，二维材料的层数为1-100层；二维材料包括单一种类的二维材料或由两种以上二维材料形成的二维材料异质结；优选的，二维材料包括石墨烯、MoS2、WS2中的任意一种，例如石墨烯/MoS2、石墨烯/WS2；4) Use mechanical exfoliation, chemical vapor deposition (CVD) and other methods to grow two-dimensional materials (such as graphene, molybdenum disulfide, etc.) and transfer them to step 3) to fabricate the surface of the device structure after the source electrode and drain electrode are formed or directly on the surface. In step 3), two-dimensional material is grown on the surface of the device structure after the source electrode and the drain electrode are formed, and the device structure after growing the two-dimensional material is shown in Figure 5; preferably, the number of layers of the two-dimensional material is 1-100 layers; The two-dimensional material includes a single type of two-dimensional material or a two-dimensional material heterojunction formed by two or more two-dimensional materials; preferably, the two-dimensional material includes any one of graphene, MoS 2 , and WS 2 , such as graphite Graphene/MoS 2 , graphene/WS 2 ;
5)利用氧等离子体或反应离子刻蚀或离子束刻蚀等刻蚀技术，刻蚀掉除源电极和漏电极之间区域以外区域的二维材料，使二维材料与源电极、漏电极形成欧姆接触；刻蚀区域可以通过光刻和掩膜转移等技术进行确定，最终形成的器件结构如图6所示。5) Use oxygen plasma or reactive ion etching or ion beam etching and other etching techniques to etch away the two-dimensional material except the area between the source electrode and the drain electrode, so that the two-dimensional material is connected to the source electrode and the drain electrode. An ohmic contact is formed; the etched area can be determined by techniques such as photolithography and mask transfer, and the final device structure is shown in Figure 6.
进一步的，本实施例还可利用半导体参数仪对制备形成的前述二维材料晶体管进行测试，获得二维材料的转移输出特性，研究器件的性能。Further, in this embodiment, a semiconductor parameter meter can also be used to test the prepared and formed two-dimensional material transistor, to obtain the transfer output characteristics of the two-dimensional material, and to study the performance of the device.
进一步的，本实施例还可对前述二维材料晶体管表面的二维材料进行掺杂或等离子体处理，再利用半导体参数仪进行测试，测出二维材料的转移输出特性，研究分析器件特性的变化。Further, in this embodiment, the two-dimensional material on the surface of the aforementioned two-dimensional material transistor can be doped or plasma treated, and then tested by a semiconductor parameter meter to measure the transfer output characteristics of the two-dimensional material, and study and analyze the characteristics of the device. Variety.
例如，以本实施例所获的一种石墨烯晶体管为例，采用半导体参数仪对该石墨烯晶体管进行测试，在源极、漏极间施加一固定电压Vds，栅极施加变化的电压Vg，测出器件源极、漏极间电流Ids随栅极电压Vg变化的曲线即转移特性曲线，转移特性曲线如图8所示；在栅极施加一固定电压Vg，源极、漏极间施加变化的电压Vds，测出源极、漏极间电流Ids随漏极电压Vds变化的曲线即输出特性曲线，输出特性曲线如图9所示。For example, taking a graphene transistor obtained in this embodiment as an example, a semiconductor parameter meter is used to test the graphene transistor, a fixed voltage Vds is applied between the source and the drain, and a varying voltage Vg is applied to the gate, The curve of the current Ids between the source and the drain of the device as a function of the gate voltage Vg is measured, that is, the transfer characteristic curve. The transfer characteristic curve is shown in Figure 8; a fixed voltage Vg is applied to the gate, and a change is applied between the source and the drain. The voltage Vds between the source and the drain is measured, and the curve that the current Ids between the source and the drain changes with the drain voltage Vds is the output characteristic curve. The output characteristic curve is shown in Figure 9.
实施例2：该实施例提供的一种基于二维电子气调控背栅的二维材料晶体管的结构可以参阅图7所示，其与实施例1的二维材料晶体管的区别之处在于：势垒层上还设有绝缘介质层，源极、二维材料、漏极均设置在该绝缘介质层上。Example 2: The structure of a two-dimensional material transistor based on a two-dimensional electron gas control back gate provided in this example can be referred to as shown in FIG. 7 , which is different from the two-dimensional material transistor of Example 1 in that the potential An insulating medium layer is also arranged on the barrier layer, and the source electrode, the two-dimensional material and the drain electrode are all arranged on the insulating medium layer.
该实施例提供的二维材料晶体管的制备方法与实施例1基本相同，区别之处在于：步骤1)还包括在势垒层上形成绝缘介质层，并以反应离子刻蚀或湿法腐蚀等刻蚀方法刻蚀除去栅电极下方区域的绝缘介质层，之后再沉积栅极金属；或者步骤2)还包括在制作形成栅电极之后，以原子层沉积(ALD)或等离子增强化学气相沉积(PECVD)等方式在势垒层和栅电极上沉积一层绝缘介质层，然后除去栅电极上方的绝缘介质层。所述绝缘介质层的厚度可以为1-1000nm，绝缘介质层的材质包括SiO2、AlN、Si3N4中的任意一种或两种以上的组合。The preparation method of the two-dimensional material transistor provided in this embodiment is basically the same as that in Embodiment 1, except that step 1) further includes forming an insulating dielectric layer on the barrier layer, and performing reactive ion etching or wet etching, etc. The insulating dielectric layer in the area below the gate electrode is etched and removed by the etching method, and then the gate metal is deposited; or step 2) also includes, after the gate electrode is formed, using atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD) ) and other methods to deposit an insulating dielectric layer on the barrier layer and the gate electrode, and then remove the insulating dielectric layer above the gate electrode. The thickness of the insulating medium layer may be 1-1000 nm, and the material of the insulating medium layer includes any one or a combination of two or more of SiO 2 , AlN, and Si 3 N 4 .
应当理解，上述实施例仅为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。It should be understood that the above-mentioned embodiments are only intended to illustrate the technical concept and characteristics of the present invention, and the purpose thereof is to enable those who are familiar with the art to understand the content of the present invention and implement it accordingly, and cannot limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be included within the protection scope of the present invention.
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