CN110277052B - Full-color LED driver chip and driving method with multi-line scanning and high refresh rate - Google Patents

Abstract

The invention discloses a multi-row scanning high-refresh-rate full-color L ED driving chip and a driving method, belonging to the field of full-color L ED driving chip design, wherein the driving method comprises a synchronous controller, a shift register, a state register, an SRAM buffer, a gray scale clock generation module, a driving module, a pre-charging circuit and an analog output module, the gray scale clock generation module is used for carrying out frequency multiplication/frequency division processing on a data clock signal DC L K according to instruction information to generate a gray scale clock signal GC L K for controlling gray scale, the driving module is used for counting the gray scale clock signal GC L K to obtain gray scale counting corresponding to each row of pixel data, and generating output waveforms of PWM signals corresponding to each row of pixel data by using continuous N rows of pixel data and corresponding gray scale counting in each scanning process to realize multi-row scanning, and the analog output module is used for receiving the PWM signals and generating and driving L ED lamp beads by matching with the pre-charging circuit.

Description

Full-color LED driver chip and driving method with multi-line scanning and high refresh rate

technical field

The invention belongs to the field of full-color LED driving chip design, and more particularly relates to a full-color LED driving chip and a driving method with multi-line scanning and high refresh rate.

Background technique

LED (Light Emitting Diode) was born in the 1960s. After more than 50 years of development, the power consumption of LED is getting lower and lower, and the effective brightness is getting higher and higher. Due to the characteristics of cost, green environmental protection, etc., it is more and more widely used in traditional lighting display, aerospace and consumer products. Thanks to the advantages of LED's good spatial scalability, consistency, and seamless splicing, LED screens have excellent performance in the field of internal and external large-screen displays, and as the size of LED lamp beads continues to decrease, the pixel density of LED screens continues to increase Increase, it can be predicted that LED screen will become the mainstream product in the field of large-screen display inside and outside. With the development of high-definition video technology, the market has higher requirements for the gray level, visual refresh rate and pixel density of LED screens. Under this trend, LED display control chips are also moving towards high gray level control and high visual refresh rate. Development in the direction of high rate and high line scanning.

The traditional general-purpose LED display control chip adopts an external PWM method to perform binary pulse width modulation by bit, and its complete grayscale display time has an exponential relationship with the grayscale level. In practical applications, in order to ensure that the currents output by all channels have good linearity, the minimum OE width (ie, the PWM output time corresponding to the lowest weight bit) cannot be infinitely reduced. In the display process of one frame time, under the condition of high grayscale display, even if the high and low weight bits are used to disperse display and gating enable, the visual refresh rate does not exceed several hundred hertz.

The dedicated LED display control chip adopts built-in PWM pulse width processing, completes the ping-pong operation of pixel grayscale data reading and writing through the built-in SRAM, and adopts pipeline design and distributed pulse width processing (SPWM) for grayscale, visual refresh rate, line scan ability enhancement. In order to ensure that the LED has a good line gray level, when the SPWM divides the sub-cycle, the number of gray clocks (GCLK) in a single sub-cycle cannot be too small, and due to the limitation of the PCB wiring frequency of the LED screen, its one frame time The total number of GCLKs is limited, while in the traditional LED driver chip, the grayscale clock signal is provided by the off-chip signal through the pin, so the visual refresh rate and the line scanning capability are mutually restricted under the condition of satisfying high grayscale display. , high visual refresh rate and multi-line scanning cannot be achieved at the same time in practical applications.

SUMMARY OF THE INVENTION

In view of the defects and improvement requirements of the prior art, the present invention provides a full-color LED driving chip and a driving method with multi-line scanning and high refresh rate, the purpose of which is to improve the refresh rate and support more scanning lines.

In order to achieve the above purpose, according to the first aspect of the present invention, a full-color LED driver chip with multi-line scanning and high refresh rate is provided, including: a synchronization controller, a shift register, a status register, an SRAM buffer, a grayscale clock Generating module, driving module, pre-charging circuit and analog output module;

The synchronization controller, whose first input terminal is used to receive the latch signal LE, and the latch signal LE is used to indicate the type of input data; the synchronization controller is used to transmit the latch signal LE to the shift register and the shift register through its first output terminal. status register;

The shift register, its first input terminal is used to receive serial input data SDI, its second input terminal is used to receive the data clock signal DCLK, its third input terminal is connected to the first output terminal of the synchronization controller, the data clock signal DCLK is used as the clock signal for sending instruction data and pixel data; the shift register is used to identify the instruction data and pixel data from the serial input data SDI according to the latch signal LE and transmit them to the status register and the SRAM buffer respectively;

The grayscale clock generation module, the first input terminal of which is used to receive the data clock signal DCLK, the second input terminal of which is connected to the status register, and the grayscale clock generation module is used for multiplying/dividing the data clock signal DCLK according to the instruction information. frequency processing to generate the gray clock signal GCLK, the gray clock signal is used to control the gray level;

The driving module, the first input terminal of which is connected to the output terminal of the grayscale clock generation module, and the second input terminal of which is connected to the SRAM buffer. The driving module is used to count the grayscale clock signal GCLK to obtain the grayscale corresponding to the pixel data of each row. Counting, and in each scanning process, the output waveform of the PWM signal corresponding to each line of pixel data is generated by using continuous N lines of pixel data and corresponding grayscale counts, thereby realizing multi-line scanning;

The synchronization controller is also used to generate a line feed/frame feed signal, and the line feed/frame feed signal is used to instruct the next line or next frame of pixels to be displayed; the input end of the precharge circuit is connected to the second output end of the synchronization controller; the analog The first input end of the output module is connected to the output end of the driving module, and the second input end of the analog output module is connected to the precharge circuit; The PWM signal of the pixel row is precharged to generate multi-channel driving current to realize constant current driving of the LED lamp bead.

The multi-line scanning high refresh rate full-color LED driving chip provided by the present invention performs frequency division/multiplication according to the data clock signal DCLK inside the chip to generate the grayscale clock signal GCLK. The grayscale clock signal is provided outside the chip. In the present invention, the grayscale clock signal GCLK can reach a higher frequency, and at the same time its frequency automatically tracks DCLK, the anti-interference ability is greatly improved, and the refresh rate and the scan line that can be supported are effectively improved. number.

Further, the grayscale clock generation module includes: a phase-locked loop, a frequency multiplying unit, a first frequency dividing unit and a second frequency dividing unit;

The first input end of the phase-locked loop is used as the first input end of the grayscale clock generation module, and the second input end of the phase-locked loop is connected to the output end of the frequency doubling unit; the first input end of the frequency doubling unit is used as the grayscale clock to generate The second input end of the module, the second input end of the frequency multiplication unit is connected to the output end of the phase-locked loop, and the frequency multiplication unit is used for frequency multiplication of the data clock signal DCLK according to the coefficient P, so as to obtain the frequency multiplied signal and phase-lock the signal. The loop outputs the frequency multiplied signal;

The input end of the first frequency dividing unit is connected to the output end of the phase-locked loop, and the first frequency dividing unit is used to divide the frequency multiplication signal according to the coefficient M ₁ to obtain the frequency division signal;

的灰度时钟信号GCLK；The input end of the second frequency dividing unit is connected to the output end of the first frequency dividing unit, and the _second frequency dividing unit is used to divide the frequency division signal according to the coefficient M

The grayscale clock signal GCLK;

Among them, P is a dynamically configurable frequency multiplication coefficient, M ₁ and M ₂ are dynamically configurable frequency division coefficients, and f _DCLK and f _GCLK are the frequencies of the data clock signal DCLK and the grayscale clock signal GCLK, respectively.

The present invention is composed of a phase-locked loop and three frequency division/multiplier units to generate a grayscale clock generation module, and generates a grayscale clock signal GCLK by dividing/multiplying the digital clock signal DCLK, wherein the frequency multiplication coefficient P, The frequency division coefficients M ₁ and M ₂ can be dynamically configured, which not only ensures that the generated grayscale clock signal GCLK can reach a higher frequency, but also ensures better brightness efficiency, and ensures that the display time is consistent with the frame interval. At the same time, the frequency division operation is completed in two times, which also reduces the storage requirements for the registers used to store the frequency division coefficients.

Further, three primary color data of R, G, and B are integrated into the pixel data, and in the process of processing the pixel data, the three primary color data of R, G, and B are processed synchronously.

The traditional LED driver chip is only responsible for driving the lamp beads of one primary color. In order to realize the driving of three primary colors, each lamp bead needs to be driven independently by three chips, which occupies a large PCB area; The three primary colors of R, G, and B are integrated in the medium, which can reduce the PCB area that needs to be occupied and increase the number of output channels, making it possible for the LED display to achieve a smaller lamp bead spacing.

Further, the second input terminal of the synchronization controller is used to receive the line feed signal ROW, the line feed signal ROW has different high-level widths, and the synchronization controller is used to generate the corresponding line feed/frame change signal according to the high level width of the line feed signal ROW. .

The traditional LED driver chip changes frames according to the field synchronization signal Vsync. When the field synchronization signal Vsync arrives, it often needs to wait for a period of time to start displaying the next frame, so there is a large frame interval and a low refresh rate; The line feed signal ROW is introduced into the pin, and a line feed/frame feed signal is generated according to the line feed signal ROW to indicate the start of scanning for the next frame or next line. The synchronization signal Vsync is irrelevant, so that a long waiting time can be avoided when changing frames, a frame interval removal technology is realized, and the refresh rate is improved.

Further, the multi-line scanning high refresh rate full-color LED driver chip provided by the present invention further includes: an error state detection module, the input end of which is connected to each output channel of the analog output module for detecting the LED lamp beads open/short state, and replace the pixel data of dead pixels with 0 to eliminate the cross phenomenon of dead pixels;

The dead point is the point where a short circuit occurs. If the dead point produces PWM output, it will cause a local high current, so that the cross highlight phenomenon centered on the dead point, that is, the dead point cross phenomenon; the present invention is detected by the error state detection module. The open/short state of the LED lamp bead, and the pixel data of the dead pixel is replaced with 0, which can avoid generating PWM output at the dead pixel, thereby eliminating the dead pixel cross phenomenon.

Further, the driving module includes: a counter, a butterfly breaking unit and a comparison unit;

The input end of the counter is used as the first input end of the driving module, and the counter is used to count the grayscale clock signal GCLK to obtain the grayscale count corresponding to the pixel data of each row;

The input end of the butterfly breaking unit is connected to the output end of the counter, and the butterfly breaking unit is used to divide the grayscale count into K gray scale blocks according to the data block mode and rearrange them by the way of butterfly breaking. , to obtain the block number sequence; each gray block corresponds to a gray clock count value, and the sum of the gray clock count values corresponding to all gray blocks is equal to the gray count;

The first input end of the comparison unit is used as the second input end of the driving module, the second input end of the comparison unit is connected to the output end of the butterfly breaking unit, and the comparison unit is used for dividing the pixel data into K pixels according to the block mode It is divided into blocks, and the corresponding numbered gray blocks and pixel blocks are compared in turn according to the block number sequence, thereby generating the output waveform of the PWM signal; each pixel block corresponds to a gray value, and all pixel blocks are The sum of the corresponding gray values is equal to the pixel data;

Among them, K is the number of blocks corresponding to the block mode.

The pixel value corresponding to a pixel block indicates the number of GCLK cycles that need to be turned on for the pixel block when displaying the pixel block. The larger the pixel value corresponding to the pixel block, the brighter the pixel block is when displayed; the traditional LED driver In the chip, when the PWM signal is generated, the grayscale clock signal GCLK is directly counted and compared with the pixel data to generate the output waveform of the PWM signal. When displayed, the first half is obviously brighter than the second half, so that the phenomenon of bright lines and bright spots appears; the present invention disperses the gray scale blocks by butterfly, and displays the pixel blocks according to the reordered number sequence, so that the brighter The darker pixel blocks and the darker pixel blocks are cross-displayed, so that the grayscale displayed on the screen is more uniform, the problem of bright lines and bright spots is avoided, and the picture quality is improved.

According to the second aspect of the present invention, a method for driving a full-color LED driver chip with a multi-line scan and high refresh rate provided by the first aspect of the present invention is provided, including:

(1) Count the grayscale clock signal GCLK to obtain the grayscale count corresponding to each row of pixel data;

(2) for any line of pixel data that needs to be displayed in the current scanning process, divide the line of pixel data into K pixel blocks according to the data block mode;

Each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all pixel blocks is equal to the pixel data;

(3) according to the data block mode, the grayscale count corresponding to the row pixel data is divided into K grayscale blocks and rearranged by the mode of butterfly breaking, to obtain the block number sequence;

Each grayscale block corresponds to a grayscale clock count value, and the sum of the grayscale clock count values corresponding to all grayscale blocks is equal to the grayscale count;

(4) according to the block number sequence, get the gray scale block and the pixel block of the corresponding number in turn and compare, thereby generating the output waveform of the PWM signal corresponding to the pixel data of this row;

(5) for consecutive N rows of pixel data, respectively perform steps (2) to (4) to obtain the output waveform of the PWM signal corresponding to each row of pixel data;

(6) Display the pixel data of consecutive N rows according to the result of the data segmentation and the generated PWM signal, so that the pixels of the same number in the pixel data of the 1st to Nth rows are displayed in sequence, and one of the pixel data of all N rows is displayed in sequence. After the numbered pixel blocks are all displayed, the next numbered pixel block in the block number sequence starts to be displayed;

Among them, K is the number of blocks corresponding to the block mode.

The driving method of the full-color LED provided by the present invention disperses the gray-scale blocks in a butterfly shape, and displays the pixel blocks according to the reordered number sequence, so that the brighter pixel blocks and the darker pixel blocks are divided into two groups. The blocks are displayed crosswise, so that the grayscale displayed on the screen is more uniform, the problem of bright lines and bright spots is avoided, and the picture quality is improved.

Further, the pixel value corresponding to the pixel block and the grayscale count value corresponding to the grayscale block are not less than L;

where L is an integer power of 2.

When the PWM signal corresponding to each pixel block is turned on, there is a level rise time, and such a level rise time restricts the improvement of the refresh rate; the present invention increases the minimum length of the data block (that is, the pixel corresponding to the pixel block). value or the grayscale count value corresponding to the grayscale block), which can effectively reduce the number of pixel blocks actually displayed, thereby reducing the total level rise time and achieving a higher refresh rate.

Further, when each row of pixel data is displayed, the corresponding PWM signal is turned on at the end of the entire PWM driving stage.

When the LED screen is refreshed, there will be a new line time. The line wrap time includes the line erasing discharge time of the previous line and the charging time of the new line. The PWM signal needs to have a pre-charge time before turning on. In the traditional LED driving method , when the PWM signal is turned on at the beginning of the entire PWM drive stage, the precharge can only be completed by using the line feed time, and the line feed time is not fixed, so it is possible that the precharge process cannot be completed normally because the line feed time is too short; the present invention By turning on the PWM signal at the end of the entire PWM driving stage, the line feed time and the first half of the PWM driving stage can be used for precharging, thereby ensuring a long enough precharging time to complete the precharging process and improving the response speed of the driving current.

In general, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

(1) The multi-line scanning high refresh rate full-color LED driver chip provided by the present invention performs frequency division/multiplication according to the data clock signal DCLK inside the chip to generate a grayscale clock signal GCLK, and the obtained grayscale clock signal GCLK A higher frequency can be achieved, and at the same time, its frequency automatically tracks DCLK, which greatly improves the anti-interference ability, effectively improving the refresh rate and the number of scan lines that can be supported.

(2) The multi-line scanning high refresh rate full-color LED driver chip provided by the present invention can reduce the PCB area required by integrating the three primary colors of R, G, and B in one driver chip, and improve the The number of output channels makes it possible for the LED display to achieve a smaller lamp bead spacing.

(3) The multi-line scanning high refresh rate full-color LED driver chip provided by the present invention introduces a line feed signal ROW through a pin, and generates a line feed/frame feed signal according to the line feed signal ROW to indicate the next frame or next line. At the beginning of scanning, even if the field synchronization signal Vsync arrives, the display can still continue, so that the frame change has nothing to do with the field synchronization signal Vsync, so that a long waiting time can be avoided when the frame is changed, and a frame interval removal technology is realized. Improved refresh rate.

(4) In the multi-line scanning high refresh rate full-color LED driver chip and driving method provided by the present invention, the present invention disperses the gray scale blocks by butterfly, and displays the pixel blocks according to the reordered number sequence. , so that the brighter pixel blocks and the darker pixel blocks are cross-displayed, so that the grayscale displayed on the screen is more uniform, the problem of bright lines and bright spots is avoided, and the picture quality is improved.

(5) The driving method provided by the present invention can effectively reduce the actual displayed pixels by increasing the minimum length of the data block (ie, the pixel value corresponding to the pixel block or the gray scale count value corresponding to the gray scale block). The number of blocks, thereby reducing the overall level rise time, enables higher refresh rates.

(6) In the driving method provided by the present invention, by turning on the PWM signal at the end of the entire PWM driving stage, the line feed time and the first half of the PWM driving stage can be used for pre-charging, thereby ensuring a long enough pre-charging time to complete the pre-charging. During the charging process, the response speed of the driving current is improved.

Description of drawings

1 is a schematic diagram of the internal architecture of a full-color LED driver chip with multi-line scanning and high refresh rate provided by an embodiment of the present invention;

Fig. 2 is the integrated R, G, B three primary color data and 48bit pixel data synchronous processing that the embodiment of the present invention provides and produces PWM data flow diagram respectively;

3 is a schematic diagram of a traditional PWM generation method;

4 is a schematic diagram of data division provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of displaying pixel data according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of the level rise time during the turn-on process of the existing PWM signal

7 is a schematic diagram of a traditional PWM signal on and a schematic diagram of a PWM signal provided by an embodiment of the present invention; wherein, (a) is a schematic diagram of a traditional PWM signal on, and (b) is a schematic diagram of the PWM signal provided by the embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

The multi-line scan high refresh rate full-color LED driver chip provided by the present invention, as shown in FIG. 1 , includes: a synchronization controller, a shift register, a status register, an SRAM buffer, a grayscale clock generation module, a driver module, Precharge circuit and analog output module;

The synchronization controller, whose first input terminal is used to receive the latch signal LE, and the latch signal LE is used to indicate the type of input data; the synchronization controller is used to transmit the latch signal LE to the shift register and the shift register through its first output terminal. status register;

The shift register, its first input terminal is used to receive serial input data SDI, its second input terminal is used to receive the data clock signal DCLK, its third input terminal is connected to the first output terminal of the synchronization controller, the data clock signal DCLK is used as the clock signal for sending instruction data and pixel data; the shift register is used to identify the instruction data and pixel data from the serial input data SDI according to the latch signal LE and transmit them to the status register and the SRAM buffer respectively;

The grayscale clock generation module, the first input terminal of which is used to receive the data clock signal DCLK, the second input terminal of which is connected to the status register, and the grayscale clock generation module is used for multiplying/dividing the data clock signal DCLK according to the instruction information. frequency processing to generate the gray clock signal GCLK, the gray clock signal is used to control the gray level;

The driving module, the first input terminal of which is connected to the output terminal of the grayscale clock generation module, and the second input terminal of which is connected to the SRAM buffer. The driving module is used to count the grayscale clock signal GCLK to obtain the grayscale corresponding to the pixel data of each row. The PWM signal corresponding to each row of pixel data is generated by using continuous N rows of pixel data and corresponding grayscale counts in each scanning process, thereby realizing multi-row scanning;

The synchronization controller is also used to generate a line feed/frame feed signal, and the line feed/frame feed signal is used to instruct the next line or next frame of pixels to be displayed; the input end of the precharge circuit is connected to the second output end of the synchronization controller; the analog The first input end of the output module is connected to the output end of the driving module, and the second input end of the analog output module is connected to the precharge circuit; The PWM signal of the pixel row is precharged to generate multi-channel driving current to realize constant current driving of the LED lamp bead.

The grayscale clock GCLK in the existing LED driver chip is provided off-chip through the chip pins, and its frequency is often limited by the trace delay of the PCB board, so the number of scanning lines is also limited; the above-mentioned multi-line scanning high refresh It is a full-color LED driver chip with a high-speed full-color LED driver chip, and the gray-scale clock signal GCLK is generated by frequency division/multiplication according to the data clock signal DCLK inside the chip, so that the gray-scale clock signal GCLK can reach a higher frequency, and its frequency automatically tracks DCLK. The interference ability is greatly improved, effectively improving the refresh rate and the number of scan lines that can be supported.

Optionally, in order to set the current size of the output channel, the multi-line scan high refresh rate full-color LED driver chip shown in FIG. 1 may also include: a digital analog converter and a power transmission current regulator; the input of the digital target converter The terminal is connected to the status register, the first input terminal of the output current regulator is used to receive the signal R-EXT, the second input terminal of the output current regulator is connected to the output terminal of the digital analog converter, and the output terminal of the output current regulator is connected to To each output channel; the signal R-EXT is connected to the input end of the external resistor to set the current of the output channel; the output current regulator obtains the content of the state register through the digital analog converter, and according to the state register The content and signal R-EXT adjust the drive current of the output channel.

Optionally, in order to further improve the picture quality, the full-color LED driver chip with multi-line scanning and high refresh rate shown in FIG. 1 may also include: an error state detection module, the input end of which is connected to each output channel of the analog output module. , used to detect the open/short state of the LED lamp bead, and replace the pixel data of the dead pixel with 0 to eliminate the cross phenomenon of the dead pixel;

The dead point is the point where a short circuit occurs. If the dead point produces PWM output, it will cause a local high current, so that the cross highlight phenomenon centered on the dead point, that is, the dead point cross phenomenon; the present invention is detected by the error state detection module. The open/short state of the LED lamp bead, and the pixel data of the dead pixel is replaced with 0, which can avoid generating PWM output at the dead pixel, thereby eliminating the dead pixel cross phenomenon.

In an optional implementation manner, as shown in FIG. 1 , the grayscale clock generation module specifically includes: a phase-locked loop, a frequency multiplying unit, a first frequency dividing unit, and a second frequency dividing unit;

The first input end of the phase-locked loop is used as the first input end of the grayscale clock generation module, and the second input end of the phase-locked loop is connected to the output end of the frequency doubling unit; the first input end of the frequency doubling unit is used as the grayscale clock to generate The second input end of the module, the second input end of the frequency multiplication unit is connected to the output end of the phase-locked loop, and the frequency multiplication unit is used for frequency multiplication of the data clock signal DCLK according to the coefficient P, so as to obtain the frequency multiplied signal and phase-lock the signal. The loop outputs the frequency multiplied signal;

The input end of the first frequency dividing unit is connected to the output end of the phase-locked loop, and the first frequency dividing unit is used to divide the frequency multiplication signal according to the coefficient M ₁ to obtain the frequency division signal;

的灰度时钟信号GCLK；The input end of the second frequency dividing unit is connected to the output end of the first frequency dividing unit, and the second frequency dividing unit is used to divide the frequency division signal according to the coefficient M ₂ , so as to satisfy the

The grayscale clock signal GCLK;

Wherein, P is a dynamically configurable frequency multiplication coefficient, M ₁ and M ₂ are dynamically configurable frequency division coefficients, and f _DCLK and f _GCLK are the frequencies of the data clock signal DCLK and the grayscale clock signal GCLK, respectively;

The present invention is composed of a phase-locked loop and three frequency division/multiplier units to generate a grayscale clock generation module, and generates a grayscale clock signal GCLK by dividing/multiplying the digital clock signal DCLK, wherein the frequency multiplication coefficient P, The frequency division coefficients M ₁ and M ₂ can be dynamically configured, which not only ensures that the generated grayscale clock signal GCLK can reach a higher frequency, but also ensures better brightness efficiency, and ensures that the display time is consistent with the frame interval. At the same time, the frequency division operation is completed in two times, which also reduces the storage requirements for the registers used to store the frequency division coefficients.

In an optional embodiment, the multi-line scanning high refresh rate full-color LED driver chip shown in FIG. 1 integrates R, G, and B three primary color data in the pixel data, and in the process of processing the pixel data , synchronously process the R, G, B three primary color data;

The traditional LED driver chip is only responsible for driving the lamp beads of one primary color. In order to realize the driving of three primary colors, each lamp bead needs to be driven independently by three chips, which occupies a large PCB area; The three primary colors of R, G, and B are integrated in the middle, which can reduce the required PCB area and increase the number of output channels, making it possible for the LED display to achieve a smaller lamp bead spacing; 16-bit single-color pixel data For example, as shown in Figure 2, a 48K bit SRAM buffer (the specific storage space size is determined by the chip loading area) can be embedded in the chip for ping-pong buffer processing, and the 48bit grayscale is then processed when the PWM signal is generated. The data is divided into 16-bit R, G, and B for separate driving, and the chip supports a maximum of 48 channels of output.

In an optional implementation manner, as shown in FIG. 1 , the second input terminal of the synchronization controller is used for receiving the line feed signal ROW, the line feed signal ROW has different high level widths, and the synchronization controller is used for receiving the line feed signal ROW according to the The high level width generates the corresponding line feed/frame feed signal;

Specifically, the high level width of the line feed signal ROW can be set according to the actual application requirements to identify the line feed or frame feed operation. For example, the high level width of the line feed signal ROW can be set to 4 DCLK widths or 8 DCLK widths, wherein, If the high level width of the signal ROW is 8 DCLK widths, it indicates the beginning of the first group of the first row (ie, frame change), and in other cases (ie, line feed) is 4 DCLK widths; in practical applications, when ROW continues When the high level of 8 DCLK cycles indicates that the display of the first group of the first line is to be performed, then the high level of the next 4 DCLK cycles indicates the display of the first group of the second line; described here The setting mode is only an exemplary description, and should not be construed as the only limitation of the present invention;

The traditional LED driver chip changes frames according to the field synchronization signal Vsync. When the field synchronization signal Vsync arrives, it often needs to wait for a period of time to start displaying the next frame, so there is a large frame interval and a low refresh rate; The line feed signal ROW is introduced into the pin, and a line feed/frame feed signal is generated according to the line feed signal ROW to indicate the start of scanning for the next frame or next line. The synchronization signal Vsync is irrelevant, so that a long waiting time can be avoided when changing frames, a frame interval removal technology is realized, and the refresh rate is improved.

In an optional implementation manner, as shown in FIG. 1 , the driving module includes: a counter, a butterfly breaking unit and a comparison unit;

The input end of the counter is used as the first input end of the driving module, and the counter is used to count the grayscale clock signal GCLK to obtain the grayscale count corresponding to the pixel data of each row;

The input end of the butterfly breaking unit is connected to the output end of the counter, and the butterfly breaking unit is used to divide the grayscale count into K gray scale blocks according to the data block mode and rearrange them by the way of butterfly breaking. , to obtain the block number sequence; each gray block corresponds to a gray clock count value, and the sum of the gray clock count values corresponding to all gray blocks is equal to the gray count;

The first input end of the comparison unit is used as the second input end of the driving module, the second input end of the comparison unit is connected to the output end of the butterfly breaking unit, and the comparison unit is used for dividing the pixel data into K pixels according to the block mode It is divided into blocks, and the corresponding numbered gray blocks and pixel blocks are compared in turn according to the block number sequence, thereby generating the output waveform of the PWM signal; each pixel block corresponds to a gray value, and all pixel blocks are The sum of the corresponding grayscale values is equal to the pixel data; wherein, the comparison unit is composed of a plurality of comparators, and each comparator is respectively used to complete the comparison of a pixel block and the grayscale block of the same number;

Among them, K is the number of blocks corresponding to the block mode;

The pixel value corresponding to a pixel block indicates the number of GCLK cycles that need to be turned on for the pixel block when displaying the pixel block. The larger the pixel value corresponding to the pixel block, the brighter the pixel block is when displayed; Take the data (ie grayscale data) as an example, if the pixel data is Data=32800 and the counter is 24 bits, in the traditional PWM signal generation method, the counter will count the grayscale clock signal GCLK, and the pixel data will be counted by the counter. Data is compared to generate a PWM signal, as shown in Figure 3, when displayed in this way, the first half of each line of pixel data will be significantly brighter than the second half when displayed, resulting in bright lines and bright spots; According to the invention, pixel data is divided into 64 blocks (ie, K=64) as an example, and the difference between the pixel values corresponding to each pixel block does not exceed the minimum block unit length (here, 1), and The pixel value corresponding to the pixel block with a smaller number is not less than the pixel value corresponding to the pixel block with a larger number. After the division is completed according to this data division mode, among the 64 blocks obtained, the numbered 0 to 31 The pixel value corresponding to the pixel block is 513, and the pixel value corresponding to the pixel block numbered 32 to 63 is 512, that is, the pixel block numbered 0 to 31 needs to open 513 GCLK cycles, and the pixel numbered 32 to 63. Blocking needs to open 512 GCLK cycles, a total of 513 × 32 + 512 × (64-32) = 32800 GCLK cycles, the specific pixel block and the GCLK cycle of each pixel block is shown in Figure 4; data division After completion, butterfly breaking up all gray scale blocks and pixel blocks to obtain a block number sequence; the present invention disperses the gray scale blocks by butterfly, and displays the pixels according to the reordered numbering order. Blocking makes brighter pixel blocks and darker pixel blocks cross-display, so that the grayscale displayed on the screen is more uniform, avoiding the problem of bright lines and bright spots, and improving the picture quality.

The butterfly breaking is used to reorder the block numbers. The specific method is to express the number of each block into binary according to the block mode, and then reverse the high and low bits of each binary number to obtain the sorted number sequence. ; For example, if the data is divided into 64 blocks, that is, the original block numbers are 0 to 63, then the normal block number is expressed in binary as 6 bits, which are 000000, 000001, 000010..., and after the high and low bits are reversed, the number sequence is 000000 ( 0), 100000(32), 010000(16)...111111(63); for another example, the data is divided into 32 blocks, that is, the original block number is 0 to 31, then the normal block number is expressed in binary as 5 bits, in turn It is 00000, 00001, 00010..., after the high and low bits are reversed, the numbering sequence is 00000(0), 10000(16), 01000(8)...11111(31).

Based on the multi-line scanning full-color LED driver chip with high refresh rate shown in FIG. 1 , the driving method provided by the present invention includes:

(1) Count the grayscale clock signal GCLK to obtain the grayscale count corresponding to each row of pixel data;

(2) for any line of pixel data that needs to be displayed in the current scanning process, divide the line of pixel data into K pixel blocks according to the data block mode;

Each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all pixel blocks is equal to the pixel data;

(3) according to the data block mode, the grayscale count corresponding to the row pixel data is divided into K grayscale blocks and rearranged by the mode of butterfly breaking, to obtain the block number sequence;

Each grayscale block corresponds to a grayscale clock count value, and the sum of the grayscale clock count values corresponding to all grayscale blocks is equal to the grayscale count;

(4) according to the block number sequence, get the gray scale block and the pixel block of the corresponding number in turn and compare, thereby generating the output waveform of the PWM signal corresponding to the pixel data of this row;

(5) for consecutive N rows of pixel data, respectively perform steps (2) to (4) to obtain the output waveform of the PWM signal corresponding to each row of pixel data;

(6) Display the pixel data of consecutive N rows according to the result of the data segmentation and the generated PWM signal, so that the pixels of the same number in the pixel data of the 1st to Nth rows are displayed in sequence, and one of the pixel data of all N rows is displayed in sequence. After the numbered pixel blocks are all displayed, the next numbered pixel block in the block number sequence starts to be displayed;

Among them, K is the number of blocks corresponding to the block mode.

According to the above driving method, taking the block result shown in FIG. 4 as an example, after performing butterfly breaking up, the display sequence of consecutive N lines of data is shown in FIG. 5 , specifically:

First display the No. 0 block in the first row, then display the No. 0 block in the second row, the No. 0 block in the third row... The Nth row No. 0 block;

Then display the 32nd block in the first row, the 32nd block in the second row...the Nth row, the 32nd block;

Then display the 16th block in the first row, the 16th block in the second row...the Nth row and the 16th block;

Then display the 48th block of the first row, the 48th block of the second row...the Nth row of the 48th block;

...

Until all blocks are displayed;

The above-mentioned driving method disperses the pixel data of each row and the corresponding grayscale counts in a butterfly shape, and displays the pixel blocks in the order after the dispersing, so that the brighter pixel blocks and the darker pixel blocks can be displayed in a cross manner. As a result, the grayscale displayed on the screen is more uniform, the problem of bright lines and bright spots is avoided, and the picture quality is improved.

In an optional embodiment, in the above driving method, the pixel value corresponding to the pixel sub-block and the gray-scale count value corresponding to the gray-scale sub-block are not less than L;

Among them, L is an integer power of 2;

When the PWM signal corresponding to each pixel block is turned on, there is a level rise time, as shown in Figure 6, such a level rise time restricts the improvement of the refresh rate; the present invention increases the minimum length of the data block (that is, the pixel The pixel value corresponding to the block or the grayscale count value corresponding to the gray block) can effectively reduce the number of pixel blocks actually displayed, thereby reducing the total level rise time and achieving a higher refresh rate;

Taking the pixel data Data ₁ =22170, divided into 64 blocks, and L=2 ² =4 as an example, the difference between the pixel values corresponding to each pixel block does not exceed the minimum block unit length (here 4), and the number of The pixel value corresponding to the smaller pixel block is not less than the pixel value corresponding to the pixel block with a larger number. After the division is completed according to this data division mode, the pixel data Data1 is divided into 64 blocks. Blocks numbered 0 to 37 enable 87 GCLK cycles of minimum length (ie, 87×4), blocks numbered 38 enable (86×4+2) GCLK cycles, and blocks numbered 39 to 63 enable 86 GCLK cycles Minimum length (ie 86×4) GCLK cycles, a total of 87×38×4+86×(64-38)×4+2=22170 GCLK cycles are turned on; when the pixel data Data ₂ =4 similar situation occurs, If the minimum length is not set, the pixel data Data ₂ will be allocated to 4 different sub-blocks, and one GCLK cycle is turned on in each sub-block, and PWM generation requires four levels of rise time; if the minimum length is set If L=4, the pixel data Data ₂ will only be allocated to one sub-block, and 4 GCLK cycles are turned on in this sub-block, and generating PWM consumes only one level rise time.

In an optional implementation manner, in the above driving method, when each row of pixel data is displayed, the corresponding PWM signal is turned on at the end of the entire PWM driving stage;

When the LED screen is refreshed, there will be a new line time. The line wrap time includes the line erasing discharge time of the previous line and the charging time of the new line. The PWM signal needs to have a pre-charge time before turning on. In the traditional LED driving method , the PWM signal is turned on at the beginning of the entire PWM drive stage, as shown in (a) in Figure 7, the precharge can only be completed by the line feed time, and the line feed time is not fixed, so it may be because the line feed time is too short As a result, the precharging process cannot be completed normally; in the present invention, by turning on the PWM signal at the end of the entire PWM driving stage, as shown in (b) in FIG. Thus, a long enough precharging time is ensured to complete the precharging process, and the response speed of the driving current is improved.

In general, the multi-line scanning high refresh rate full-color LED driver chip and driving method provided by the present invention, the chip internally acquires and generates a grayscale clock GCLK and a multi-channel (for example, 48 channels in FIG. 1) driving technology, The LED lamp beads have a higher refresh rate and better grayscale. The internal grayscale clock GCLK frequency division/multiplication technology supports up to 64 line scans. In the integrated R, G, B three-channel pixels When the data reaches the 48-channel constant current drive output of a single chip, the LED display can achieve a smaller lamp bead spacing. Compared with the prior art, the present invention makes the LED screen display more delicate, has better high-brightness and low-gray effects, and a higher refresh rate, and can carry a larger display screen under the condition of the same number of driving chips It provides a good solution for designing full-color LED driver chips with small dot pitch, multi-channel, multi-line scanning and high refresh rate, and has practical application value.

Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, etc., All should be included within the protection scope of the present invention.

Claims (8)

1. A full-color L ED driving chip with multi-row scanning high refresh rate is characterized by comprising a synchronous controller, a shift register, a state register, an SRAM buffer, a gray scale clock generation module, a driving module, a pre-charging circuit and an analog output module;

the synchronization controller, a first input of which is used for receiving a latch signal L E, the latch signal L E is used for indicating the type of input data, the synchronization controller is used for transmitting the latch signal L E to the shift register and the state register through a first output of the synchronization controller;

the shift register is used for identifying instruction data and pixel data from the serial input data SDI according to the latch signal L E and transmitting the instruction data and the pixel data to the state register and the SRAM buffer respectively;

the first input end of the gray clock generation module is used for receiving the data clock signal DC L K, the second input end of the gray clock generation module is connected with the state register, and the gray clock generation module is used for performing frequency multiplication/frequency division processing on the data clock signal DC L K according to instruction information to generate a gray clock signal GC L K, wherein the gray clock signal is used for controlling gray scales;

the first input end of the driving module is connected to the output end of the gray clock generation module, the second input end of the driving module is connected to the SRAM buffer, and the driving module is configured to count the gray clock signal GC L K to obtain a gray count corresponding to each row of pixel data, and generate an output waveform of a PWM signal corresponding to each row of pixel data by using N consecutive rows of pixel data and the corresponding gray count in each scanning process, thereby implementing multi-row scanning;

the synchronous controller is also used for generating a line changing/frame changing signal which is used for indicating to display a next line or a next frame pixel, the input end of the pre-charging circuit is connected to the second output end of the synchronous controller, the first input end of the analog output module is connected to the output end of the driving module, and the second input end of the analog output module is connected with the pre-charging circuit which is used for pre-charging a PWM signal of a pixel line to be displayed under the indication of the line changing/frame changing signal so as to generate a multi-channel driving current and realize the constant current driving of an L ED lamp bead;

the driving module includes: the device comprises a counter, a butterfly scattering unit and a comparison unit;

the input end of the counter is used as the first input end of the driving module, and the counter is used for counting the gray clock signal GC L K to obtain the gray count corresponding to each row of pixel data;

the input end of the butterfly scattering unit is connected to the output end of the counter, and the butterfly scattering unit is used for dividing the gray scale count into K gray scale blocks according to a data blocking mode and rearranging the K gray scale blocks in a butterfly scattering mode to obtain a block numbering sequence; each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;

the first input end of the comparison unit is used as the second input end of the driving module, the second input end of the comparison unit is connected to the output end of the butterfly scattering unit, the comparison unit is used for dividing pixel data into K pixel blocks according to the block mode, and sequentially taking the gray blocks and the pixel blocks which are correspondingly numbered according to the block number sequence for comparison, so that the output waveform of the PWM signal is generated; each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data;

and K is the number of the blocks corresponding to the block mode.

2. The multi-scan high refresh rate full-color L ED driver chip of claim 1, wherein the gray scale clock generation module comprises a phase locked loop, a frequency doubling unit, a first frequency dividing unit, and a second frequency dividing unit;

the first input end of the frequency doubling unit is used as the second input end of the gray scale clock generation module, the second input end of the frequency doubling unit is connected to the output end of the phase-locked loop, and the frequency doubling unit is used for doubling the frequency of the data clock signal DC L K according to a coefficient P to obtain a frequency doubling signal and outputting the frequency doubling signal through the phase-locked loop;

the input end of the first frequency division unit is connected to the output end of the phase-locked loop, and the first frequency division unit is used for dividing the phase-locked loop according to a coefficient M₁Dividing the frequency of the frequency multiplication signal to obtain a frequency division signal;

the input end of the second frequency dividing unit is connected to the output end of the first frequency dividing unit, and the second frequency dividing unit is used for dividing the frequency according to a coefficient M₂Frequency-dividing the frequency-divided signal to obtain a frequency-divided signal satisfying

The gray scale clock signal GC L K;

wherein P is a dynamically configurable frequency multiplication coefficient, M₁And M₂For dynamically configurable division factor, f_DCLKAnd f_GCLKThe frequencies of the data clock signal DC L K and the gray clock signal GC L K, respectively.

3. The multi-row scan high refresh rate full-color L ED driver chip of claim 1 or 2, wherein R, G, B three primary color data are integrated into the pixel data, and R, G, B three primary color data are processed synchronously during the processing of the pixel data.

4. The multi-ROW scan high refresh rate full-color L ED driver chip as claimed in claim 1 or 2, wherein the second input terminal of the synchronous controller is used for receiving a line feed signal ROW having different high-level widths, and the synchronous controller is used for generating corresponding line/frame signals according to the high-level widths of the line feed signal ROW.

5. The multi-row scan high-refresh-rate full-color L ED driver chip of claim 1 or 2, further comprising an error detection module having an input connected to each output channel of the analog output module for detecting L open/short circuit status of the ED lamp bead and replacing the pixel data of dead pixel with 0 to eliminate dead pixel cross.

6. A driving method of a multi-row scan high refresh rate full-color L ED driver chip according to any of claims 1-5, comprising:

(1) counting the gray clock signal GC L K to obtain a gray count corresponding to each row of pixel data;

(2) dividing any line of pixel data to be displayed in the current scanning process into K pixel blocks according to a data block mode;

each pixel block corresponds to a gray value, and the sum of the gray values corresponding to all the pixel blocks is equal to the pixel data;

(3) dividing the gray scale count corresponding to the row of pixel data into K gray scale blocks according to the data block mode, and rearranging the K gray scale blocks in a butterfly scattering mode to obtain a block number sequence;

each gray scale block corresponds to a gray scale clock count value, and the sum of the gray scale clock count values corresponding to all the gray scale blocks is equal to the gray scale count;

(4) sequentially taking the gray-scale blocks with the corresponding numbers and the pixel blocks according to the block number sequence for comparison, thereby generating an output waveform of the PWM signal corresponding to the row of pixel data;

(5) for the continuous N rows of pixel data, steps (2) to (4) are respectively executed to obtain output waveforms of PWM signals corresponding to the pixel data of each row;

(6) displaying the pixel data of the continuous N lines according to the data blocking result and the generated PWM signal, so that the pixel blocks with the same number in the pixel data of the 1 st to N lines are sequentially displayed, and starting to display the pixel block with the next number in the block number sequence after the pixel block with one number in all the pixel data of the N lines is completely displayed;

and K is the number of the blocks corresponding to the block mode.

7. The driving method according to claim 6, wherein a pixel value corresponding to the pixel block and a gray scale value corresponding to the gray scale block are not less than L;

wherein L is an integer power of 2.

8. A method according to claim 6 or 7, wherein for each row of pixel data to be displayed, the corresponding PWM signal is turned on at the end of the entire PWM driving phase.

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