CN109903721B - LED drive circuit based on frequency multiplication OS-PWM algorithm - Google Patents
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Abstract
The invention discloses an LED driving circuit based on a frequency multiplication OS-PWM algorithm, and belongs to the technical field of circuits. The LED driving circuit based on the frequency multiplication OS-PWM algorithm comprises a reset circuit, a decoding circuit, an SRAM control circuit, an MBIST circuit, a PWM control circuit, a PWM generating circuit, a low-ash processing circuit and an open-circuit detection circuit. The reset circuit generates a frame-changing reset signal; the decoding circuit completes instruction decoding operation; the SRAM control circuit completes SRAM read-write logic control; the MBIST circuit completes SRAM check; the PWM control circuit completes the relevant logic control of the PWM counter; the PWM generating circuit generates PWM output; the low-ash processing circuit realizes low-ash processing operations such as ghost, first line and the like; the open circuit detection circuit completes open circuit LED detection and shielding. The invention solves the problems of low refresh rate, poor low gray scale uniformity, ghost, dark first row, open cross and the like of the small-spacing LED driving chip, reduces the circuit area and the cost, and is successfully applied.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to an LED driving circuit based on a frequency multiplication OS-PWM algorithm.
Background
As a novel semiconductor lighting material, the LED is widely applied to lighting equipment, display screens and other electronic equipment by virtue of the advantages of low power consumption, long service life, small size, low cost, high efficiency, safety, greenness, no pollution and the like.
The LED display screen with the small dot spacing has the advantages of seamless splicing, natural and real color, clear picture, modularized maintenance, good display uniformity and the like, meets the requirements of the display screen on high definition, high fineness and close range appreciation of the display effect, and gradually becomes a research hotspot. The multi-path constant-current LED driving chip has the advantages of good matching, accurate current control, high gray scale display, excellent display effect and the like, and is widely applied to small-spacing LED driving chips.
In a traditional multi-path constant-current LED driving chip, a PWM mode is mostly adopted for display control, and the display effect of different gray-scale brightness is achieved by controlling the bright/dark time of an LED. When the displayed gray scale brightness is low, namely the LED has short light emitting time in the working period and has long continuous non-light emitting time, human eyes can easily feel the flicker phenomenon at the time. In a small-dot-pitch LED display screen, the traditional PWM has the problems of low refresh rate, low gray level, unsatisfactory low gray effect and the like, and can not meet the requirements of the display screen on the reality, fineness and vivid color of a picture. In a traditional PWM control mode, a flicker phenomenon occurs, the refresh rate is low, and the gray level is not high; due to the influence of parasitic capacitance, display defects such as ghost, low gray-white balance color cast, dark first line, uneven low gray color block, open cross and the like can occur.
Disclosure of Invention
The invention aims to provide an LED drive circuit based on a frequency multiplication OS-PWM algorithm, which is applied to a small-dot-spacing multi-channel constant-current LED drive chip and solves the problems of low refresh rate, poor low gray scale uniformity, ghost, dark first line, open-circuit cross and the like of the small-spacing LED drive chip, so that a display picture is clearer, finer and more real.
In order to solve the above technical problem, the present invention provides an LED driving circuit based on a frequency multiplication OS-PWM algorithm, comprising:
a reset circuit generating a frame change reset signal;
the decoding circuit completes instruction decoding operation;
the SRAM control circuit is used for finishing SRAM read-write logic control;
the MBIST circuit completes SRAM check;
the PWM control circuit is used for finishing the related logic control of the PWM counter;
a PWM generation circuit that generates a PWM output;
the low-ash processing circuit is used for realizing low-ash processing operations such as ghost, first line and the like;
and the open circuit detection circuit is used for completing the open circuit LED detection and shielding.
Optionally, the reset circuit generates a frame-changing reset signal RSTN for resetting the internal control signal when changing frames; by inserting a delay unit, delaying the signal CMD _ VSYNC to obtain a signal CMD _ VSYNC _ D, and combining the two signals to generate a frame-change reset signal RSTN, that is:
RSTN＝～CMD_VSYNC|CMD_VSYNC_D。
optionally, the decoding circuit parses the LE length into a data input mode, a register read/write mode, an SDO output mode, and a test mode; wherein,
the length of LE means the number of rising edges of DCLK when LE is high, EN _ OP is issued first for each frame, then registers are configured, and PRE _ ACT needs to be issued first before each register is configured.
Optionally, the SRAM control circuit parses input data and addresses into corresponding SRAM control signals; DCLK is used as a read-write clock, and the next row of data is read in advance by adding 16 multiplied by 16bit buffer;
and when read-write operation occurs simultaneously, the write operation is processed preferentially, a group of DCLK needs to be sent in advance after the first frame data of VSYNC, and a write overflow protection circuit is added.
Optionally, the MBIST circuit completes SRAM check, and enables an SRAM check state when the LE length includes 15 LE rising edge numbers, and enters MBIST debugging; the SRAM input selects different signals, including data input/output, W/R control, address, clock.
Optionally, the PWM control circuit generates PWM counter 9-bit CNT1 and 7-bit CNT2, a line counter, and EN _ ghz and leading line dim adjust indication signals; the 9-bit CNT1 is used for counting the clock number of each group of PWM period, the 7-bit CNT2 is used for counting the scattered group number, and the 9-bit CNT1 and the 7-bit CNT2 are combined, and the PWM counting control is realized by adopting a frequency multiplication technology; wherein,
the frequency doubling technology specifically comprises the following steps: the 9-bit CNT1 adopts a double-edge counting mode, and a double-edge counting clock is inverted and subjected to exclusive OR generation on the rising edge and the falling edge of GCLK based on GCLK; the frequency multiplication is closed, the rising edge counting is started, the frequency multiplication and the double edge counting are started, and the circuit area can be reduced by half.
Optionally, the PWM generating circuit uses an OS-PWM algorithm to break up the on-time of a group of data into a plurality of relatively short time periods, and each of the relatively short time periods maintains the original duty ratio, so as to increase the overall refresh rate of the LED display screen.
Optionally, the OS-PWM algorithm specifically includes: the PWM data is scattered, so that the problem of flicker under the condition of low ash can be avoided; dividing 16-bit data into 9-bit upper-bit data MSB and 7-bit lower-bit data LSB;
because the data of the MSB with the upper 9 bits takes the main role in image display, the refresh rate of the LED display screen is improved by scattering the counting of the MSB; the MSB count cycle is broken up and repeated for multiple times, plus one LSB count cycle, to achieve the same resolution as the undivided PWM.
Optionally, the low-gray processing circuit provides an adjusting method for the first row which is dark, the reserved time enables the capacitor to discharge in advance, and the problem of the first row which is dark is solved; for the lower ghost, charge is discharged within a reserved time, so that the lower ghost problem is solved; for low gray balance, a register adjustment design is added.
Optionally, the open-circuit detection circuit records the information of the open-circuit LED lamp by detecting the open-circuit LED lamp bead, and does not light the open-circuit LED lamp bead during the display process.
The invention has the following beneficial effects:
(1) on the basis of an OS-PWM display algorithm, the invention adopts a clock frequency multiplication technology to improve the whole refresh rate, simultaneously reduces the complexity of the algorithm by a half and reduces the whole area by 40 percent;
(2) aiming at the problems of poor display uniformity, ghost, dark first line, open-circuit cross and the like, the OS-PWM algorithm is subjected to complementary design, so that the problems are effectively solved;
(3) the invention provides a universal design method, which is suitable for display control of a multi-channel constant-current LED driving chip, specific parameters can be defined by self according to requirements, and the flexibility and the applicability are strong.
Drawings
FIG. 1 is an overall architecture diagram of an LED driving circuit based on a frequency multiplication OS-PWM algorithm provided by the present invention;
fig. 2 is a reset signal generation timing diagram;
FIG. 3 is a timing diagram of an LED driver circuit configuration register;
FIG. 4 is a state jump diagram of an SRAM control circuit;
FIG. 5 is an OS-PWM algorithm scatter control chart;
FIG. 6 is a control diagram of the OS-PWM algorithm 32 row scan 16 channel display.
Detailed Description
The LED driving circuit based on the frequency multiplication OS-PWM algorithm according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides an LED driving circuit based on a frequency multiplication OS-PWM algorithm, which is suitable for a multi-channel constant-current LED driving chip. As shown in fig. 1, the LED driving circuit based on the frequency multiplication OS-PWM algorithm includes a reset circuit, a decoding circuit, an SRAM control circuit, an MBIST circuit, a PWM control circuit, a PWM generation circuit, a low-gray processing circuit, and an open circuit detection circuit; specifically, the reset circuit generates a frame change reset signal; the decoding circuit completes instruction decoding operation; the SRAM control circuit completes SRAM read-write logic control; the MBIST circuit completes SRAM check; the PWM control circuit completes the relevant logic control of the PWM counter; the PWM generating circuit generates PWM output; the low-ash processing circuit realizes low-ash processing operations such as a first line of ghost; the open circuit detection circuit completes open circuit LED detection and shielding.
Fig. 2 is a timing diagram of the reset signal generation, and the reset circuit generates a frame-change reset signal RSTN for resetting the internal related control signals at the time of frame change. Delaying the signal CMD _ VSYNC by inserting a delay unit to obtain a signal CMD _ VSYNC _ D; the two signals are combined to generate a frame-change reset signal RSTN, namely: RSTN ═ CMD _ VSYNC | CMD _ VSYNC _ D.
Table 1 is an instruction decoding circuit decoding table, which is parsed into corresponding data input, register read/write, SDO output, and test modes according to the input LE length. The length of LE refers to the number of rising edges of DCLK when LE is high. EN _ OP is issued first and then registers are configured, PRE _ ACT is signaled before each register is configured, and the instruction system table is shown in Table 1. The LE length, i.e., the number of rising edges of DCLK, is counted by a 4-bit counter. On the falling edge of the signal LE _ IN, depending on the value of the counter, LE _ IN is decoded into the corresponding instruction.
TABLE 1 instruction decode circuit decode table
Fig. 3 is a timing diagram of a register configuration of the LED driving circuit, where data is written into a corresponding register according to an instruction for writing different registers at a falling edge of a signal LE _ IN, and a reset signal of each register is a power-on reset signal and is a default value after reset. The specific process is as follows:
(1) from time a to time B, an EN _ OP command (LE high level for 12 DCLK) is sent, enabling the channel;
(2) at times C to D, a PRE _ ACT command (LE high level for 14 DCLK) is sent;
(3) at times E to F, a WR _ CFG1 command (LE high level of 4 DCLK) is transmitted, and 16-bit serial data WR _ REG1 is written to register 1 by SDI;
(4) at times G through H, a PRE _ ACT command (LE high for 14 DCLK) is sent, at which time the SDO serially outputs the value of RD _ REG 1;
(5) at times I to J, a WR _ CFG2 command (LE high level of 6 DCLK) is transmitted, and 16-bit serial data WR _ REG2 is written to the register 2 through SDI;
(6) at times K through L, a PRE _ ACT command (LE high for 14 DCLK) is issued, at which time the SDO serially outputs the value of RD _ REG 2.
Fig. 4 is a state jump diagram of an SRAM control circuit, which mainly resolves the input data and address into corresponding SRAM control signals. The gray DATA 1, 16bit DATA is latched as the first row DATA of the channel 15, the 2 nd 16bit DATA is as the first row DATA of the channel 14, and the 17 th 16bit DATA is as the second row DATA of the channel 15 by the "DATA _ LATCH" command. The novel architecture of a built-in 16KB single SRAM is used for caching multiple rows of gray scale data. The SRAM is divided into two 8KB according to the highest bit of the address, one block is displayed for image display, and the other block is written in the next frame data. DCLK is used as a read-write clock, the relation between DCLK and GCLK is not limited, and the next row of data is read in advance by adding 16 multiplied by 16bit buffer. And when the read-write operation occurs at the same time, the write operation is preferentially processed. First frame data after VSYNC (vertical synchronization) needs to send a group of DCLK in advance, and the write overflow protection function is added.
Fig. 5 is a scatter control chart of the OS-PWM algorithm, taking a 32-scan 16-channel constant-current LED driving chip applied with the present invention as an example, 16-bit gray data has 65536 kinds of gray. If under traditional PWM mode, LED lamp pearl will have a considerable time of going out when low gray, causes the distinguishable scintillation of people's eye. And the SPWM technology is utilized to scatter the PWM data, so that the problem of flicker under the condition of low ash can be avoided. The 16-bit data is divided into 9-bit upper data MSB and 7-bit lower data LSB. Since the data of the MSB with the upper 9 bits plays a major role in image display, the refresh rate of the LED display screen is increased by scattering the count of the MSB. The MSB count cycle is broken up and repeated for multiple times, plus one LSB count cycle, to achieve the same resolution as the undivided PWM. One display period T is divided into 128/256 equal parts each based on 9 bits 511T/255T and one clock period T for the timing of lower data, making up 512/256 count periods. Thus, the total is still 512T × 128-65536T-T (256T × 256-65536T-T), and the total gray scale is unchanged, but the refresh rate is increased by 128/256 times.
Table 2 shows a refresh rate table, which shows that 65536 clocks are required for one frame of data, and in the case of frequency doubling off, 512/256 clocks are respectively required for the dispersed 128/256 groups, and the rate is 1/2 times in turn. Under the condition of frequency multiplication starting, the rising edge and the falling edge are counted at the same time, the number of required clocks is reduced by half, namely the same frame data, the required clocks of the scattered 128/256 groups are 256/128 clocks respectively, and in the same time, the refresh rate is doubled, namely 2/4 times.
TABLE 2 Refresh multiplying power table
Table 3 shows the multiplier counter selection table, and the PWM control circuit generates PWM counter 9-bit CNT1 and 7-bit CNT2, the line counter, and the ghost-down and leading-line dim-down adjustment indicators. The 9-bit CNT1 is used for counting the number of clocks per PWM period, and is generated by combining an ODD counter CNT1_ ODD and an EVEN counter CNT1_ EVEN, the 7-bit CNT2 is used for counting the number of scattered groups, and the 9-bit CNT1 and the 7-bit CNT2 are combined to realize PWM counting control. With the doubling off, the CNT1_ EVEN is inactive and the 9-bit CNT1 is derived directly from the CNT1_ ODD, jumping on the rising edge of the clock. With the frequency doubling on, the CNT1_ ODD transitions on the rising edge of the clock, the CNT1_ EVEN transitions on the falling edge of the clock, and the final 9-bit CNT selects CNT1_ EVEN at clock high and CNT1_ ODD at clock low.
TABLE 3 selection table for frequency multiplication counter
Fig. 6 is a control diagram of OS-PWM algorithm 32 line scan 16-channel display, taking a 32-scan 16-channel constant current LED driving chip applied with the present invention as an example, and sequentially switching and outputting from 0 to 31 lines in each scattering period. Considering different application scenarios, the break-up situation is designed to be configurable: 128 groups and 256 groups, the number of groups can be matched, but the total GCLK period is not changed, so that different refresh rates can be obtained. The larger the number of packets, the better the break-up, the higher the refresh rate, but at the same time the switching frequency of the output switches. In each of the broken groups, the pulse widths of the PWM waveforms will be averaged to the greatest possible extent. For example, the OS-PWM pattern is configured to break up 128 GROUPs, named GROUP0 and GROUP1 … … GROUP127 respectively, if the gray scale is 128, the maximum possible average pulse width of each GROUP will be 1 GCLK period, if the gray scale is 132, except that the pulse widths in GROUP jp0, GROUP64, GROUP32 and GROUP96 are 2 GCLK periods, the rest are still 1 GCLK period, i.e. the rest 4 gray scales after averaging will be evenly distributed into 4 GROUPs, and the interval between each GROUP is 32 GROUPs to achieve the average distribution as much as possible.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (1)
1. An LED driving circuit based on a frequency multiplication OS-PWM algorithm is characterized by comprising:
a reset circuit generating a frame change reset signal;
the decoding circuit completes instruction decoding operation;
the SRAM control circuit is used for finishing SRAM read-write logic control;
the MBIST circuit completes SRAM check;
the PWM control circuit is used for finishing the related logic control of the PWM counter;
a PWM generation circuit that generates a PWM output;
the low-ash processing circuit is used for realizing low-ash processing operations such as ghost, first line and the like;
an open circuit detection circuit for completing the open circuit LED detection and shielding;
the SRAM control circuit resolves input data and addresses into corresponding SRAM control signals; DCLK is used as a read-write clock, and the next row of data is read in advance by adding 16 multiplied by 16bit buffer; when read-write operation occurs simultaneously, the write operation is processed preferentially, a group of DCLK needs to be sent in advance after first frame data of VSYNC, and a write overflow protection circuit is added;
the MBIST circuit completes SRAM check, and when the LE length comprises 15 LE rising edge numbers, the SRAM check state is enabled, and MBIST debugging is started; SRAM inputs select different signals, including data input/output, W/R control, address, clock;
the PWM control circuit generates PWM counter 9-bit CNT1 and 7-bit CNT2, a line counter, and EN _ GHOST and leading line dim-bias adjustment indication signals; the 9-bit CNT1 is used for counting the clock number of each group of PWM period, the 7-bit CNT2 is used for counting the scattered group number, and the 9-bit CNT1 and the 7-bit CNT2 are combined, and the PWM counting control is realized by adopting a frequency multiplication technology; the frequency doubling technology specifically comprises the following steps: the 9-bit CNT1 adopts a double-edge counting mode, and a double-edge counting clock is inverted and subjected to exclusive OR generation on the rising edge and the falling edge of GCLK based on GCLK; the frequency multiplication is turned off, the rising edge counting is turned on, the frequency multiplication and the double edge counting are turned on, and half of the circuit area can be reduced;
the PWM generating circuit adopts an OS-PWM algorithm to break the conduction time of a group of data into a plurality of relatively short time periods, and the original duty ratio is kept in each relatively short time period so as to increase the overall refresh rate of the LED display screen; the OS-PWM algorithm is specifically as follows: the PWM data is scattered, so that the problem of flicker under the condition of low ash can be avoided; dividing 16-bit data into 9-bit upper-bit data MSB and 7-bit lower-bit data LSB; because the data of the MSB with the upper 9 bits takes the main role in image display, the refresh rate of the LED display screen is improved by scattering the counting of the MSB; after the counting period of the MSB is scattered, the counting is repeated for a plurality of times, and the resolution ratio which is the same as that of the non-decomposed PWM can be achieved by adding the counting period of the LSB once;
the reset circuit generates a frame-changing reset signal RSTN used for resetting an internal control signal when a frame is changed; by inserting a delay unit, delaying the signal CMD _ VSYNC to obtain a signal CMD _ VSYNC _ D, and combining the two signals to generate a frame-change reset signal RSTN, that is:
RSTN=~CMD_VSYNC | CMD_VSYNC_D；
the decoding circuit analyzes the data into a data input mode, a register read-write mode, an SDO output mode and a test mode according to the input LE length; wherein,
the length of LE means that when LE is high level, the rising edge number of DCLK sends EN _ OP first, then the register is configured, and PRE _ ACT needs to be sent before each register is configured;
the low-gray processing circuit provides an adjusting method for the first row which is dark, the capacitor is discharged in advance by the reserved time, and the problem of the first row which is dark is solved; for the lower ghost, charge is discharged within a reserved time, so that the lower ghost problem is solved; aiming at low gray balance, a register adjustment design is added;
the open circuit detection circuit records the information of the open circuit LED lamp by detecting the open circuit LED lamp bead, and the open circuit LED lamp bead is not lightened in the display process.
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| CN111599305B (en) * | 2020-06-04 | 2023-06-06 | 南京达斯琪数字科技有限公司 | LED drive circuit of flexible transparent screen |
| KR102744636B1 (en) | 2020-08-11 | 2024-12-20 | 삼성전자주식회사 | Display apparatus and controlling method thereof |
| CN112116892A (en) * | 2020-09-09 | 2020-12-22 | 中科芯集成电路有限公司 | Low-gray-scale optimization PWM algorithm for LED driving chip |
| CN112037710B (en) * | 2020-09-09 | 2021-11-23 | 中科芯集成电路有限公司 | PWM algorithm for opening channels of multi-channel LED driving chip in time-sharing manner |
| CN114501096B (en) * | 2020-10-27 | 2025-04-29 | 西安钛铂锶电子科技有限公司 | Image display method, image display device and image display system |
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| CN114664238B (en) * | 2022-03-23 | 2023-09-19 | 无锡力芯微电子股份有限公司 | PWM data synchronization method for LED display |
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