CN112116892A - Low-gray-scale optimization PWM algorithm for LED driving chip - Google Patents
Low-gray-scale optimization PWM algorithm for LED driving chip Download PDFInfo
- Publication number
- CN112116892A CN112116892A CN202010941254.9A CN202010941254A CN112116892A CN 112116892 A CN112116892 A CN 112116892A CN 202010941254 A CN202010941254 A CN 202010941254A CN 112116892 A CN112116892 A CN 112116892A
- Authority
- CN
- China
- Prior art keywords
- sub
- period
- opt
- gray scale
- gclk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005457 optimization Methods 0.000 title claims abstract description 25
- 230000000694 effects Effects 0.000 claims abstract description 9
- 229910002056 binary alloy Inorganic materials 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000011324 bead Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of El Displays (AREA)
Abstract
The invention discloses an LED driving chip low gray scale optimization PWM algorithm, and belongs to the field. 2 required for displaying N-bit gray dataNGCLK is equally distributed to 2LIn each sub-period, each sub-period includes 2HGCLK, N, H, L are positive integers, N ═ H + L; setting an optimization level Opt which is a non-negative integer, and setting the minimum width of PWM in each sub-period to 2Opt(ii) a When the gray scale data is 2L+OptAt integral multiple of (2), the gray data is equally distributed to 2LIn a sub-period; when the gray data is not 2L+OptAt integral multiple of (d), the highest bit to the (L + Opt +1) th bit of the binary gray scale data is multiplied by 2L+OptThe obtained product is equally distributed to 2LIn a sub-period; dividing Low (L + Opt) bits of binary Gray data by 2OptThe obtained quotient is marked as D, and the remainder is marked as R; allocating R GCLK in the 0 th sub-period; divide the remaining gray values into D groups of 2OptGCLK assigned to sub-periods 1 to 2 in units of groupsL1 is mentioned above. The invention canThe display effect in the low gray scale is effectively improved, and the problems of low gray pockmarks, uneven low gray display and the like are solved.
Description
Technical Field
The invention relates to the technical field of LED display, in particular to a low gray scale optimization PWM algorithm of an LED driving chip.
Background
The LED is also called as a light emitting diode, and has the advantages of high energy efficiency, low power consumption, low cost, environmental protection and the like. The LED display screen has the advantages of good display effect, customization, high maintainability and the like, and has good prospect in the indoor and outdoor display large-screen market.
The LED large-screen driving chip on the market generally adopts a PWM dimming technology, and controls LED driving current by adjusting the pulse width of a digital signal, so that the brightness of an LED lamp bead is controlled. The SPWM is developed on the basis of the PWM algorithm, namely the PWM algorithm is broken up, and FIG. 1 is a schematic diagram of the SPWM algorithm commonly adopted by the current LED driving chip. The algorithm breaks up the whole display period into a plurality of groups, each group comprises a plurality of GCLK periods, the original PWM pulse is evenly distributed into the broken groups, and the original PWM duty ratio, namely the brightness, is kept unchanged; due to the fact that the channel opening times are increased, the display refresh rate can be greatly improved, and the visual smoothness is improved.
The conventional SPWM algorithm causes a serious display problem when displaying a low gray image. Fig. 2 is a waveform of the conventional SPWM algorithm in low gray, and it can be seen that each time the gray value is increased, a new gray value is assigned to a new break-up sub-period, each sub-period only contains 1 GCLK period, which has the advantage of improving the screen refresh rate. The analog channel of the LED driving chip needs to correspondingly change the output voltage when the upper edge and the lower edge of the PWM waveform are identified, so that the LED lamp bead is controlled. With the increase of the GCLK frequency, the time of each GCLK period is reduced, the analog channel is difficult to complete the pull-up and pull-down of the level in time, and often needs to be pulled up before the pull-down is completed, so that the effective display time cannot be identified. At the moment, the LED screen has serious low-gray pockmark and uneven display, and the LED display effect is reduced to a great extent. Therefore, a new algorithm is needed to solve the display problem of the LED driving chip in low gray.
Disclosure of Invention
The invention aims to provide a low-gray level optimization PWM algorithm of an LED driving chip, which aims to solve the problems that the existing LED large screen is easy to have low-gray pockmarks and uneven color display when displaying a low-gray picture.
In order to solve the above technical problem, the present invention provides a low gray scale optimization PWM algorithm for an LED driving chip, comprising:
step 1, 2 required for displaying N-bit gray scale dataNGCLK is equally distributed to 2LIn each sub-period, each sub-period includes 2HGCLK, N, H, L are positive integers, N ═ H + L;
step 2, setting an optimization grade Opt, wherein the Opt is a non-negative integer, and setting the minimum width of the PWM in each sub-period to be 2Opt；
step 5, on the basis of step 4, dividing the low (L + Opt) bit of the binary gray scale data by 2OptThe obtained quotient is marked as D, and the remainder is marked as R;
step 6, distributing R GCLK in the 0 th sub-period based on the step 5;
step 7, on the basis of the steps 5 and 6, dividing the residual gray values into D groups, wherein each group 2 is provided withOptGCLK assigned to sub-periods 1 to 2 in units of groupsL1 is mentioned above.
Optionally, step 2 includes: when Opt takes 0, 1, 2, 3 … … respectively, the minimum PWM width in each sub-period is 1, 2, 4, 8 … … respectively; only when the PWM width in one sub-period reaches the minimum PWM width will the gray value be allocated in the other sub-periods.
Optionally, in the step 3, the gray data are equally distributed to 2LSub-periods, each sub-period being assigned 2OptPositive integer multiples of GCLK; when L is 5, the whole display period is scattered as2532 sub-periods; the optimization level Opt is set to 2, and the minimum width of PWM in each sub-period is 224 GCLK; if the gray scale data is 128, it is equal to 25+2Is 2L +OptThe integral multiple of the gray scale data, the gray scale data are evenly distributed into 32 sub-periods, and each sub-period has 4 GCLK; if the gradation data is 256, it is equal to 25+2X 2 is 2L+OptThe integer multiple of (2), the gray scale data is equally distributed into 32 sub-periods, 8 GCLK per sub-period.
Optionally, in step 4, when L is 5, the whole display period is broken up to 2532 sub-periods; the optimization level Opt is set to 2, and the minimum width of PWM in each sub-period is 224 GCLK; if the gray data is 129, the highest bit of the binary system is taken to the 8 th bit (2' b0..001), and the result is 128 after being multiplied by 128, and the 128 gray values are evenly distributed into 32 sub-periods, each of which is 4 GCLK.
Optionally, in step 5, when L is 5, the whole display period is broken up to 2532 sub-periods; the optimization level Opt is set to 2, and the minimum width of PWM in each sub-period is 224 GCLK; if the gray scale data is 9, dividing the binary lower 7 bits (7' b0001001) by 4 to obtain a quotient D of 2 and a remainder R of 1; if the gray scale data is 131, the binary lower 7 bits (7' b0000010) are divided by 4 to obtain a quotient D equal to 0 and a remainder R equal to 3.
Optionally, in the step 6, the remainder R GCLK in the step 5 is allocated to the 0 th sub-period.
Optionally, in step 7, the groups are allocated to sub-period 1 to sub-period 2LThe principle of allocation in-1 is: the spacing between groups is made equal as much as possible to improve the display uniformity.
Optionally, by increasing the minimum width of the PWM pulse during low gray, the problem that the effective display time is difficult to identify by the analog channel during low gray can be effectively solved, resulting in low gray pits and uneven display.
Optionally, the remainder R in step 6 is fully distributed in the 0 th sub-period, so that the PWM widths of the remaining sub-periods are always equal to each otherIn 2OptThe integral multiple of the channel interference is reduced, and the display effect of each channel is improved.
In the LED driving chip low gray scale optimization PWM algorithm provided by the invention, 2 required for displaying N-bit gray scale dataNGCLK is equally distributed to 2LIn each sub-period, each sub-period includes 2HGCLK, N, H, L are positive integers, N ═ H + L; setting an optimization level Opt which is a non-negative integer, and setting the minimum width of PWM in each sub-period to 2Opt(ii) a When the gray scale data is 2L+OptAt integral multiple of (2), the gray data is equally distributed to 2LIn a sub-period; when the gray data is not 2L+OptAt integral multiple of (d), the highest bit to the (L + Opt +1) th bit of the binary gray scale data is multiplied by 2L+OptThe obtained product is equally distributed to 2LIn a sub-period; dividing Low (L + Opt) bits of binary Gray data by 2OptThe obtained quotient is marked as D, and the remainder is marked as R; allocating R GCLK in the 0 th sub-period; divide the remaining gray values into D groups of 2OptGCLK assigned to sub-periods 1 to 2 in units of groupsL1 is mentioned above.
The invention has the following beneficial effects:
(1) aiming at the problems that the traditional LED driving PWM algorithm is easy to cause display pockmarks and uneven color display in low gray, the PWM algorithm is optimized, and the display uniformity and the display effect of an LED screen in the low gray condition are effectively improved;
(2) coupling interference among channels of the LED driving chip is effectively reduced;
(3) the display effect of the cross-plate coupling is effectively improved.
Drawings
FIG. 1 is a schematic diagram of a conventional SPWM algorithm;
FIG. 2 is a waveform schematic of a conventional SPWM algorithm at low gray;
FIG. 3 is a schematic flow chart of a low gray scale optimization PWM algorithm for an LED driver chip according to the present invention;
fig. 4 is a schematic diagram of a low gray scale optimization PWM algorithm of an LED driving chip according to the present invention.
Detailed Description
The following describes an LED driving chip low gray scale optimization PWM algorithm according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It should be noted that, in this patent, like reference numerals are used for like elements, and the drawings are in a very simplified form and are not to precise scale, so as to facilitate and clearly explain the embodiments of the present invention.
Example one
The invention provides a low gray scale optimization PWM algorithm of an LED driving chip, which comprises the following steps:
step S31, display 2 needed by N-bit gray scale dataNGCLK is equally distributed to 2LIn each sub-period, each sub-period includes 2HGCLK, N, H, L are positive integers, N ═ H + L;
step S32, setting an optimization level Opt which is a non-negative integer, and setting the minimum width of PWM in each sub-period to be 2Opt；
Step S33, when the gray scale data is 2L+OptAt integral multiple of (2), the gray data is equally distributed to 2LIn a sub-period;
step S34, when the gray scale data is not 2L+OptAt integral multiple of (d), the highest bit to the (L + Opt +1) th bit of the binary gray scale data is multiplied by 2L+OptThe obtained product is equally distributed to 2LIn a sub-period;
step S35, dividing the low (L + Opt) bit of the binary gray scale data by 2 based on the step S34OptThe obtained quotient is marked as D, and the remainder is marked as R;
step S36, based on step S35, allocating R GCLKs in the 0 th sub-period;
step S37, on the basis of the steps S35 and S36, dividing the residual gray values into D groups, each group being 2OptGCLK assigned to sub-periods 1 to 2 in units of groupsL1 is mentioned above.
As shown in fig. 4, L is set to 5 and Opt is set to 2, i.e.: break up the whole display period into 2532 sub-periods, each sub-period comprising several GCLK periods; the optimization level is 2, and the minimum width of PWM in each sub-period is 4 GCLK periods. Distributing gray values 1, 2 and 3 in the 0 th sub-period; when the gray value is 4, the 0 th sub-period has no PWM pulse, and 4 GCLK are distributed in the 1 st sub-period; when the gray value is 5, 6 and 7, 1, 2 and 3 GCLK are distributed in the 0 th sub-period, and the 1 st sub-period keeps 4 GCLK; when the gray value is 8, the 0 th sub-period has no PWM pulse, and 4 GCLK are respectively distributed in the 1 st and 17 th sub-periods; when the gray value is 9, 10 and 11, 1, 2 and 3 GCLK are distributed in the 0 th sub-period, and the 1 st and 17 th sub-periods keep 4 GCLK; when the gray value is 12, the 0 th sub-period has no PWM pulse, and 4 GCLK are respectively distributed in the 1 st, 9 th and 17 th sub-periods; when the gray value is 13, 14 and 15, 1, 2 and 3 GCLK are distributed in the 0 th sub-period, and 4 GCLK are kept in the 1 st, 9 th and 17 th sub-periods; when the gray level is 16, the 0 th sub-period has no PWM pulse, and 4 GCLK pulses are allocated to the 1 st, 9 th, 17 th and 25 th sub-periods, respectively. And when the gray value continues to increase, the distribution is carried out according to the above rule. When the gray value is larger than 128, 4 GCLK are distributed in each sub-period, and the rest GCLK is distributed in the 0 th sub-period, and then the distribution is still carried out according to the same rule. It can be found that the gray values are uniformly distributed in the whole display period by 4 groups, only the pulse width of the 0 th sub-period may be 1, 2 or 3 GCLK, the analog channel of the LED driving chip has sufficient time to identify the high and low edges of the digital signal and complete the level conversion, and the display effect under the low gray condition is greatly improved.
According to the algorithm provided by the invention, except the 0 th sub-period, the PWM width of each of the other sub-periods is always equal to 2OptThe simulation channel can identify the effective channel opening time and correctly complete the level conversion. Meanwhile, except for the 0 th sub-period, the pulse width with different channel phase differences of PWM pulse width is always 2OptAnd the channels are not easy to be coupled and interfered, so that the display effect of each channel is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (9)
1. An LED driving chip low gray scale optimization PWM algorithm is characterized by comprising the following steps:
step 1, 2 required for displaying N-bit gray scale dataNGCLK is equally distributed to 2LIn each sub-period, each sub-period includes 2HGCLK, N, H, L are positive integers, N ═ H + L;
step 2, setting an optimization grade Opt, wherein the Opt is a non-negative integer, and setting the minimum width of the PWM in each sub-period to be 2Opt；
Step 3, when the gray data is 2L+OptAt integral multiple of (2), the gray data is equally distributed to 2LIn a sub-period;
step 4, when the gray data is not 2L+OptAt integral multiple of (d), the highest bit to the (L + Opt +1) th bit of the binary gray scale data is multiplied by 2L+OptThe obtained product is equally distributed to 2LIn a sub-period;
step 5, on the basis of step 4, dividing the low (L + Opt) bit of the binary gray scale data by 2OptThe obtained quotient is marked as D, and the remainder is marked as R;
step 6, distributing R GCLK in the 0 th sub-period based on the step 5;
step 7, on the basis of the steps 5 and 6, dividing the residual gray values into D groups, wherein each group 2 is provided withOptGCLK assigned to sub-periods 1 to 2 in units of groupsL1 is mentioned above.
2. The LED driving chip low gray scale optimized PWM algorithm according to claim 1, wherein said step 2 comprises: when Opt takes 0, 1, 2, 3 … … respectively, the minimum PWM width in each sub-period is 1, 2, 4, 8 … … respectively; only when the PWM width in one sub-period reaches the minimum PWM width will the gray value be allocated in the other sub-periods.
3. As claimed inThe LED driving chip low gray scale optimization PWM algorithm of 2 is characterized in that gray scale data are evenly distributed to 2 in the step 3LSub-periods, each sub-period being assigned 2OptPositive integer multiples of GCLK; when L is 5, the whole display period is broken up to 2532 sub-periods; the optimization level Opt is set to 2, and the minimum width of PWM in each sub-period is 224 GCLK; if the gray scale data is 128, it is equal to 25+2Is 2L+OptThe integral multiple of the gray scale data, the gray scale data are evenly distributed into 32 sub-periods, and each sub-period has 4 GCLK; if the gradation data is 256, it is equal to 25+2X 2 is 2L+OptThe integer multiple of (2), the gray scale data is equally distributed into 32 sub-periods, 8 GCLK per sub-period.
4. The LED driving chip low gray scale optimized PWM algorithm according to claim 3, wherein in said step 4, when L is 5, the whole display period is broken up to 2532 sub-periods; the optimization level Opt is set to 2, and the minimum width of PWM in each sub-period is 224 GCLK; if the gray data is 129, the highest bit of the binary system is taken to the 8 th bit (2' b0..001), and the result is 128 after being multiplied by 128, and the 128 gray values are evenly distributed into 32 sub-periods, each of which is 4 GCLK.
5. The LED driving chip low gray scale optimized PWM algorithm according to claim 4, wherein in said step 5, when L is 5, the whole display period is scattered to 2532 sub-periods; the optimization level Opt is set to 2, and the minimum width of PWM in each sub-period is 224 GCLK; if the gray scale data is 9, dividing the binary lower 7 bits (7' b0001001) by 4 to obtain a quotient D of 2 and a remainder R of 1; if the gray scale data is 131, the binary lower 7 bits (7' b0000010) are divided by 4 to obtain a quotient D equal to 0 and a remainder R equal to 3.
6. The LED driver chip low gray scale optimized PWM algorithm of claim 5, wherein in step 6, the remainder R GCLK of step 5 is assigned to the 0 th sub-period.
7. The LED driver chip low gray scale optimized PWM algorithm of claim 6, wherein in said step 7, the groups are distributed to sub-period 1 to sub-period 2LThe principle of allocation in-1 is: the spacing between groups is made equal as much as possible to improve the display uniformity.
8. The LED driving chip low gray scale optimized PWM algorithm according to any one of claims 1-7, wherein by increasing the minimum width of PWM pulse in low gray, the problem of low gray mottle and uneven display caused by difficulty in identifying effective display time of an analog channel in low gray can be effectively solved.
9. The LED driver chip low gray scale optimized PWM algorithm of any one of claims 1-7, wherein the remainder R in step 6 is fully distributed in the 0 th sub-period, so that the PWM width of each of the remaining sub-periods is always equal to 2OptThe integral multiple of the channel interference is reduced, and the display effect of each channel is improved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010941254.9A CN112116892A (en) | 2020-09-09 | 2020-09-09 | Low-gray-scale optimization PWM algorithm for LED driving chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010941254.9A CN112116892A (en) | 2020-09-09 | 2020-09-09 | Low-gray-scale optimization PWM algorithm for LED driving chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112116892A true CN112116892A (en) | 2020-12-22 |
Family
ID=73803117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010941254.9A Pending CN112116892A (en) | 2020-09-09 | 2020-09-09 | Low-gray-scale optimization PWM algorithm for LED driving chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112116892A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112992050A (en) * | 2021-02-23 | 2021-06-18 | 中科芯集成电路有限公司 | Constant-current LED driving chip composite SPWM algorithm |
| CN113793564A (en) * | 2021-09-16 | 2021-12-14 | 中科芯集成电路有限公司 | OSPWM algorithm for multi-interval optimization |
| CN115497417A (en) * | 2022-09-30 | 2022-12-20 | 南京浣轩半导体有限公司 | Mini-LED compensation method, equipment and medium based on decimal gray correction |
| CN115909957A (en) * | 2022-11-14 | 2023-04-04 | 成都利普芯微电子有限公司 | LED display screen driving chip and LED display screen |
| CN115985230A (en) * | 2023-01-09 | 2023-04-18 | 中科芯集成电路有限公司 | Screen-off energy-saving control method for constant-current LED display driving chip |
| CN116153241A (en) * | 2022-02-16 | 2023-05-23 | 北京大学 | Sectional PWM control method for LED display driving chip |
| CN116524851A (en) * | 2023-07-04 | 2023-08-01 | 集创北方(成都)科技有限公司 | LED display driving method, LED display driving chip and device and display panel |
| CN117894270A (en) * | 2024-03-14 | 2024-04-16 | 集创北方(珠海)科技有限公司 | LED display driving method and device, chip and electronic equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104050928A (en) * | 2014-07-10 | 2014-09-17 | 杭州士兰微电子股份有限公司 | Gray level display driving method and device for LED display |
| CN109147653A (en) * | 2018-10-09 | 2019-01-04 | 中国电子科技集团公司第五十八研究所 | A kind of LED drive chip display control OS-PWM method |
| CN109903721A (en) * | 2019-04-10 | 2019-06-18 | 中国电子科技集团公司第五十八研究所 | A kind of LED drive circuit based on frequency multiplication OS-PWM algorithm |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Full-color LED driver chip and driving method with multi-line scanning and high refresh rate |
| CN111326102A (en) * | 2020-03-11 | 2020-06-23 | 深圳市德普微电子有限公司 | Gray scale display control method |
| CN111489685A (en) * | 2020-01-22 | 2020-08-04 | 南京浣轩半导体有限公司 | Multi-line scanning L ED gray scale switching display method and system |
| CN111489688A (en) * | 2020-04-29 | 2020-08-04 | 四川遂宁市利普芯微电子有限公司 | Method for optimizing low-gray display effect |
-
2020
- 2020-09-09 CN CN202010941254.9A patent/CN112116892A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104050928A (en) * | 2014-07-10 | 2014-09-17 | 杭州士兰微电子股份有限公司 | Gray level display driving method and device for LED display |
| CN109147653A (en) * | 2018-10-09 | 2019-01-04 | 中国电子科技集团公司第五十八研究所 | A kind of LED drive chip display control OS-PWM method |
| CN109903721A (en) * | 2019-04-10 | 2019-06-18 | 中国电子科技集团公司第五十八研究所 | A kind of LED drive circuit based on frequency multiplication OS-PWM algorithm |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Full-color LED driver chip and driving method with multi-line scanning and high refresh rate |
| CN111489685A (en) * | 2020-01-22 | 2020-08-04 | 南京浣轩半导体有限公司 | Multi-line scanning L ED gray scale switching display method and system |
| CN111326102A (en) * | 2020-03-11 | 2020-06-23 | 深圳市德普微电子有限公司 | Gray scale display control method |
| CN111489688A (en) * | 2020-04-29 | 2020-08-04 | 四川遂宁市利普芯微电子有限公司 | Method for optimizing low-gray display effect |
Non-Patent Citations (1)
| Title |
|---|
| 曾忠: "《基于SPWM的二次优化与实现》", 《电子与封装》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112992050A (en) * | 2021-02-23 | 2021-06-18 | 中科芯集成电路有限公司 | Constant-current LED driving chip composite SPWM algorithm |
| CN113793564A (en) * | 2021-09-16 | 2021-12-14 | 中科芯集成电路有限公司 | OSPWM algorithm for multi-interval optimization |
| CN113793564B (en) * | 2021-09-16 | 2023-04-25 | 中科芯集成电路有限公司 | Multi-region optimization OSPWM algorithm |
| CN116153241A (en) * | 2022-02-16 | 2023-05-23 | 北京大学 | Sectional PWM control method for LED display driving chip |
| CN116153241B (en) * | 2022-02-16 | 2023-08-22 | 北京大学 | A segmented PWM control method for LED display driver chip |
| CN115497417A (en) * | 2022-09-30 | 2022-12-20 | 南京浣轩半导体有限公司 | Mini-LED compensation method, equipment and medium based on decimal gray correction |
| CN115497417B (en) * | 2022-09-30 | 2023-07-18 | 南京浣轩半导体有限公司 | Mini-LED compensation method, device and medium based on decimal gray scale correction |
| CN115909957A (en) * | 2022-11-14 | 2023-04-04 | 成都利普芯微电子有限公司 | LED display screen driving chip and LED display screen |
| CN115985230A (en) * | 2023-01-09 | 2023-04-18 | 中科芯集成电路有限公司 | Screen-off energy-saving control method for constant-current LED display driving chip |
| CN116524851A (en) * | 2023-07-04 | 2023-08-01 | 集创北方(成都)科技有限公司 | LED display driving method, LED display driving chip and device and display panel |
| CN116524851B (en) * | 2023-07-04 | 2023-10-24 | 集创北方(成都)科技有限公司 | LED display driving method, LED display driving chip and device and display panel |
| CN117894270A (en) * | 2024-03-14 | 2024-04-16 | 集创北方(珠海)科技有限公司 | LED display driving method and device, chip and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112116892A (en) | Low-gray-scale optimization PWM algorithm for LED driving chip | |
| CN109147653B (en) | LED driving chip display control OS-PWM method | |
| CN112992050B (en) | Composite SPWM algorithm of constant-current LED driving chip | |
| CN113793564B (en) | Multi-region optimization OSPWM algorithm | |
| CN112037710B (en) | PWM algorithm for opening channels of multi-channel LED driving chip in time-sharing manner | |
| WO2021147170A1 (en) | Multi-row scanning led grayscale switching display method and system | |
| JP4676418B2 (en) | Driving device and driving method for liquid crystal display device | |
| CN114550644B (en) | Constant-current LED driving chip self-adaptive SPWM algorithm based on gray data | |
| CN102054434B (en) | Light-emitting diode (LED) display system and method having pulse scattering mode | |
| KR100778487B1 (en) | Modulation circuit, image display device and modulation method using same | |
| CN111653235A (en) | LED driving chip display control distributed PWM algorithm | |
| CN112466250A (en) | LED driving chip display algorithm with low gray and high brush | |
| CN115938287A (en) | High-refresh-rate display method and system for LED (light emitting diode) at low gray level | |
| EP2549464B1 (en) | Low grayscale enhancing method for field emission display based on subsidiary driving technique | |
| CN113436574B (en) | LED driving chip algorithm for optimizing low-gray display effect | |
| CN116189608A (en) | Method for eliminating phenomena of caterpillar and smear and improving refresh rate of LED display screen | |
| CN104123913A (en) | LED (Light-Emitting Diode) scanning method | |
| CN115866838A (en) | LED driving pulse modulation method and circuit | |
| TW202347307A (en) | Grayscale distribution control circuit, LED display driver chip and LED display panel wherein the grayscale distribution control circuit is configured to generate an SPWM signal to prevent a specific grayscale that will cause pitting from being directly displayed on the LED display panel | |
| CN115884466A (en) | LED driving pulse modulation method and circuit | |
| CN116416914A (en) | Image display method, device and system and nonvolatile storage medium | |
| CN103077682B (en) | LED (Light-Emitting Diode) display screen pulse control method capable of eliminating dynamic false contour | |
| CN110599945B (en) | LED display device and driving method thereof | |
| CN220420231U (en) | Driving circuit of light-emitting diode device | |
| CN107507559B (en) | A method of promoting LED high color depth display effect |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201222 |