CN103310735A - Display control method and display control system both supportive of gray level expansion - Google Patents
Display control method and display control system both supportive of gray level expansion Download PDFInfo
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Abstract
The invention belongs to the technical field of display control and provides a display control method and a display control system both supportive of gray level expansion. The method and the system are characterized in that in a synchronous control card, each to-be-displayed gray datum with display accuracy of n1 is processed to acquire a group of gray data, with the display accuracy of n2 respectively, corresponding to each to-be-displayed gray datum, n2 is equal to or smaller than n1 and n2 is smaller than 16, and in 2n1 gray clock signal cycles, duty ratio represented by a group of gray data with the display accuracy of n2 respectively is identical with that needed to be demonstrated by the to-be-demonstrated gray data with the display accuracy of n1. By the method, data transmission quantity between the synchronous control card and a driving chip is lowered to n2 digits from 16 digits currently, so that data transmission rate between the synchronous control card and the driving chip is increased by 16/n2 times, the frequency upper limit of gray clock signals is improved, line scanning frequency is increased, and image refreshing rate is increased.
Description
Technical field
The invention belongs to the display control technology field, relate in particular to display control method, system and synchro control card, driving chip that a kind of LED of being mainly used in shows the control aspect and supports the gray shade scale expansion.
Background technology
In the demonstration control field of LED display, (Pulse Width Modulation, PWM) mode realize the adjusting to each LED luminosity to adopt pulse-length modulation.Specifically, be in fixing display cycle, by regulate LED bright/time ratio that goes out, reach the purpose of LED brightness regulation, and when LED was bright, what flow through was the electric current of fixing, light wavelength can not change, and avoids the change color problem of LED under different electric currents.
Show the typical structure of the display control program of LED display as Fig. 1, it comprises the driving chip of synchro control card and some cascades.Wherein, serial data transmission line SDI is a level on line, data clock line DCLK, grayscale clock line GCLK and latch line LE and be respectively bridging line; Serial data transmission line SDI cooperates with data clock line DCLK, obtains required demonstration data, latchs line LE and cooperates with the data clock line, obtains required steering order.Particularly, synchro control card and the display data transmissions process that drives between the chip are: the synchro control cartoon is crossed serial data transmission line SDI transmits gradation data from certain precision to connected driving chip, after the display data transmissions of arbitrary port finishes in driving chip, the gradation data of this port is latched, so repeatedly, up to the equal end of transmission of the gradation data of all of the port and after latching, gradation data to integral body latchs, and the gradation data that latchs is used for output and shows.
In the prior art, adopt the transmission mode of 16 gradation datas between synchro control card and the driving chip, that is to say, the synchro control calorie requirement sends 16 gradation datas to driving chip in a display cycle, even if when the accuracy requirement that shows data is lower than 16, still need to make the transmission figure place of gradation data remain unchanged in low level benefit 0.And for the dynamic screen that shows dynamic menu, its picture refreshing rate depends primarily on line feed sweep frequency (that is: go frequency sweep rate), then show one fixedly during the demonstration data of display precision at dynamic screen, need be after the basic cycle of a pwm signal of each row complete demonstration of LED, could enter a new line, at this moment, dynamically the capable frequency sweep rate of screen can be expressed as:
Wherein, F
FrameBe row frequency sweep rate, F
GCLKBe the frequency of grayscale clock signal, n is display precision, and m is the number of scanning lines.As seen, if the gradation data transmission quantity is big, in order to finish the transmission of gradation data, the number of cycles of desired data clock signal DCLK is many, frequency is fast, and then limited the upper frequency limit of grayscale clock signal GCLK, reduce capable frequency sweep rate, and then reduced the refresh rate of picture.For example, the driving chip number of supposing cascade is 12, every drives chip and has 16 to drive port, display precision is 10, then in 1024 grayscale clock cycles (i.e. display cycle), synchro control card and the volume of transmitted data that drives between the chip are: gradation data figure place 16 * driving chip number 12 * each drives the driving port number 16=3072 of chip, that is to say, the frequency of data clock signal DCLK need reach three times of grayscale clock signal GCLK, in practice, the maximum frequency of data clock signal DCLK and grayscale clock signal GCLK is 30MHz, and in this example, the frequency of maximum data clock signal DCLK is 30MHz, and the frequency of maximum grayscale clock signal GCLK is restricted to 10MHz, dynamically shield for 8 scannings, the frequency sweep rate of then going is:
Refresh rate is lower, and display precision is more high, because the not lifting of volume of transmitted data between synchro control card and the driving chip, so refresh rate is lower, has reduced user experience.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of display control method of supporting the gray shade scale expansion, be intended to solve in the prior art, owing to adopt the transmission mode of 16 gradation datas between synchro control card and the driving chip, data quantity transmitted is big, cause the refresh rate of picture low, the problem of user experience difference.
The embodiment of the invention is achieved in that a kind of display control method of supporting the gray shade scale expansion, said method comprising the steps of:
The synchro control card is that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the gradation data serial that each group display precision is respectively n2 exported to the driving chip, described n1 and n2 are positive integer, and n2≤n1, n2＜16 are 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the corresponding display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical;
Described synchro control card sends grayscale clock signal, data clock signal, port latch instruction, whole latch instruction and counting instruction to described driving chip;
Described driving chip is the gradation data of n2 in the sample precision of driving chip output of described synchro control card or upper level connection of the rising edge of described data clock signal and/or negative edge;
The gradation data that the described port latch instruction that the described synchro control card of described driving chips incorporate sends, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain, it is luminous to drive each light-emitting component.
Another purpose of the embodiment of the invention is to provide a kind of synchro control card, and described synchro control card comprises:
Data processing module, handle for the gradation data to be shown that to each display precision is n1, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the gradation data serial that each group display precision is respectively n2 exported to the driving chip, described n1 and n2 are positive integer, and n2≤n1, n2＜16 are 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the corresponding display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical;
Transport module is used for sending grayscale clock signal, data clock signal, port latch instruction, whole latch instruction and counting instruction to described driving chip.
Another purpose of the embodiment of the invention is to provide a kind of driving chip, and described driving chip comprises:
Sampling module, being used for the sample precision of driving chip output of described synchro control card or upper level connection of the rising edge of the data clock signal that sends at the synchro control card and/or negative edge is the gradation data of n2, described n2 is positive integer, and n2＜16;
Driver module is used for the gradation data that the port latch instruction that sends in conjunction with described synchro control card, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain, and it is luminous to drive each light-emitting component.
Another purpose of the embodiment of the invention is to provide a kind of display control program of supporting the gray shade scale expansion, and described system comprises the driving chip that the synchro control card is connected with cascade, and described synchro control card is aforesaid synchro control card.
Display control method and the system of the support gray shade scale expansion that the embodiment of the invention proposes are in the synchro control card, be that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and n2≤n1 and n2＜16 are arranged, simultaneously 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical.By this method, synchro control card and the volume of transmitted data that drives between the chip are the n2 position from existing 16 potential drops, therefore, synchro control card and the message transmission rate that drives between the chip have promoted 16/n2 doubly, thereby in terms of existing technologies, improve the upper frequency limit of grayscale clock signal GCLK, improved capable frequency sweep rate, and then improved the refresh rate of picture.
Description of drawings
Fig. 1 is in the prior art, the exemplary block diagram of the display control program of LED display.
Fig. 2 is the process flow diagram of the display control method of the support gray shade scale expansion that provides of the embodiment of the invention one;
Fig. 3 is in the embodiment of the invention one, and the synchro control card is treated the detail flowchart that the display gray scale data are handled;
Fig. 4 is in the embodiment of the invention one, drives the luminous detail flowchart of each luminescence unit of chip drives;
Fig. 5 is the process flow diagram of the gradation data output intent that provides of the embodiment of the invention two;
Fig. 6 is in the embodiment of the invention two, treats the detail flowchart that the display gray scale data are handled;
Fig. 7 is the process flow diagram of the driving method that provides of the embodiment of the invention three;
Fig. 8 is in the embodiment of the invention three, drives the luminous detail flowchart of each luminescence unit;
Fig. 9 is the structural drawing of the synchro control card that provides of the embodiment of the invention four;
Figure 10 is the structural drawing of data processing module among Fig. 9;
Figure 11 is the structural drawing of the driving chip that provides of the embodiment of the invention five;
Figure 12 is a kind of circuit diagram of the driving chip that provides of the embodiment of the invention five;
Figure 13 is a kind of circuit diagram that triggers among Figure 12 along processing unit;
Figure 14 is a kind of circuit diagram of n2 bit shift buffer among Figure 12;
Figure 15 is a kind of circuit diagram of n2 digit counter among Figure 12;
Figure 16 is a kind of circuit diagram of Pwm controller among Figure 12;
Figure 17 is a kind of circuit diagram of comparer among Figure 12;
Figure 18 is a kind of circuit diagram of instruction control unit among Figure 12;
Figure 19 is a kind of circuit diagram of gradation data storage unit among Figure 12.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
Problem at the prior art existence, the present invention proposes a kind of display control method of supporting the gray shade scale expansion, in this method, the synchro control card is that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and n2≤n1 and n2＜16 are arranged, simultaneously 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical.Describe implementation of the present invention in detail below in conjunction with embodiment:
Embodiment one
The embodiment of the invention one has proposed a kind of display control method of supporting the gray shade scale expansion, as shown in Figure 2, comprising:
Step S1: the synchro control card is that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the driving chip is exported in the gradation data serial that each group display precision is respectively n2.Wherein, n1 and n2 are positive integer, and n2≤n1, and n2＜16 are simultaneously 2
N1Individual grayscale clock signal is in the cycle, dutycycle and the corresponding display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical, that is to say that the gray shade scale that the gradation data that one group of display precision is respectively n2 characterizes and corresponding display precision are that the gray shade scale that the gradation data to be shown of n1 characterizes is consistent.
Further, in the embodiment of the invention one, as shown in Figure 3, step S1 can comprise again:
Step S11: the display precision n1 of the gradation data to be shown that the synchro control card is more current and the magnitude relationship between the display precision n2.
Step S12: according to the comparative result of step S11, if display precision n1 equals display precision n2, then the synchro control card is directly exported to the driving chip with current gradation data to be shown.
Step S13: according to the comparative result of step S11, greater than display precision n2, then the synchro control card extracts the low n1-n2 bit data D1 in the current gradation data to be shown, and the decimal data K of computational data D1 correspondence as if display precision n1.
Step S14: according to the comparative result of step S11, greater than display precision n2, then the synchro control card extracts the high n2 bit data D2 in the current gradation data to be shown as if display precision n1.
Step S15: whether everybody is 1 to synchro control card judgment data D2, is execution in step S18 then, otherwise execution in step S16.
Step S16: the synchro control card adds 1 with data D2, obtains data D3.
Step S17: the synchro control card is K data D3, and 2
N1-n2The driving chip is exported in-K data D2 serial.
Step S18: the synchro control card is with 2
N1-n2The driving chip is exported in individual data D2 serial.
According to above-mentioned steps S13 to step S18, if current gradation data to be shown is B
N1-1B
N1-2B
0, the dutycycle of the required demonstration of this n1 bit binary data is Duty1=(B
N1-1*2
N1-1+ B
N1-2*2
N1-2+ ... + B
0*2
0)/2
N1Behind step S13, the data D1 of extraction is B
N1-n2-1B
N1-n2-2B
0, the decimal data K=(B of data D1 correspondence
N1-n2-1*2
N1-n2-1+ B
N1-n2-2*2
N1-n2-2+ ... + B
0*2
0); Afterwards, the data D2 that extracts through step S14 is B
N1-1B
N1-2B
N1-n2Afterwards, if n1-n2 binary data among the data D2 is 1, execution in step S18 then is with 2
N1-n2The driving chip is exported in individual data D2 serial, if n1-n2 binary data among the data D2 is not 1 entirely, and execution in step S16 then, obtaining data D3 is B
N1-1B
N1-2B
N1-n2+ 1, and after obtaining data D3, execution in step S17, the synchro control card is with K data D3 and 2
N1-n2The driving chip is exported in-K data D2 serial.Wherein, data D3 is 2
N2Individual grayscale clock signal is in the cycle, and effectively the grayscale clock number of cycles is B
N1-1*2
N2-1+ B
N1-2*2
N2-2+ ... + B
N1-n2*2
0+ 1, data D2 is 2
N2Individual grayscale clock signal is in the cycle, and effectively the grayscale clock number of cycles is B
N1-1*2
N2-1+ B
N1-2*2
N2-2+ ... + B
N1-n2*2
0, like this, 2
N1Individual grayscale clock is in the cycle, and effectively the grayscale clock number of cycles is K*(B
N1-1*2
N2-1+ B
N1-2*2
N2-2+ ... + B
N1-n2*2
0+ 1)+(2
N1-n2-K) * (B
N1-1*2
N2-1+ B
N1-2*2
N2-2+ ... + B
N1-n2*2
0), the dutycycle of its representative is Duty2=(B
N1-1*2
N1-1+ B
N1-2*2
N1-2+ ... + B
0*2
0)/2
N1, namely satisfy Duty2=Duty1.
For instance, suppose n1=16, n2=10, current gradation data to be shown is 3a35, and binary form is shown 0011101000110101, and the dutycycle of its required displaying is Duty1=14901/65536.Behind step S13, the data D1 of extraction is 110101, the decimal number K=53 of data D1 correspondence; Afterwards, through step S14, the data D2 of extraction is 0011101000; Because the binary data among the data D2 is not 1 entirely, so execution in step S16, obtaining data D3 is 0011101000+1=0011101001; Afterwards, execution in step S17, the synchro control card is exported to the driving chip with 53 data D3 and 11 data D2 serial.Wherein, among the data D3 2
10Individual grayscale clock signal is in the cycle, and effectively the grayscale clock signal number of cycles is Lighth=233, and data D2 is 2
10Individual grayscale clock signal is in the cycle, and effectively the grayscale clock signal number of cycles is Lightl=232, like this, and 2
16Individual grayscale clock signal is in the cycle, and effectively the grayscale clock signal number of cycles is Lighth+Lightl=53*233+11*232=14901, and the dutycycle Duty2=14901/65536 of its representative satisfies Duty2=Duty1.
Step S2: the synchro control card sends grayscale clock signal, data clock signal, port latch instruction, whole latch instruction and counting instruction to driving chip.
Step S3: driving chip is the gradation data of n2 in the precision of the driving chip output of the rising edge of data clock signal and/or negative edge sample-synchronous control card or upper level connection.
In the embodiment of the invention one, driving chip can be the gradation data of n2 in the precision of the driving chip output of the rising edge of data clock signal or negative edge sample-synchronous control card or upper level connection, can be the gradation data of n2 in the precision of the driving chip output of the rising edge of data clock signal and the equal sample-synchronous control card of negative edge or upper level connection also.
Step S4: drive the gradation data that the port latch instruction of chips incorporate synchro control card transmission, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain, it is luminous to drive each light-emitting component.
Because in actual applications, the number optimum of the driving chip of cascade is 12, each port number that drives chip is generally 16, if drive chip waste that then can cause resource above 12, therefore, in the embodiment of the invention one, in order to have transmitted the gradation data of corresponding number at grayscale clock signal in the cycle, need, n2 is preferably 10, so that when being improved, having optimum cascade, refresh rate drives the chip number.Certainly, under concrete condition, n2 gets 9 or 11.
Further, in the embodiment of the invention one, as shown in Figure 4, step S4 can comprise again:
Step S41: drive chip according to the counting instruction, grayscale clock signal is counted.
Step S42: drive chip according to the port latch instruction, 2
N1-n2Individual respectively by 2
N2In the display cycle that the individual grayscale clock signal cycle is formed, one group of that sampling is obtained, corresponding with the light-emitting component of corresponding port gradation data latchs, and each light-emitting component respectively corresponding respectively organize gradation data all latch finish after, according to whole latch instruction, each group gradation data is carried out integral body latch.
Step S43: drive chip and generate original gray scale conditioning signal according to whole latch instruction.
Step S44: drive chip original gray scale conditioning signal and the gradation data of respectively organizing that latchs are compared respectively, respectively organized gradation data pulse width modulating signal and the output of correspondence respectively, luminous to drive each light-emitting component.
The display control method of the support gray shade scale expansion that the embodiment of the invention one proposes is in the synchro control card, be that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and n2≤n1 and n2＜16 are arranged, simultaneously 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical.By this method, synchro control card and the volume of transmitted data that drives between the chip are the n2 position from existing 16 potential drops, and therefore, synchro control card and the message transmission rate that drives between the chip have promoted 16/n2 doubly.And if further, driving chip is the gradation data of n2 in the precision of the driving chip output of the rising edge of data clock signal and the equal sample-synchronous control card of negative edge or upper level connection, then with respect to existing clock sampling mode, synchro control card and the message transmission rate that drives between the chip further can be promoted 2 times, that is to say that optimum can promote message transmission rate 16/n2*2 doubly.Thereby in terms of existing technologies, improved the upper frequency limit of grayscale clock signal GCLK, further improved capable frequency sweep rate, and then improved the refresh rate of picture.For instance, suppose that the frequency of maximum data clock signal DCLK and the frequency of the grayscale clock signal GCLK of maximum are 30MHz, the driving chip number of cascade is 12, every drives chip and has 16 to drive port, display precision is 10, then in 1024 grayscale clock cycles (i.e. display cycle), synchro control card and the volume of transmitted data that drives between the chip are: gradation data figure place 10 * driving chip number 12 * each drives the driving port number 16=1920 of chip.Drive chip and at the rising edge of data clock signal and the equal sampling precision of negative edge be 10 gradation data, the data clock signal number of cycles that then needs is 1920/2=960, because 960 are less than grayscale clock number of cycles 1024, therefore the upper frequency limit of grayscale clock signal GCLK can reach maximal value 30MHz, dynamically shield for 8 scannings, row frequency sweep rate can reach:
With respect to existing 1.2KHz, refresh rate gets a promotion, and has improved user experience.
Embodiment two
The embodiment of the invention two has proposed a kind of gradation data output intent, as shown in Figure 5, comprising:
Step S5: be that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the driving chip is exported in the gradation data serial that each group display precision is respectively n2.
Wherein, n1 and n2 are positive integer, and n2≤n1, and n2＜16 are simultaneously 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the corresponding display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical.
Further, as shown in Figure 6, step S5 comprises again:
Step S51: the display precision n1 of more current gradation data to be shown and the magnitude relationship between the display precision n2.
Step S52: according to the comparative result of step S51, if display precision n1 equals display precision n2, then directly current gradation data to be shown is exported to the driving chip.
Step S53: according to the comparative result of step S51, if display precision n1 greater than display precision n2, then extracts the low n1-n2 bit data D1 in the current gradation data to be shown, and the decimal data K of computational data D1 correspondence.
Step S54: according to the comparative result of step S51, if display precision n1 greater than display precision n2, extracts the high n2 bit data D2 in the current gradation data to be shown.
Whether everybody is 1 to step S55: judgment data D2, is execution in step S58 then, otherwise execution in step S56.
Step S56: D2 adds 1 with data, obtains data D3.
Step S57: with K data D3, and 2
N1-n2The driving chip is exported in-K data D2 serial.
Step S58: with 2
N1-n2The driving chip is exported in individual data D2 serial.
Step S6: send grayscale clock signal, data clock signal, port latch instruction, whole latch instruction and counting instruction to driving chip.
Embodiment three
The embodiment of the invention three has proposed a kind of driving method, as shown in Figure 7, comprising:
Step S7: the precision in the driving chip output of the rising edge of data clock signal and/or negative edge sample-synchronous control card or upper level connection is the gradation data of n2, and wherein, n2 is positive integer, and n2＜16.
Step S8: the gradation data that port latch instruction, whole latch instruction, counting instruction, grayscale clock signal and the sampling that sends in conjunction with the synchro control card obtains, it is luminous to drive each light-emitting component.
Further, as shown in Figure 8, step S8 comprises again:
Step S81: according to the counting instruction, grayscale clock signal is counted.
Step S82: according to the port latch instruction, 2
N1-n2Individual respectively by 2
N2In the display cycle that the individual grayscale clock signal cycle is formed, one group of that sampling is obtained, corresponding with the light-emitting component of corresponding port gradation data latchs, and each light-emitting component respectively corresponding respectively organize gradation data all latch finish after, according to whole latch instruction, each group gradation data is carried out integral body latch.
Step S83: generate original gray scale conditioning signal according to whole latch instruction.
Step S84: original gray scale conditioning signal and the gradation data of respectively organizing that latchs are compared respectively, respectively organized gradation data pulse width modulating signal and the output of correspondence respectively, luminous to drive each light-emitting component.
Embodiment four
The embodiment of the invention four has proposed a kind of synchro control card, as shown in Figure 9, for convenience of explanation, only shows the part relevant with the embodiment of the invention four.
Specifically, the synchro control card that the embodiment of the invention four proposes comprises: data processing module 11, handle for the gradation data to be shown that to each display precision is n1, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the driving chip is exported in the gradation data serial that each group display precision is respectively n2; Transport module 12 is used for sending grayscale clock signal, data clock signal, port latch instruction, whole latch instruction and counting instruction to driving chip.
Wherein, n1 and n2 are positive integer, and n2≤n1, and n2＜16 are simultaneously 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the corresponding display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical.
Further, as shown in figure 10, data processing module 11 can comprise: comparison sub-module 111 is used for the display precision n1 of more current gradation data to be shown and the magnitude relationship between the display precision n2; First output sub-module 112 is used for the comparative result according to comparison sub-module 111, if display precision n1 equals display precision n2, then directly current gradation data to be shown is exported to the driving chip; First calculating sub module 113 is used for the comparative result according to step comparison sub-module 111, if display precision n1 greater than display precision n2, then extracts the low n1-n2 bit data D1 in the current gradation data to be shown, and the decimal data K of computational data D1 correspondence; Extract submodule 114, be used for the comparative result according to comparison sub-module 111, if display precision n1 greater than display precision n2, extracts the high n2 bit data D2 in the current gradation data to be shown; Judge submodule 115, whether everybody is 1 to be used for judgment data D2; Second calculating sub module 116 is used for when everybody of judgement submodule 115 judgment data D2 is not 1 entirely, and D2 adds 1 with data, obtains data D3; Second output sub-module 117 is used for K data D3, and 2
N1-n2The driving chip is exported in-K data D2 serial; The 3rd output sub-module 118 is used for when everybody of judgement submodule 115 judgment data D2 is 1, with 2
N1-n2The driving chip is exported in individual data D2 serial.
Embodiment five
The embodiment of the invention five has proposed a kind of driving chip, as shown in figure 11, for convenience of explanation, only shows the part relevant with the embodiment of the invention five.
Specifically, the driving chip that the embodiment of the invention five proposes comprises: sampling module 21, and the precision that is used in the driving chip output of the rising edge of data clock signal and/or negative edge sample-synchronous control card or upper level connection is the gradation data of n2, wherein, n2 is positive integer, and n2＜16; Driver module 22 is used for the gradation data that the port latch instruction that sends in conjunction with the synchro control card, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain, and it is luminous to drive each light-emitting component.
Further, show a kind of circuit of the driving chip that the embodiment of the invention five provides as Figure 12.At this moment, drive chip and comprise data clock interface DCLK', serial data input interface SDI', grayscale clock interface GCLK', latch the output that interface LE', serial data output interface SDO' and at least one connect light-emitting component respectively and drive interface OUT, this light-emitting component is light emitting diode preferably.Wherein, data clock interface DCLK', serial data input interface SDI', grayscale clock interface GCLK', latch interface LE' and connect the synchro control card respectively, serial data output interface SDO' connects the serial data input interface SDI' that next stage drives chip.Sampling module 21 comprises: trigger along processing unit 212, be used for receiving the data clock signal that the synchro control card sends by data clock interface DCLK', and export the monostable pulse at rising edge and/or the negative edge of data clock signal.Driver module 22 comprises: n2 bit shift buffer 211, and being used for according to the precision that triggers along the driving chip output of the monostable impulse sampling synchro control card of processing unit 212 outputs or upper level connection is the gradation data of n2; Instruction control unit 221 is used for receiving port latch instruction, whole latch instruction and the counting instruction that the synchro control card sends by latching interface LE'; N2 digit counter 222 is used for receiving the grayscale clock signal that the synchro control card sends by grayscale clock interface GCLK', and according to the counting instruction, grayscale clock signal is counted; At least one gradation data storage unit 223 is used for according to the port latch instruction, 2
N1-n2Individual respectively by 2
N2In the display cycle that the individual grayscale clock signal cycle is formed, n2 bit shift buffer 211 samplings one group of gradation data that obtain, corresponding with the light-emitting component of corresponding port is latched, and each light-emitting component respectively corresponding respectively organize gradation data all latch finish after, according to whole latch instruction, each group gradation data is carried out integral body latch; Pwm controller 224 is used for generating original gray scale conditioning signal according to whole latch instruction; The comparer 225 that at least one connects one to one with gradation data storage unit 223 respectively, the gradation data of respectively organizing that latchs for original gray scale conditioning signal and gradation data storage unit 223 with Pwm controller 224 generations compares respectively, respectively organized gradation data pulse width modulating signal and the output of correspondence respectively, luminous to drive each light-emitting component.
Further, when n2=10, as shown in figure 13, triggering can comprise along processing unit 212: the input end of first delay circuit, 2121, the first delay circuits 2121 connects data clock interface DCLK'; The XOR gate XOR of two inputs, the input pin of XOR gate XOR connects the output terminal of first delay circuit 2121, and another input pin of XOR gate XOR connects data clock interface DCLK', and the output pin of XOR gate XOR connects n2 bit shift buffer 211.
Wherein, first delay circuit 2121 when each rising edge/negative edge of data clock DCLK' moves, all produces time-delay for generation of time-delay.Data clock DCLK' through first delay circuit 2121 after, relative data clock DCLK' is itself, and is only variant when rising edge/negative edge, therefore, DCLK'_2 is the output high impulse when data clock DCLK' rising edge/negative edge, all the other times are 0.
Further, when n2=10, as shown in figure 14, n2 bit shift buffer 211 can comprise: 10 D flip-flop DFF that are connected in series, export after being used for converting parallel data to via the serial data of serial data input interface SDI' input.Wherein, the data input pin D of first D flip-flop DFF connects serial data input interface SDI', and the clock pin CLK of 10 D flip-flop DFF connects the output pin of XOR gate XOR jointly.
Further, when n2=10, as shown in figure 15, n2 digit counter 222 can comprise: 10 D flip-flop DFF1 that are connected in series, 10 totalizer FA that are connected in series, the data input pin D of each D flip-flop DFF1 connect a corresponding totalizer FA's and output pin, the clock pin CLK of 10 D flip-flop DFF1 that are connected in series connects grayscale clock interface GCLK' jointly.N2 digit counter 222 is used for counting via the grayscale clock of grayscale clock interface GCLK' input.It is that unit adds 1 one by one that its Q9～Q0 was changed to 1 grayscale clock GCLK' cycle.For example Q9～Q0 variation is expressed as with 16 systems: 000 → 001 → 002 → ... 3FE → 3FF → 000.
Further, when n2=10, as shown in figure 16, Pwm controller 224 can comprise: 9 and a door AND, 1 impact damper BUF, 7 rejection gate NOR, 1 not gate INV; 8 are divided other first input end to be connected 222,8 of n2 digit counters with a door AND to divide other second input end to connect the output pin of corresponding rejection gate NOR with an AND; 1 first input end with door AND is connected the output terminal that 222,1 second input ends with door AND of n2 digit counter are connected not gate INV, and the input end of not gate INV is connected n2 digit counter 222 jointly with the input end of impact damper BUF; 9 are connected comparer 225 jointly with the door output terminal of AND and the output terminal of impact damper BUF.Pwm controller 224 Pwm controllers 224 are used for the output of n2 digit counter 222 is handled, and are convenient to the comparison of comparer 225.
Further, when n2=10, as shown in figure 17, comparer 225 can comprise: 10 and door AND1 and 1 or an OR.10 with the door AND1 divide other first input end to be connected gradation data storage unit 223,10 with the door AND1 divide other second input end to be connected Pwm controller 224,10 are divided other output terminal to be connected with door AND1 or the input end of door OR, or the output terminal OUT of door OR is as output driving interface OUT.Comparer 225 is used for the output of gradation data storage unit 223 and the output of Pwm controller 224 are compared, and obtains the dutycycle corresponding with gradation data.What deserves to be explained is that the realization of Pwm controller 224 and comparer 225 can change because of the PWM mode of OUT output.
Further, when n2=10, as shown in figure 18, instruction control unit 221 can comprise: the totalizer FA1 of 4 series connection, the D flip-flop DFF2 of 4 series connection, D flip-flop DFF3, D flip-flop DFF4, second delay circuit 2211 and the 3rd delay circuit 2212, not gate U1 and not gate U2.Wherein, the data input pin D that is connected 1 corresponding D flip-flop DFF2 with output pin S of each totalizer FA1; The reset pin RST of D flip-flop DFF2 all connects and latchs interface LE', and the clock pin CLK of D flip-flop DFF2 all connects the output pin DCLK'_2 of XOR gate XOR; The data output pin Q3 of last D flip-flop DFF2 among the D flip-flop DFF2 of 4 series connection of data input pin D connection of D flip-flop DFF3, the clock pin CLK of D flip-flop DFF3 connects the output terminal of not gate U1, interface LE' is latched in the input end connection of not gate U1, and the data output pin Q of D flip-flop DFF3 connects the reset pin RST of D flip-flop DFF3 by second delay circuit 2211; The data output pin Q3 of last D flip-flop DFF2 among the D flip-flop DFF2 of 4 series connection of data input pin D connection of D flip-flop DFF4, the clock pin CLK of D flip-flop DFF4 connects the output terminal of not gate U2, interface LE' is latched in the input end connection of not gate U2, and the data output pin Q of D flip-flop DFF4 connects the reset pin RST of D flip-flop DFF4 by the 3rd delay circuit 2212.
Instruction control unit 221 is used for the rising of data clock DCLK' in the high level time that latchs interface LE' and/or negative edge counting according to count results, are instructed accordingly.This circuit is realized is that the data of OUT port latch (latchi) and integral body latchs (latch_global), be respectively applied to store certain port data, latch all of the port data.
Further, when n2=10, as shown in figure 19, gradation data storage unit 223 can comprise: the latch LATCH1 of 10 series connection, the latch LATCH of 10 series connection.The clock pin CLK of each latch LATCH1 connects the data output pin Q of D flip-flop DFF3 jointly, the clock pin CLK of each latch LATCH connects the data output pin Q of D flip-flop DFF4 jointly, and the data output pin Q of each latch LATCH1 connects the data input pin D of corresponding 1 latch LATCH.Gradation data storage unit 223 is used for the gradation data in the n2 bit shift buffer 211 is latched into corresponding port.Latchi latchs corresponding to the data of OUTi port, and latch_global is the data latch clock of all of the port.
Embodiment six
The embodiment of the invention six has proposed a kind of display control program of supporting the gray shade scale expansion, comprises as above embodiment four described synchro control cards and embodiment five described driving chips.
In sum, display control method and the system of the support gray shade scale expansion that the present invention proposes are in the synchro control card, be that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and n2≤n1 and n2＜16 are arranged, simultaneously 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical.By this method, synchro control card and the volume of transmitted data that drives between the chip are the n2 position from existing 16 potential drops, and therefore, synchro control card and the message transmission rate that drives between the chip have promoted 16/n2 doubly.And if further, driving chip is the gradation data of n2 in the precision of the driving chip output of the rising edge of data clock signal and the equal sample-synchronous control card of negative edge or upper level connection, then with respect to existing clock sampling mode, synchro control card and the message transmission rate that drives between the chip further can be promoted 2 times, that is to say that optimum can promote message transmission rate 16/n2*2 doubly.Thereby in terms of existing technologies, improved the upper frequency limit of grayscale clock signal GCLK, further improved capable frequency sweep rate, and then improved the refresh rate of picture.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a display control method of supporting the gray shade scale expansion is characterized in that, said method comprising the steps of:
The synchro control card is that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the gradation data serial that each group display precision is respectively n2 exported to the driving chip, described n1 and n2 are positive integer, and n2≤n1, n2＜16, at 2n1 grayscale clock signal in the cycle, dutycycle and the corresponding display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical;
Described synchro control card sends grayscale clock signal, data clock signal, port latch instruction, whole latch instruction and counting instruction to described driving chip;
Described driving chip is the gradation data of n2 in the sample precision of driving chip output of described synchro control card or upper level connection of the rising edge of described data clock signal and/or negative edge;
The gradation data that the described port latch instruction that the described synchro control card of described driving chips incorporate sends, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain, it is luminous to drive each light-emitting component.
2. the display control method of support gray shade scale as claimed in claim 1 expansion, it is characterized in that, described synchro control card is that the gradation data to be shown of n1 is handled to each display precision, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the step that drives chip is exported in the gradation data serial that each group display precision is respectively n2 further be may further comprise the steps:
The display precision n1 of the gradation data to be shown that described synchro control card is more current and the magnitude relationship between the display precision n2;
If described display precision n1 equals described display precision n2, then described synchro control card is directly exported to described driving chip with described current gradation data to be shown;
If described display precision n1 is greater than described display precision n2, then described synchro control card extracts the low n1-n2 bit data D1 in the described current gradation data to be shown, and calculates the decimal data K of described data D1 correspondence;
If described display precision n1 is greater than described display precision n2, then described synchro control card extracts the high n2 bit data D2 in the described current gradation data to be shown;
Described synchro control card judges whether everybody is 1 to described data D2, is then with 2
N1-n2Described driving chip is exported in individual described data D2 serial, otherwise described data D2 is added 1, obtains data D3, and with K described data D3 and 2
N1-n2Described driving chip is exported in-K described data D2 serial.
3. the display control method of support gray shade scale as claimed in claim 1 expansion, it is characterized in that, the gradation data that the described port latch instruction that the described synchro control card of described driving chips incorporate sends, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain drives the luminous step of each light-emitting component and further may further comprise the steps:
Described driving chip instructs according to described counting, and described grayscale clock signal is counted;
Described driving chip is according to described port latch instruction, 2
N1-n2Individual respectively by 2
N2In the display cycle that the individual described grayscale clock signal cycle is formed, one group of that sampling is obtained, corresponding with the light-emitting component of corresponding port gradation data latchs, and each light-emitting component respectively corresponding respectively organize gradation data all latch finish after, according to described whole latch instruction, each group gradation data is carried out integral body latch;
Described driving chip generates original gray scale conditioning signal according to described whole latch instruction;
Described driving chip compares described original gray scale conditioning signal and the gradation data of respectively organizing that latchs respectively, is respectively organized gradation data pulse width modulating signal and the output of correspondence respectively, and is luminous to drive described each light-emitting component.
4. as the display control method of each described support gray shade scale expansion of claim 1 to 3, it is characterized in that described n2 is 10.
5. a synchro control card is characterized in that, described synchro control card comprises:
Data processing module, handle for the gradation data to be shown that to each display precision is n1, obtain the gradation data that the one group display precision corresponding with each gradation data to be shown is respectively n2, and the gradation data serial that each group display precision is respectively n2 exported to the driving chip, described n1 and n2 are positive integer, and n2≤n1, n2＜16 are 2
N1Individual grayscale clock signal is in the cycle, and dutycycle and the corresponding display precision that one group of display precision is respectively the gradation data representative of n2 is that the dutycycle of the required displaying of gradation data to be shown of n1 is identical;
Transport module is used for sending grayscale clock signal, data clock signal, port latch instruction, whole latch instruction and counting instruction to described driving chip.
6. synchro control card as claimed in claim 5 is characterized in that, described n2 is 10, and described data processing module comprises:
Comparison sub-module is used for the display precision n1 of more current gradation data to be shown and the magnitude relationship between the display precision n2;
First output sub-module is used for the comparative result according to described comparison sub-module, if described display precision n1 equals described display precision n2, then directly described current gradation data to be shown is exported to described driving chip;
First calculating sub module, be used for the comparative result according to described comparison sub-module, if described display precision n1 is greater than described display precision n2, then extracts the low n1-n2 bit data D1 in the described current gradation data to be shown, and calculate the decimal data K of described data D1 correspondence;
Extract submodule, be used for the comparative result according to described comparison sub-module, if described display precision n1, extracts the high n2 bit data D2 in the described current gradation data to be shown greater than described display precision n2;
Judge submodule, be used for judging whether everybody is 1 to described data D2;
Second calculating sub module, be used for judging described data D2 when described judgement submodule everybody when being not 1 entirely, described data D2 is added 1, obtain data D3;
Second output sub-module is used for a described data D3, and 2
N1-n2Described driving chip is exported in-K described data D2 serial;
The 3rd output sub-module, be used for judging described data D2 when described judgement submodule everybody when being 1, with 2
N1-n2Described driving chip is exported in individual described data D2 serial.
7. one kind drives chip, it is characterized in that described driving chip comprises:
Sampling module, being used for the sample precision of driving chip output of described synchro control card or upper level connection of the rising edge of the data clock signal that sends at the synchro control card and/or negative edge is the gradation data of n2, described n2 is positive integer, and n2＜16;
Driver module is used for the gradation data that the port latch instruction that sends in conjunction with described synchro control card, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain, and it is luminous to drive each light-emitting component.
8. driving chip as claimed in claim 7, it is characterized in that, described driving chip comprises the data clock interface, serial data input interface, the grayscale clock interface that connect described synchro control card respectively, latchs interface, connect the serial data output interface that next stage drives the serial data input interface of chip, and at least one output that connects light-emitting component respectively drives interface, and described n2 is 10;
Described sampling module comprises:
Triggering is used for receiving the data clock signal that described synchro control card sends by described data clock interface along processing unit, and exports the monostable pulse at rising edge and/or the negative edge of described data clock signal;
N2 bit shift buffer, being used for according to described triggering is the gradation data of n2 along the precision of the driving chip output of the described synchro control card of described monostable impulse sampling of processing unit output or upper level connection;
Described driver module comprises:
Instruction control unit is used for receiving described port latch instruction, whole latch instruction and the counting instruction that described synchro control card sends by the described interface that latchs;
The n2 digit counter is used for receiving the grayscale clock signal that described synchro control card sends by described grayscale clock interface, and according to described counting instruction, described grayscale clock signal is counted;
At least one gradation data storage unit is used for according to described port latch instruction, 2
N1-n2Individual respectively by 2
N2In the display cycle that the individual grayscale clock signal cycle is formed, described n2 bit shift buffer sampling one group of gradation data that obtain, corresponding with the light-emitting component of corresponding port is latched, and each light-emitting component respectively corresponding respectively organize gradation data all latch finish after, according to described whole latch instruction, each group gradation data is carried out integral body latch;
Pwm controller is used for generating original gray scale conditioning signal according to described whole latch instruction;
The comparer that at least one connects one to one with described gradation data storage unit respectively, the gradation data of respectively organizing that latchs for described original gray scale conditioning signal and described gradation data storage unit with described Pwm controller generation compares respectively, respectively organized gradation data pulse width modulating signal and the output of correspondence respectively, luminous to drive each light-emitting component.
9. display control program of supporting gray shade scale expansion, described system comprises the driving chip that the synchro control card is connected with cascade, it is characterized in that, described synchro control card is as claim 5 or 6 described synchro control cards.
10. the display control program of support gray shade scale as claimed in claim 9 expansion, it is characterized in that, described driving chip connect respectively the synchro control card data clock interface, serial data input interface, grayscale clock interface, latch interface, connect the serial data output interface that next stage drives the serial data input interface of chip, and at least one output that connects light-emitting component respectively drives interface, and described driving chip also comprises:
Sampling module, being used for the sample precision of driving chip output of described synchro control card or upper level connection of the rising edge of the data clock signal that sends at the synchro control card and/or negative edge is the gradation data of n2, described n2 is 10;
Driver module is used for the gradation data that the port latch instruction that sends in conjunction with described synchro control card, whole latch instruction, counting instruction, grayscale clock signal and sampling obtain, and it is luminous to drive each light-emitting component;
Described sampling module comprises:
Triggering is used for receiving the data clock signal that described synchro control card sends by described data clock interface along processing unit, and exports the monostable pulse at rising edge and/or the negative edge of described data clock signal;
N2 bit shift buffer, being used for according to described triggering is the gradation data of n2 along the precision of the driving chip output of the described synchro control card of described monostable impulse sampling of processing unit output or upper level connection;
Described driver module comprises:
Instruction control unit is used for receiving described port latch instruction, whole latch instruction and the counting instruction that described synchro control card sends by the described interface that latchs;
The n2 digit counter is used for receiving the grayscale clock signal that described synchro control card sends by described grayscale clock interface, and according to described counting instruction, described grayscale clock signal is counted;
At least one gradation data storage unit is used for according to described port latch instruction, 2
N1-n2Individual respectively by 2
N2In the display cycle that the individual grayscale clock signal cycle is formed, described n2 bit shift buffer sampling one group of gradation data that obtain, corresponding with the light-emitting component of corresponding port is latched, and each light-emitting component respectively corresponding respectively organize gradation data all latch finish after, according to described whole latch instruction, each group gradation data is carried out integral body latch;
Pwm controller is used for generating original gray scale conditioning signal according to described whole latch instruction;
The comparer that at least one connects one to one with described gradation data storage unit respectively, the gradation data of respectively organizing that latchs for described original gray scale conditioning signal and described gradation data storage unit with described Pwm controller generation compares respectively, respectively organized gradation data pulse width modulating signal and the output of correspondence respectively, luminous to drive each light-emitting component.
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