CN201788499U - LED scanning control chip device - Google Patents
LED scanning control chip device Download PDFInfo
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- CN201788499U CN201788499U CN2010202926670U CN201020292667U CN201788499U CN 201788499 U CN201788499 U CN 201788499U CN 2010202926670 U CN2010202926670 U CN 2010202926670U CN 201020292667 U CN201020292667 U CN 201020292667U CN 201788499 U CN201788499 U CN 201788499U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
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Abstract
本实用新型公开了一种LED扫描控制芯片装置，该LED扫描控制芯片装置包括输出电流量调节器、恒流源、计数器、同步控制器、十六位位移缓存器、状态缓存器、比较器和缓冲存储器等模块。有益效果：本实用新型采用一种新型的基于FPGA的扫描控制芯片装置，通过设置同步控制器、计数器、位移缓存器、缓冲存储器及比较器，使得本芯片与外围电路、显示面板及计算机构成的LED大屏幕显示系统，实现LED显示屏的256级灰度显示，在简化系统硬件结构的前提下取得清晰稳定的画面显示。
The utility model discloses an LED scanning control chip device, which comprises an output current regulator, a constant current source, a counter, a synchronous controller, a sixteen-bit displacement register, a state register, a comparator and Buffer memory and other modules. Beneficial effects: the utility model adopts a novel scanning control chip device based on FPGA, and by setting a synchronous controller, a counter, a displacement register, a buffer memory and a comparator, the chip and the peripheral circuit, the display panel and the computer are formed. The LED large-screen display system realizes the 256-level grayscale display of the LED display screen, and obtains a clear and stable picture display under the premise of simplifying the system hardware structure.
Description
Technical field
The utility model relates to LED display and semi-conductor chip field, relates in particular to a kind of LED scanning control chip device.
Background technology
LED(light emitting diode) display screen is made of light emitting diode matrix.Light emitting diode (LED) is a kind of current control device, have advantages such as brightness height, volume is little, monochromaticity good, response speed is fast, driving is simple, the life-span is long, therefore the information release tasks of the real-time of the competent various occasions of energy, diversity, dynamic has obtained widespread use.Wherein, the LED giant-screen is to be combined by led array, realize literal by certain control method, image, picture, video, the clear broadcast of signals such as TV, all adopted the form of standard cell block on its structure, promptly adopt 8*16,16*16,16*32,24*24 or 32*32 display pixel fluorescent tube constitutes a unit module, each module forms independently electron scanning function, control function, memory function, and constitute an independent subsystem with this, and then connect and compose complete some matrix LED giant-screen with each standard source and communication driver part, add certain computer controlled member made, just constituted the whole LED display system after having the multimedia card of digitizing component output or DVI card and power supply memory communication driver part.
See also Fig. 1, core wherein is a LED scanning control chip device, how want to check on it controls, must know its gray scale scanning principle: for high grade grey level LED large screen display, the layered approach of gray scale is the key of Video Controller design, because the luminosity of LED and the fluorescent lifetime in the scan period are approximated to direct ratio, so the realization of gray shade scale promptly adopts modulation duty cycle to realize normally by the fluorescent lifetime of control LED and the ratio of scan period.Supposing that the display gray scale number of degrees is N, is t because gray level is 1 pixel in the correspondence time of lighting of screen body, thereby gray level is that data presentation time of i is it after the gray scale linear modulation, and the data presentation time that gray level is the highest is (N-1) * td.Common consideration is to finish in td once the reading of storer data line, and to be the cycle simultaneously with td be driven into the screen body with the data line of reading carries out gray scale and show.Since have N number of greyscale levels, so be frame-scan period: T=n*t*m,
Screen body display efficiency: p=(N-1) * t*m/T=(N-1)/N, setting video data input rate is Vi, it is Vo that storer is read speed, owing to must finish once reading of data line in the storage unit in the time at t, so Vo/Vi 〉=h/ (t*n) is arranged, establish λ and be storer and read ratio with input rate, i.e. λ=Vo/Vi, λ 〉=h/ (t*n)=h*N*m/ (T*n), for guaranteeing the steady display of image, the scanning frame frequency must be enough high, establishes F 〉=Fo, T≤To then, (To=1/Fo).Fo is the acceptable scanning frame frequency of human eye (Fo 〉=60), λ 〉=h*N*m/ (To*n); T=To/ (N*m).For 256 grades of gray scale full screen scannings, it is conflicting that high number of greyscale levels, high scanning frame frequency and low storer are read speed, obtain high number of greyscale levels, just must improve the read-out speed of storer, perhaps reduce vertical sweep frequency, when number of greyscale levels is higher, being difficult to reach the three with present integrated circuit realization level takes into account, one of solution is to adopt parallel organization in a large number, but one times of cost of the every minimizing of sweep frequency just increases by one times nearly, and the complexity of circuit also can increase to some extent; Another kind method is suitably to sacrifice the compromise of screen body display efficiency in the hope of frame frequency and speed, adopts λ=1, t=h/16, and promptly storer is read speed and is equaled the data input rate, and demonstration basic time unit is 1/16 of a line period.Gray scale scanning is realized by the method that gradation data step-by-step timesharing is shown, be that computer screen image is when exporting (each 8bit of red, green, blue) with every pixel 24bit, the not coordination of the bit byte by giving every kind of color distributes the different demonstration time to reach the purpose that gray scale shows, as the corresponding 1/16 row demonstration time of lowest order (the 8th), the 7th 1/8 row demonstration time of correspondence,, second 4 row demonstration time of correspondence, corresponding 8 row demonstration times of most significant digit.Screen volume data update time is unit with the line period, and lowest order corresponding update time is 1 line time, wherein shows 1/16 line time, in all the other 15/16 line times, produces blanking signal by control circuit and carries out blanking, and all the other positions roughly the same.
Summary of the invention
The technical matters that the utility model mainly solves provides a kind of LED scanning control chip device of importing based on eight bit parallels of FPGA, 256 grades of gray scales that can realize LED display show, obtain steady and audible picture display effect under the prerequisite of simplified system hardware configuration.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of LED scanning control chip device is provided, comprises output current regulator, constant current source, counter, isochronous controller, sixteen bit bit shift register, status register, comparer and buffering storer; Described output current regulator has first input end, second input end and output terminal, described counter has first input end, second input end and output terminal, described isochronous controller has input end, first output terminal, second output terminal and the 3rd output terminal, described sixteen bit bit shift register has first input end, second input end, the 3rd input end, four-input terminal, first output terminal, second output terminal and the 3rd output terminal, described memory buffer has input end and output terminal, and described comparer has first input end, second input end and output terminal; The first input end of described output current regulator connects the outer meeting resistance that is used to set output current, second input end of described output current regulator connects first output terminal of described status register, and the output terminal of described output current regulator connects the control end of constant current source; The first input end of described counter connects the GTG clock signal, and second input end of described counter connects the output terminal of isochronous controller, and the output terminal of described counter connects the first input end of described comparer; The input end of described isochronous controller connects the data strobe signal, first output terminal of described isochronous controller connects second input end of described counter, second output terminal of described isochronous controller connects the first input end of described status register, and the 3rd output terminal of described isochronous controller connects described sixteen bit bit shift register the 3rd input end; The first input end of described sixteen bit bit shift register connects data clock signal, the second input end input serial data of described sixteen bit bit shift register, the 3rd input end of described sixteen bit bit shift register connects the 3rd output terminal of isochronous controller, second output terminal of the four-input terminal connection status buffer of described sixteen bit bit shift register, second input end of the first output terminal connection status buffer of described sixteen bit bit shift register, second output terminal of described sixteen bit bit shift register connects the input end of memory buffer, the 3rd output terminal output serial data of described sixteen bit bit shift register; The input end of described memory buffer connects second output terminal of sixteen bit bit shift register, and the output terminal of described memory buffer connects second input end of described comparer; The output terminal of the first input end linkage counter of described comparer, second input end of described comparer connects the input end of memory buffer, and the output terminal of described comparer connects constant current source.
The beneficial effects of the utility model are: its circuit complexity of a large amount of employing parallel organizations and the higher defective of cost that are different from prior art, perhaps sacrifice chip performance and try to achieve the defective of effect, the utility model adopts a kind of novel based on the FPGA(field programmable gate array) the scanning control chip device, by isochronous controller is set, counter, bit shift register, memory buffer and comparer, make this chip and peripheral circuit, the LED large screen display system that display panel and computing machine constitute, 256 grades of gray scales that realize LED display show, obtain steady and audible picture display effect under the prerequisite of simplified system hardware configuration.
Description of drawings
Fig. 1 is the LED display system architectures block scheme of background technology.
Fig. 2 is the functional block diagram of the LED scanning control chip device of the utility model embodiment.
Fig. 3 is the control circuit figure of the LED scanning control chip device of the utility model embodiment.
Embodiment
By describing technology contents of the present utility model, structural attitude in detail, realized purpose and effect, give explanation below in conjunction with embodiment and conjunction with figs. are detailed.
See also Fig. 2, the utility model LED scanning control chip device comprises output current regulator, constant current source, counter, isochronous controller, sixteen bit bit shift register, sixteen bit LED misdata processing module, status register, comparer and buffering storer;
Described output current regulator has first input end, second input end and output terminal, the first input end of described output current regulator connects the outer meeting resistance that is used to set output current, second input end of described output current regulator connects first output terminal of described status register, and the output terminal of described output current regulator connects the control end of constant current source;
Described counter has first input end, second input end and output terminal, the first input end of described counter connects the GTG clock signal, second input end of described counter connects the output terminal of isochronous controller, and the output terminal of described counter connects the first input end of described comparer;
Described isochronous controller has input end, first output terminal, second output terminal and the 3rd output terminal, the input end of described isochronous controller connects the data strobe signal, first output terminal of described isochronous controller connects second input end of described counter, second output terminal of described isochronous controller connects the first input end of described status register, and the 3rd output terminal of described isochronous controller connects described sixteen bit bit shift register;
Described sixteen bit bit shift register has first input end, second input end, the 3rd input end, four-input terminal, the 5th input end, first output terminal, second output terminal and the 3rd output terminal, the first input end of described sixteen bit bit shift register connects data clock signal, the second input end input serial data of described sixteen bit bit shift register, the 3rd input end of described sixteen bit bit shift register connects the 3rd output terminal of isochronous controller, second output terminal of the four-input terminal connection status buffer of described sixteen bit bit shift register, the 5th input end of described sixteen bit bit shift register connects the output terminal of sixteen bit LED misdata processing module, second input end of the first output terminal connection status buffer of described sixteen bit bit shift register, second output terminal of described sixteen bit bit shift register connects the input end of memory buffer, the 3rd output terminal output serial data of described sixteen bit bit shift register;
The input end of described memory buffer connects second output terminal of sixteen bit bit shift register, and the output terminal of described memory buffer connects second input end of described comparer;
Described comparer has first input end, second input end and output terminal, the output terminal of the first input end linkage counter of described comparer, second input end of described comparer connects the input end of memory buffer, and the output terminal of described comparer connects constant current source;
The input end of described sixteen bit LED misdata processing module connects constant current source, and the output terminal of described sixteen bit LED misdata processing module connects the 5th input end of sixteen bit bit shift register.
The quantity of described memory buffer is identical with the quantity of the quantity of described comparer and described constant current source, can or be 16 multiple for 16.
Described counter is 12 or 16 digit counters.
The utility model embodiment realizes like this from vain to 256 grades of black gray-scale Control, this control chip has 16 bit serial input ports with clock synchronization, include 16 bit shift buffers and 16 bit data latchs, can be shifted and latch 16 bit serial data.When circuit was started working, 16 bit serial data were squeezed under the effect of shift clock pulse in the offset buffer module of chip, and 16 shift registers are contained in its inside, were shifted after 16 times, and data will output to next chip from the SDO of this chip; 16 16 bit data of gained of will being shifted simultaneously are input in the GTG mapped buffer storer, this moment is as long as the output control signal is low, provide the capable gating signal of row of the same name and make its output open, each row can begin to export constant current, simultaneously 12 digit counters begin the gray level clock is counted, and when the gray-scale value of being stored in count value and this row comparer equated, i.e. end was exported in the constant current of these row, thereby realize that corresponding LED shows the control of time, i.e. dutycycle control.If adopt 10 these indicative control unit cascade driving LED display screens, then parallel always displacement just can be finished the transmission of first line data for 160 times.
Utilization VerilogHDL writes code and with the Modelsim simulation software this circuit code is compiled emulation, can see under the control of control ends such as control end enable, rsel, bc_ena, latch, can realize control according to different demands to different gray scales and brightness, in the gray-scale Control unit, data shift transport to output terminal after having passed through 16 pulses is exported, and has realized the adjustable of 8 row or 16 row outputs; In brightness control unit, can realize the adjustable of output data equally by the value of adjusting enable, bc_ena, latch, thereby realize the function of brilliance control accurately; Equal demonstration time of this row of the same name according to whole transmission times of each several part row of the same name, can obtain the value in line period and row cycle, be i.e. the line number of line period=frame period/scan mode, row cycle=line period/(every row count * part number).For example frame frequency is 120Hz, and then the frame period is 1/120s=8.33ms, is 1,/16 80 row to be divided into 5 16 row according to scan mode, and every row 160 is listed as, and line period is 520.6 μ s like this, and the row cycle is 650.75ns, and the row frequency is 1.54*106Hz.
Each pin of the chip of the utility model embodiment is defined as follows:
GND: the earth terminal of steering logic and drive current.
SDI: the serial data input end that inputs to bit shift register.
DCLK: the input end of data clock signal, the data displacement occurs in the clock rising edge, when LE starts, but input control order.
LE: data are dodged the control input end, cooperate DCLK can assign control command.
OUT0 ~ OUT15: constant current output terminal.
GCLK: GTG clock signal input terminal, GTG show it is by the function that relatively reach Wave-wide regulation controlled electric of GTG clock with the input data.
SDO: the serial data output terminal, the SDI that can be connected to next driver holds.
R-EXT: the input end that connects outer meeting resistance; This outer meeting resistance can be set the output current of all output channels.
The VDD:3.3V/5V power source supply end.
See also Fig. 3, the circuit control end of the utility model embodiment is defined as follows:
Din: data input pin.
Rsel: row selects signal end.
Mode: pattern control end.
Latch: latch signal end.
Clk: clock signal terminal.
Clkh: high level output.
Clkl: low level output.
Enable: enable control end.
Be different from its circuit complexity of a large amount of employing parallel organizations and the higher defective of cost of prior art, perhaps sacrifice chip performance and try to achieve the defective of effect, the utility model adopts a kind of novel scanning control chip device based on FPGA, by isochronous controller, counter, bit shift register, memory buffer and comparer are set, make the LED large screen display system that this chip and peripheral circuit, display panel and computing machine constitute, 256 grades of gray scales that realize LED display show, obtain steady and audible picture and show under the prerequisite of simplified system hardware configuration.
The above only is embodiment of the present utility model; be not so limit claim of the present utility model; every equivalent structure or equivalent flow process conversion that utilizes the utility model instructions and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present utility model.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202926670U CN201788499U (en) | 2010-08-16 | 2010-08-16 | LED scanning control chip device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010202926670U CN201788499U (en) | 2010-08-16 | 2010-08-16 | LED scanning control chip device |
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| CN201788499U true CN201788499U (en) | 2011-04-06 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930349A (en) * | 2010-08-16 | 2010-12-29 | 深圳市洲明科技股份有限公司 | Led scanning control chip |
| CN104900183A (en) * | 2015-04-22 | 2015-09-09 | 深圳市巨能伟业技术有限公司 | Multi-current drive chip used for LED display drive |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Full-color LED driver chip and driving method with multi-line scanning and high refresh rate |
-
2010
- 2010-08-16 CN CN2010202926670U patent/CN201788499U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930349A (en) * | 2010-08-16 | 2010-12-29 | 深圳市洲明科技股份有限公司 | Led scanning control chip |
| CN101930349B (en) * | 2010-08-16 | 2012-01-11 | 深圳市洲明科技股份有限公司 | Led scanning control chip |
| CN104900183A (en) * | 2015-04-22 | 2015-09-09 | 深圳市巨能伟业技术有限公司 | Multi-current drive chip used for LED display drive |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Full-color LED driver chip and driving method with multi-line scanning and high refresh rate |
| CN110277052B (en) * | 2019-06-13 | 2020-08-04 | 华中科技大学 | Full-color LED driver chip and driving method with multi-line scanning and high refresh rate |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20110406 Effective date of abandoning: 20120111 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20110406 Effective date of abandoning: 20120111 |