CN108663862B - Display panel - Google Patents

Abstract

The present invention provides a display panel, which includes a substrate, a scan line, a data line, a thin film transistor, a first insulating layer, a planarization layer and a pixel electrode layer. The scan line is arranged on the substrate and has a concave portion. The data line is arranged on the substrate, and the data line and the scan line are arranged in an interlaced manner. The thin film transistor is arranged on the substrate and has a gate and a drain, the gate is electrically connected to the scan line, and the drain is electrically connected to the data line. The first insulating layer is arranged on the drain and exposes a portion of the drain, wherein the concave portion of the scan line is arranged corresponding to the exposed portion of the drain. The planarization layer is arranged on the first insulating layer. The pixel electrode layer is arranged on the planarization layer and is electrically connected to the exposed portion of the drain.

Description

display panel

This application was filed on February 25, 2014, and the application number is 201410064232.3, a division of a Chinese invention patent application for "display panel and display device"

technical field

The present invention relates to a display panel and a display device including the display panel.

Background technique

With the advancement of science and technology, flat-panel display devices have been widely used in various fields, especially liquid crystal display devices, which have gradually replaced traditional cathode ray tube display devices due to their superior characteristics such as thinness, low power consumption, and no radiation. , and applied to many kinds of electronic products, such as mobile phones, portable multimedia devices, notebook computers, LCD TVs and LCD screens, etc.

A conventional liquid crystal display device includes a thin film transistor substrate. The thin film transistor substrate has a thin film transistor and a pixel electrode disposed on a substrate. In the process, a through hole needs to be etched above the drain electrode of the thin film transistor, and a transparent conductive layer is passed through the inner wall of the through hole to electrically connect the drain electrode of the thin film transistor with the pixel electrode. In addition, the gate electrode of the thin film transistor is electrically connected to a scan line, and the source electrode of the thin film transistor is electrically connected to a data line. When the scan line inputs a scan signal to the gate of the thin film transistor, the data voltage of the data line can be input to the pixel electrode through the source electrode, the drain electrode and the transparent conductive layer by controlling the thin film transistor. Display images.

In addition, the existing polysilicon thin film transistor has a mobility of about 100 cm ² /Vs, but it must be fabricated at a temperature of 450° C. or higher, so it can only be formed on a substrate with high heat resistance, and is not suitable for application Large area or flexible substrates. In addition, although the existing amorphous silicon thin film transistor can be manufactured at a relatively low temperature, about 300° C., since such an amorphous silicon thin film transistor only has a mobility of about 1 cm ² /Vs, it is not suitable for use in High-definition panel. In this regard, some manufacturers propose to use metal oxide semiconductors, such as indium gallium zinc oxide (IGZO), as the channel layer of the thin film transistor.

Although the indium gallium zinc oxide thin film transistor has the advantage of higher mobility than the amorphous silicon thin film transistor, and its process is simpler than that of the crystalline silicon thin film transistor, the indium gallium zinc oxide is very sensitive to light, water and oxygen. sensitive.

In order to protect the channel layer of the thin film transistor, in the prior art, a protective layer (such as silicon dioxide) is disposed on the channel layer of the metal oxide semiconductor to protect the channel layer. As shown in FIG. 1A , which is a schematic diagram of an electrical characteristic curve of a thin film transistor after a protective layer is disposed on the metal oxide semiconductor channel layer. Although a protective layer has been provided to protect the channel layer, after a period of time (or after a heat treatment), as shown in FIG. 1B , the characteristic curve of the thin film transistor still deviates from the original curve in FIG. 1A , so that the thin film transistor The performance of the device is reduced, thereby affecting the display quality of the display panel and the display device.

Therefore, how to provide a display panel and a display device that can have stable thin film transistor performance so that the display panel and the display device have stable display quality has become one of the important issues.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, an object of the present invention is to provide a display panel and a display device which can have a stable thin film transistor performance so that the display panel and the display device have stable display quality.

The technical solution of the present invention is to provide a display panel, which includes a substrate, a scan line, a data line, a thin film transistor, a first insulating layer, a planarization layer and a pixel electrode layer. The scan line is arranged on the substrate and has a concave portion. The data lines are arranged on the substrate, and the data lines and the scan lines are arranged alternately. The thin film transistor is disposed on the substrate and has a gate electrode and a drain electrode, the gate electrode is electrically connected to the scan line, and the drain electrode is electrically connected to the data line. The first insulating layer is disposed on the drain electrode and exposes a part of the drain electrode, wherein the recessed part of the scan line is disposed correspondingly to the exposed part of the drain electrode. The planarization layer is disposed on the first insulating layer. The pixel electrode layer is disposed on the planarization layer and is electrically connected with the exposed portion of the drain electrode.

Description of drawings

FIG. 1A is a schematic diagram of an electrical characteristic curve of a thin film transistor in a conventional thin film transistor substrate when a protective layer is provided on a channel layer of the thin film transistor.

FIG. 1B is a schematic diagram of an electrical characteristic curve of the thin film transistor in the thin film transistor substrate of FIG. 1A after a period of time.

2A is a schematic top view of a thin film transistor substrate of the present invention.

FIG. 2B is an enlarged schematic view of area C of FIG. 2A .

FIG. 2C is a schematic cross-sectional view taken along the section line B-B of FIG. 2B .

FIG. 2D is a partial enlarged schematic view of FIG. 2C .

FIG. 2E is a schematic cross-sectional view of a thin film transistor substrate according to another embodiment.

3A to 3D are schematic diagrams illustrating a method for fabricating the through hole of FIG. 2C .

FIG. 4 is a relative schematic diagram of the data lines and the scan lines and their overlapping positions.

5A is a schematic diagram of an electrical characteristic curve of a thin film transistor when a first sublayer and a second sublayer are disposed on the channel layer of the thin film transistor in the thin film transistor substrate of the preferred embodiment of the present invention.

FIG. 5B is a schematic diagram of an electrical characteristic curve of the thin film transistor in the thin film transistor substrate of FIG. 5A after a period of time.

6 is a schematic cross-sectional view of a display panel according to a preferred embodiment of the present invention.

7 is a schematic cross-sectional view of a display device according to a preferred embodiment of the present invention.

Main component label description

1. 1a: Thin film transistor substrate 11: Gate dielectric layer

12: channel layer 13: first insulating layer

131: First sublayer 132: Second sublayer

14: Planarization layer 15: Second insulating layer

16: Pixel electrode layer 18: Common electrode layer

2: Display panel 3: Display device

A: Alignment film B: Backlight module

B-B: Hatch line BM: Black matrix layer

C: Region D: Drain

E: Electrode layer ES: Etch stop layer

F: Color filter G: Grid

L: Display layer O: Overlap

O1: First opening O2: Second opening

P1: First side wall P2: Second side wall

S: Source S1: Substrate

S2: Counter substrate T: Thin film transistor

U: Recess V1: First through hole

V2: second via w1: first width

w2: second width w3: distance

Detailed ways

The display panel and the display device according to the preferred embodiments of the present invention will be described below with reference to the related drawings, wherein the same elements will be described with the same reference symbols.

The display panel of the preferred embodiment of the present invention is an active matrix liquid crystal display panel, and includes a thin film transistor substrate 1 . The structure of the thin film transistor substrate 1 will be described in detail below.

Please refer to FIGS. 2A to 2D , wherein FIG. 2A is a schematic top view of the thin film transistor substrate 1 , FIG. 2B is an enlarged schematic view of the region C of FIG. 2A , FIG. 2C is a schematic cross-sectional view of the section line B-B of FIG. 2D is a partially enlarged schematic diagram of FIG. 2C . It should be noted that, for the convenience of description, the dimensional relationship (ratio) of the height and width of each element shown in FIGS. 2A to 2D is only a schematic representation, and does not represent an actual dimensional relationship.

As shown in FIG. 2A , the thin film transistor substrate 1 may have a plurality of scan lines, a plurality of data lines and a plurality of pixels (only two scan lines and four data lines are shown in FIG. 2A ). Wherein, the scan lines and the data lines can be staggered to form the pixel arrays. When the scan lines receive a scan signal, the scan lines can be turned on respectively, and a data signal corresponding to each row of pixels is transmitted to the pixels through the data lines, so that the display panel can display images. In FIG. 2A , the data lines are shown as cross-section lines, but in other layouts, the data lines may also be straight lines or other shapes. In addition, the thin film transistor substrate 1 may further have a black matrix layer BM, and the black matrix layer BM is disposed on the scan line to shield the area of the scan line and prevent light leakage of the pixels. Of course, the black matrix layer BM can also be disposed on a pair of facing substrates of the liquid crystal display panel. Here, it is taken as an example that the black matrix layer BM is disposed on the thin film transistor substrate 1 .

As shown in FIG. 2C , the thin film transistor substrate 1 has a substrate S1 , a thin film transistor T, a first insulating layer 13 (shown in FIG. 2D ), a planarization layer 14 , a second insulating layer 15 , and a pixel electrode layer 16 and a common electrode layer 18.

The thin film transistor T is disposed on the substrate S1. In practice, the substrate S1 can be a light-transmitting material for a transmissive display device, such as glass, quartz or the like, plastic, rubber, glass fiber or other polymer materials, preferably a light-transmitting material. Alumino silicate glass substrate. The substrate S1 can also be made of an opaque material for self-luminous or reflective display devices, such as a metal-glass fiber composite board and a metal-ceramic composite board.

The thin film transistor T of this embodiment has a gate G, a gate dielectric layer 11 , a channel layer 12 , a source S and a drain D. The gate G is disposed on the substrate S1, and the material of the gate G can be a single-layer or multi-layer structure composed of metal (eg, aluminum, copper, silver, molybdenum, or titanium) or its alloy. Part of the wires used to transmit the driving signals can be electrically connected to each other by using the structure of the same layer and the same process as the gate G, such as scan lines. The gate dielectric layer 11 is disposed on the gate G, and the gate dielectric layer 11 can be an organic material such as organic silicon oxide compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, Alumina, hafnium oxide, or a multilayer structure of the above materials. The gate dielectric layer 11 needs to completely cover the gate G, and can optionally partially or completely cover the substrate S1.

The channel layer 12 is disposed on the gate dielectric layer 11 relative to the gate G. In practice, the channel layer 12 may comprise, for example, an oxide semiconductor. Wherein, the aforementioned oxide semiconductor includes oxide, and the oxide includes indium, gallium, zinc and tin or one of them, such as Indium Gallium Zinc Oxide (IGZO).

The source electrode S and the drain electrode D are respectively disposed on the channel layer 12, and the source electrode S and the drain electrode D are respectively in contact with the channel layer 12. When the channel layer 12 of the thin film transistor T is not turned on, the two are electrically separated. The material of the source electrode S and the drain electrode D may be a single-layer or multi-layer structure composed of metal (eg, aluminum, copper, silver, molybdenum, or titanium) or its alloy. In addition, some of the wires used for transmitting the driving signals can use the structure of the same layer and the same process as the source S and the drain D, such as data lines.

It is worth mentioning that the source S and the drain D of the thin film transistor T in this embodiment are disposed on the etch stop layer ES, and one end of the source S and the drain D can be self-etched respectively. The opening of the termination layer ES is in contact with the channel layer 12 . The etch stop layer ES may be an organic material such as an organic silicon oxide compound, or a single-layer inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a combination of the above materials. The layer structure is not limited. However, in other embodiments, as shown in FIG. 2E , the source electrode S and the drain electrode D can also be directly disposed on the channel layer 12 without the etch stop layer ES.

2B to FIG. 2D again, the first insulating layer 13 has a first sub-layer 131 and a second sub-layer 132, and the first sub-layer 131 and the second sub-layer 132 are sequentially disposed on the drain electrode D, and cover at least part of the drain D. Here, the first sub-layer 131 is disposed on the drain D and has a first opening O1 with a first width w1, and the second sub-layer 132 has a second opening O2 with a second width w2 located in the first opening O1. On opening O1. The first opening O1 and the second opening O2 may form a first through hole V1, and the second width w2 is greater than the first width w1. In other words, since the second opening O2 of the second sub-layer 132 is larger than the first opening O1 of the first sub-layer 131 , the first through hole V1 of the first insulating layer 13 (the first sub-layer 131 and the second sub-layer 132 ) for a ladder.

较佳者例如为

另外，第二子层132的材料可包含氮化硅或氧化铝(AlxOx)。本实施例是以氮化硅为例，且其厚度可介于

至之间

其中，第二子层132的较佳厚度为

至

之间。The first sub-layer 131 and the second sub-layer 132 may use a deposition rate such as less than thickness to form. The material of the first sub-layer 131 may include silicon oxide (SiOx) or silicon nitride (SiNx). In this embodiment, silicon dioxide (SiO ₂ ) is used as an example, and its thickness can be between between 3000 angstroms

Preferably, for example

In addition, the material of the second sub-layer 132 may include silicon nitride or aluminum oxide (AlxOx). In this embodiment, silicon nitride is used as an example, and its thickness can be between

to between

Wherein, the preferred thickness of the second sub-layer 132 is

to

between.

In practice, the first sub-layer 131 and the second sub-layer 132 can be etched to form openings O1 and O2, respectively. Since the second sub-layer 132 (silicon nitride) is etched away more, the first The sub-layer 131 (silicon oxide) is less etched away, so that the first via V1 can have a stepped shape. In addition, in this embodiment, the first sub-layer 131 has a slope, and the second sub-layer 132 also has a slope. In addition, the first width w1 of the first sub-layer 131 in this embodiment is the smallest width among the first openings O1, and the second width w2 of the second sub-layer 132 is also the smallest width among the second openings O2. In addition, the distance w3 between one side edge of the first sub-layer 131 and the same side edge of the second sub-layer 132 may be, for example, between 0.1 μm (μm) and 0.5 μm (0.1 μm≦distance w3≦0.5 μm).

The planarization layer 14 is disposed on the first insulating layer 13, and has a second through hole V2 on the drain D, and the size of the first through hole V1 and the second through hole V2 can be the same or different, and Unrestricted. Here, the top view shapes of the first through hole V1 and the second through hole V2 are respectively a square shape as an example. The first through hole V1 and the second through hole V2 are partially overlapped and form an overlap O, that is, the first through hole V1 formed by the first opening O1 and the second opening O2 and the planarization layer 14 The projections of the second through holes V2 on the substrate S1 of the thin film transistor substrate 1 are at least partially overlapped with each other, and the area of the overlapping portion O may be between 4 and 49 square micrometers.

In addition, the ratio of the area of the overlapping portion O of the first through hole V1 and the second through hole V2 to the area of the first through hole V1 may be between 0.14 and 0.78, and the ratio of the first through hole V1 and the second through hole V2 The ratio of the area of the overlapping portion O to the area of the second through hole V2 can also be between 0.14 and 0.78. Here, the area can be described by the cross-sectional area or the projected area. For example, the area of the overlapping portion O is 9 square microns. , the area of the first through hole V1 is 36 square micrometers. Compared with the existing technology of etching another through hole in a larger through hole, the area of O where the first through hole V1 and the second through hole V2 overlap is smaller than that of the through hole in the prior art, and there is no Alignment of another via in a large via. In addition, because the area of the overlapping portion O is smaller than the area of the through hole in the prior art, when the black matrix layer BM is arranged on the scanning line, the relative coverage width can be smaller than that in the prior art, so the pixels of the display panel can be increased. opening rate. It is particularly noted that the size of the overlapping position O of the first through hole V1 and the second through hole V2 is between 2 and 8 μm, so as to facilitate subsequent processes.

Hereinafter, please refer to FIGS. 3A to 3D . Here, a method for manufacturing the through hole of FIG. 2C will be described first.

First, as shown in FIG. 3A , a first insulating layer 13 and a planarization layer 14 are deposited on the source electrode S and the drain electrode D in sequence. The first insulating layer 13 has a first sub-layer 131 and a second sub-layer 132 .

Next, as shown in FIG. 3B , a photomask (not shown) is used to perform a lithography etching process to form a second via V2 on the planarization layer 14 and expose the first insulating layer 13 .

Next, as shown in FIG. 3C , a second insulating layer 15 is formed to cover the first insulating layer 13 and the planarizing layer 14 .

Then, as shown in FIG. 3D , the second insulating layer 15 and the first insulating layer 13 are lithographically etched with a mask to form a first through hole V1 to expose the drain electrode D. As shown in FIG.

The shapes of the first through holes V1 and the second through holes V2 may include polygons, circular ovals or irregular shapes, for example. The overlapping situation of the first through hole V1 and the second through hole V2 is preferably that the first through hole V1 and the second through hole V2 are both rectangular, and the overlapping position O of the first through hole V1 and the second through hole V2 is at central part. In this way, there is less problem of alignment of small vias in the existing large vias, and thus will not affect the electrical conduction of the transparent conductive layer in the subsequent process (if the alignment is not good, the transparent conductive layer may be affected. The arrangement of the layers affects the electrical connection between the drain electrode and the pixel electrode).

Referring to FIG. 2C again, the second insulating layer 15 is disposed on the planarization layer 14 , and the pixel electrode layer 16 is disposed on the second insulating layer 15 . Here, the pixel electrode layer 16 is in the shape of a comb. In addition, the pixel electrode layer 16 is filled in the first through hole V1 and the second through hole V2 formed by the first opening O1 and the second opening O2, and can pass through the overlap of the first through hole V1 and the second through hole V2 O is electrically connected to the drain D. The material of the pixel electrode layer 16 may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), cadmium tin oxide (CTO), tin oxide (SnO ₂ ), Or transparent conductive materials such as zinc oxide (ZnO).

In particular, when the insulating layer is etched in the prior art, the sidewalls of the through holes are prone to have right angles or chamfers, and there are breaks. Therefore, when the transparent conductive layer is arranged in the through holes, it is easy to cause disconnection. and affect the yield. However, in the first side wall P1 of the overlapping position O of the first through hole V1 and the second through hole V2, a part of the pixel electrode layer 16 filled in the overlapping position O is located in the first side wall P1, and is in contact with the planarization layer 14. Direct contact (as shown on the right side wall of the via in Figure 2C). In addition, in the second sidewall P2 of the overlapping portion O of the first via V1 and the second via V2 in this embodiment, a part of the second insulating layer 15 filled in the overlapping portion O is located on the second sidewall P2 and In direct contact with the planarization layer 14 (as shown in the left side wall of the through hole in FIG. 2C ), the second insulating layer 15 of the second sidewall P2 can make the insulating layers (second sublayers) located above and below the planarization layer 14 132 is connected with the second insulating layer 15), so the number of possible breakages is less than that of the prior art, and generally the flat layer 15 is relatively smooth after etching, and the two sidewalls have different lamination relationships, making it possible to set pixels When the electrode layer 16 is used, the probability of disconnection is relatively small, which can indirectly improve the yield of the process.

In addition, the common electrode layer 18 is provided between the planarization layer 14 and the second insulating layer 15 . It should be mentioned again that, in other embodiments, as shown in FIG. 4 , since the area of the overlapping position O of the first through hole V1 and the second through hole V2 is smaller than that of the through hole in the prior art, the scanning line is The intersection of adjacent data lines may have a concave portion U (the scan line of the concave portion U is hollowed out), and the concave portion U may be correspondingly disposed at the overlap O of the first through hole V1 and the second through hole V2 (FIG. 4 only shows the first through hole V2). The portion O where the first through hole V1 and the second through hole V2 overlap, the top view shape of the first through hole V1 and the second through hole V2 is not shown). As mentioned above, since the area of the overlapping portion O of the first through hole V1 and the second through hole V2 is smaller than that of the through hole in the prior art, the concave portion U on the scanning line will not be too large to cause disconnection of the scanning line, and Only the line width of the scan line with the recess U is smaller, so that the coupling capacitance between the scan line and the data line can be reduced.

Please refer to FIG. 5A and FIG. 5B , wherein FIG. 5A shows the thin film transistor substrate 1 according to the preferred embodiment of the present invention, when the first sub-layer 131 and the second sub-layer 132 are provided on the channel layer 12 of the thin film transistor T , a schematic diagram of the electrical characteristic curve of the thin film transistor T, and FIG. 5B is a schematic diagram of the electrical characteristic curve of the thin film transistor T after a period of time in the thin film transistor substrate 1 of FIG. 5A . 5A and 5B show four characteristic curves of the thin film transistor T obtained under four different measurement conditions.

It can be found from FIGS. 5A and 5B , through the arrangement of the first sub-layer 131 and the second sub-layer 132 , after a period of time, the change of the curve in FIG. 5B is much smaller than that in FIG. 1B . In addition, the curve change of FIG. 5B is not too different from that of FIG. 5A. In other words, by sequentially disposing the first sub-layer 131 and the second sub-layer 132 on the drain D and the channel layer 12 of the thin film transistor T, the performance of the thin film transistor T can be maintained stable, and thus will not affect the display panel and the display. The display quality of the device.

Next, please refer to FIG. 6 , which is a schematic cross-sectional view of a display panel 2 according to a preferred embodiment of the present invention.

The display panel 2 includes a thin film transistor substrate 1 , a pair of facing substrates S2 and a display layer L. The opposite substrate S2 is disposed opposite to the thin film transistor substrate 1 , and can optionally have an electrode layer E and an alignment film A. Wherein, the opposite substrate S2 can be a material that can transmit light, such as glass, quartz or the like. In practical application, the substrate S1 and the opposite substrate S2 of the thin film transistor substrate 1 can be made of different materials, for example, the opposite substrate S2 uses a potassium glass substrate, and the substrate S1 uses a borate alkali-free glass substrate. In addition, the electrode layer E is disposed on the side of the opposite substrate S2 facing the thin film transistor substrate 1 , and the alignment film A is disposed under the electrode layer E. In addition, a color filter F can also be inserted between the opposite substrate S2 and the electrode layer E for colorized display. In addition, the display layer L is disposed between the thin film transistor substrate 1 and the opposite substrate S2, wherein the display layer can be a liquid crystal layer or an organic light-emitting layer. The thin film transistor substrate 1 has been described in detail above, and will not be repeated here. Of course, the thin film transistor substrate 1 can also be replaced by the thin film transistor substrate 1a of FIG. 2E .

In addition, please refer to FIG. 7 , which is a schematic cross-sectional view of a display device 3 according to a preferred embodiment of the present invention.

The display device 3 includes a display panel 2 and a backlight module B. As shown in FIG. The display panel 2 includes a thin film transistor substrate 1 , a pair of opposing substrates S2 and a display layer L. The thin film transistor substrate 1 has been described in detail above, and will not be repeated here.

The opposite substrate S2 is disposed opposite to the thin film transistor substrate 1 , and optionally has an electrode layer E and an alignment film A. Wherein, the opposite substrate S2 can be a material that can transmit light, such as glass, quartz or the like. In practical application, the substrate S1 and the opposite substrate S2 of the thin film transistor substrate 1 can be made of different materials, for example, the opposite substrate S2 uses a potassium glass substrate, and the substrate S1 uses a borate alkali-free glass substrate. In addition, the electrode layer E is disposed on the side of the opposite substrate S2 facing the thin film transistor substrate 1 , and the alignment film A is disposed under the electrode layer E. In addition, a color filter F can also be inserted between the opposite substrate S2 and the electrode layer E for colorized display. In addition, the display layer L is provided between the thin film transistor substrate 1 and the opposite substrate S2. It should be noted that the source S and the drain D of the thin film transistor T in FIG. 6 and FIG. 7 are disposed on the etch stop layer ES, and one ends of the source S and the drain D are respectively self-etching The openings are in contact with the channel layer 12 . The etch stop layer ES may be an organic material such as an organic silicon oxide compound, or a single-layer inorganic material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a combination of the above materials. layer structure. However, in other embodiments, the source electrode S and the drain electrode D can also be directly disposed on the channel layer 12 and in contact with the channel layer 12 .

In addition, the backlight module B is disposed on the other side of the thin film transistor substrate 1 relative to the opposite substrate S2, and emits light, so that the light passes from the substrate S1 of the thin film transistor substrate 1 through the display layer L, and then exits from the opposite substrate S2. It should be noted that, in this embodiment, the display layer L is a liquid crystal layer, so the backlight module B is used. If the display layer L is an organic light-emitting layer, the backlight module B is not required.

To sum up, in the display panel and the display device according to the present invention, the first insulating layer of the thin film transistor substrate has a first sublayer and a second sublayer, and the first sublayer and the second sublayer are in sequence arranged on the drain of the thin film transistor. The first sub-layer has a first opening with a first width, the second sub-layer has a second opening with a second width on the first opening, and the first opening and the second opening can form a first through hole, and the third The second width may be greater than the first width. In addition, the pixel electrode layer of the thin film transistor substrate is disposed on the second insulating layer, and fills the first through hole to connect to the drain electrode. Therefore, compared with the prior art, the first sub-layer and the second sub-layer are sequentially disposed on the drain electrode of the thin film transistor, so that the performance of the thin film transistor after a period of time can still be maintained stable, so that the display will not be affected. Display quality of panels and display devices.

In addition, in an embodiment of the present invention, the projections of the first through hole formed by the first opening and the second opening and the second through hole of the planarization layer on the substrate of the thin film transistor substrate overlap with each other, and the overlapping position The area can be between 4 and 49 square microns. Therefore, compared with the existing technology of etching another through hole in a larger through hole, the overlapping area of the first through hole and the second through hole can be smaller than that of the through hole in the prior art, and there is no Alignment of another via in a large via. In addition, because the overlapping area is smaller than the area of the through hole in the prior art, when the black matrix layer is arranged on the scanning line, the relative coverage width can be smaller than that in the prior art, so the display panel and the display device can also be improved. pixel aperture ratio.

The above description is exemplary only, not limiting. Any equivalent modifications or changes without departing from the spirit and scope of the present invention should be included in the claims.

Claims (9)

1. A display panel, comprising:

a substrate;

a scanning line, disposed on the substrate and having a concave portion;

a data line arranged on the substrate, wherein the data line and the scanning line are arranged in a staggered manner;

a thin film transistor disposed on the substrate and having a gate and a drain, the gate being electrically connected to the scan line, the drain being electrically connected to the data line;

a first insulating layer disposed on the drain electrode and exposing a portion of the drain electrode, wherein the recess of the scan line is disposed corresponding to the exposed portion of the drain electrode, and the first insulating layer has a through hole;

a planarization layer disposed on the first insulating layer, the planarization layer having another through hole, wherein the recess is correspondingly disposed at the overlapping position of the through hole and the another through hole; and

and the pixel electrode layer is arranged on the planarization layer and is electrically connected with the exposed part of the drain electrode.

2. The display panel according to claim 1, wherein the first insulating layer has an opening.

3. The display panel according to claim 2, wherein the opening of the first insulating layer has a step shape.

4. The display panel according to claim 2, wherein the opening of the first insulating layer has a slope.

5. The display panel according to claim 2, wherein the pixel electrode layer is filled in the opening and electrically connected to the portion of the drain electrode exposed.

6. The display panel of claim 1, wherein the another via hole has a first sidewall, and a portion of the pixel electrode layer is in direct contact with the first sidewall.

7. The display panel of claim 1, further comprising:

a second insulating layer disposed on the planarization layer.

8. The display panel of claim 7, wherein the another via has a second sidewall, and a portion of the second insulating layer is on and in direct contact with the second sidewall.

9. The display panel according to claim 8, wherein the second insulating layer is connected to the first insulating layer.

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